CN100350614C - Rram存储器单元电极及其制造方法 - Google Patents

Rram存储器单元电极及其制造方法 Download PDF

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CN100350614C
CN100350614C CNB2004100104308A CN200410010430A CN100350614C CN 100350614 C CN100350614 C CN 100350614C CN B2004100104308 A CNB2004100104308 A CN B2004100104308A CN 200410010430 A CN200410010430 A CN 200410010430A CN 100350614 C CN100350614 C CN 100350614C
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CN1641881A (zh
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许胜籐
潘威
张风燕
庄维佛
李延凯
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Allogeneic Development Co ltd
Eicke Fout Intellectual Property Co
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0007—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising metal oxide memory material, e.g. perovskites
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
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    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/841—Electrodes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/883—Oxides or nitrides
    • H10N70/8836—Complex metal oxides, e.g. perovskites, spinels
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/30—Resistive cell, memory material aspects
    • G11C2213/31—Material having complex metal oxide, e.g. perovskite structure
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70—Resistive array aspects
    • G11C2213/77—Array wherein the memory element being directly connected to the bit lines and word lines without any access device being used

Abstract

在其中具有工作结而其上具有金属栓的硅衬底上形成的RRAM存储单元，包括第一抗氧化层、第一难熔金属层、CMR层、第二难熔金属层以及第二抗氧化层。制造多层电极RRAM存储单元的方法包括准备硅衬底；在衬底上形成从N+结和P+结组成的结组中选出的结；在该结上沉积金属栓；在金属栓上沉积第一抗氧化层；在该第一抗氧化层上沉积第一难熔金属层；在该第一难熔金属层上沉积CMR层；在该CMR层上沉积第二难熔金属层；在该第二难熔金属层上沉积第二抗氧化层；以及完成该RRAM存储单元。

Description

RRAM存储器单元电极及其制造方法
技术领域
本发明涉及一种用于非易失性存储器阵列的薄膜电阻存储器器件，更具体地涉及RRAM存储器单元的多层电极。
背景技术
现在没有商业可用的RRAM器件，然而，使用Pt，Au，Ag，Al，Ti和TiN电极的实验性器件已经被开发出来了。Pt、An和Ag电极设备具有良好的持久力，然而，由这些材料形成的电极不能用传统的集成电路蚀刻工艺来蚀刻。实验性器件通过使用浅掩模或化学机械抛光(CMP)工艺制成，它们对于亚微米和大型存储器件的制造既不合适而且成本效率不高。而在实验器件中使用的另外的电极材料表现出低可靠度和低持久力。在2000年5月的Apllied PhysicsLetters，Vol.76，#19，p2749-2751刊登了Liu等人的“Electrical-pulse-inducedreversible resistance change effect in magnetoresistive films(在磁阻薄膜中的电脉冲引起的可逆阻抗变化效应)”。该发明提供可靠的电极结构以提升器件可靠度、持久力，而同时减少制造成本。
发明内容
在其中具有工作结而其上具有金属栓的硅衬底上形成的RRAM存储设备，包括第一抗氧化层；第一难熔金属层；CMR层；第二难熔金属层；和第二抗氧化层。
一种制造多层电极RRAM存储单元的方法，包括准备硅衬底；在该衬底中形成选自由N+结和P+结组成的结组中的结；在结上沉积金属栓；在金属栓上沉积第一抗氧化层；在第一抗氧化层上沉积第一难熔金属层；在第一难熔金属层上沉积CMR层；在该CMR层上沉积第二难熔金属层；在第二难熔金属层上沉积第二抗氧化层；并完成RRAM存储单元。
本发明的一个目的是提供一种可靠的电极以改进器件的可靠性和器件的寿命，并且可以更经济地生产器件。
本发明的另一个目的是提供抗氧化的多层电极。
本发明更进一步的目的是提供用于RRAM的金属电极。
提供本发明的说明和目的以快速理解本发明的本质。结合附图并参考下面对本发明优选实施例的详细描述可以对本发明更透彻地理解。
附图说明
图1描述了RRAM存储单元的电阻特性。
图2描述了本发明的RRAM多层电极。
图3为本发明的方法的方块图。
具体实施方式
实验数据证明，在编程期间，在阴极附近的RRAM材料的电阻系数转变成高电阻系数状态，同时阳极附近的转变成低电阻系数状态。电阻系数的转变发生在窄电压脉冲施加到该器件的瞬间，它导致在阴极附近有电压降(voltagedrop)。电阻系数的变化需要清晰的起始电压(onset voltage)。实验也发现该材料需要一定的含氧量，因为当含氧量太低时，没有电阻系数的变化。
如果RRAM存储单元的电极不具有抗氧化性，该电极将在制造过程中的温度处理期间被氧化，或者在正常操作中会被电流-电压产生的热量逐渐氧化。电极发生氧化的同时，氧从RRAM材料扩散到电极中，导致氧缺乏区域。氧化电极和氧缺乏区域都具有高电阻。另外，如图1所示的氧缺乏区域不能被电脉冲转变成低电阻状态。因此，施加到阴极的有效电压是这样给定的：
V EFF = V C - IR - Q DS C OD
其中I是流过该器件的电流，R存储器材料的是氧化电极和氧缺乏区域中的串联电阻，QDS是在耗尽区的净电荷(net charge)而COD是氧缺乏区域电容和氧化电极电容的串联电容。上述等式证明有效编程电压可以通过电极的氧化而明显地减少。
如上所述，亚微米尺寸的Pt电极可以通过化学机械抛光(CMP)处理来形成。缺点在于成本。CMP需要晶片表面(wafer surface)的平面化、形成氧化物沟以及CMP处理。另外，Pt不能阻碍氧的扩散，并且氧的丢失和氧缺乏区域的形成仍然会发生。
RRAM电极必须不跟电阻材料反应。优选使用贵金属材料。然而，大多数贵金属不能阻止氧扩散。因此，通常在10需要多层电极，如图2所示。图2描述了一个衬底12，其中形成N-结或P+结，金属栓16通过氧化层从结16延伸到多层电极RRAM存储单元18。RRAM存储单元18包括抗氧化材料层20和28，难熔金属层22和26，以及一金属层，特别地，在优选实施例中，是超巨磁阻(CMR)材料层24。
层20、28是由抗氧化材料，例如TiN、TaN、TiAlNx、TaAlNx、TaSiN、TiSiN和RuTiN形成的。层20、28(本文中也分别称为第一和第二抗氧化层)的厚度大约分别为50nm～300nm。层20、28也可以使用任何传统的干法蚀刻工艺来蚀刻。
层22、26由例如Pt、Ir、IrO2、Ru、RuO2、Au、Ag、Rh、Pd、Ni和Co的难熔金属形成。层22、26(本文中也分别称为第一和第二难熔金属层)的厚度约为3nm～50nm。因为层22、26非常薄，它们可以使用没有过多的掩模材料的劣化(degradation)和蚀刻材料的再沉积的局部溅射工艺进行干法蚀刻。虽然优选阴极和阳极使用双金属电极，如图2所描绘的，但是对于某些应用仅有一个双金属电极的RRAM单元也是可靠的。
CMR层24可以由任何CMR材料(例如PCMO(Pr0.7Ca0.3MnO3)、LPCMO)或者高温超导材料等形成，并且可以通过溅射、金属有机化学气相沉积(MOCVD)或金属氧化物沉积(MOD)(包括旋涂)来沉积。CMR层的厚度约为50nm～300nm。
参照图3，30概括性示出了本发明的方法，并且该方法包括制备衬底32，并在其中形成N+结或P+结34。金属栓16通过溅射沉积36，它可以由钨或铜形成。金属栓16被图形化并蚀刻，并且然后被接下来在金属栓16上沉积的氧化物层包围。
在沉积第一抗氧化层38之后第一难熔金属层40的沉积。然后沉积CMR层42。在沉积第二难熔金属层44之后沉积第二抗氧化层46。然后根据公知技术完成RRAM存储单元48。
因此，已经公开了RRAM存储单元电极的制造方法。可以理解不脱离所附的权利要求书中定义的本发明的范围，进行进一步的变化和修改是可能的。

Claims (14)

1.一种形成在其中具有工作结且其上形成有金属栓的硅衬底上的RRAM存储单元，依次包括：
第一抗氧化层；
第一难熔金属层；
CMR层；
第二难熔金属层；
第二抗氧化层。
2.如权利要求1的RRAM存储单元，其中抗氧化层是由从TiN、TaN、TiAlNx、TaAlNx、TaSiN、TiSiN和RuTiN组成的材料组中选择的材料形成的。
3.如权利要求2的RRAM存储单元，其中抗氧化层的厚度为50nm～300nm。
4.如权利要求1的RRAM存储单元，其中难熔金属层是由从Pt、Ir、IrO2、Ru、RuO2、Au、Ag、Rh、Pd、Ni和Co组成的材料组中选择的材料形成的。
5.如权利要求4的RRAM存储单元，其中难熔金属层的厚度为3nm～50nm。
6.如权利要求1的RRAM存储单元，其中该CMR层是由从CMR材料和高温超导材料组成的材料组中选取的材料形成的。
7.如权利要求6的RRAM存储单元，其中该CMR层厚度为50nm～300nm。
8.一种制造多层电极RRAM存储单元的方法，包括：
准备硅衬底；
在硅衬底中形成选自由N+结和P+结组成的结组中的结；
在该结上沉积金属栓；
在金属栓上沉积第一抗氧化层；
在该第一抗氧化层上沉积第一难熔金属层；
在该第一难熔金属层上沉积CMR层；
在该CMR层上沉积第二难熔金属层；
在该第二难熔金属层上沉积第二抗氧化层；
完成该RRAM存储单元。
9.如权利要求8的方法，其中所述沉积抗氧化层包括沉积从TiN、TaN、TiAlNx、TaAlNx、TaSiN、TiSiN和RuTiN组成的材料组中选出的材料。
10.如权利要求9的方法，其中所述沉积抗氧化层包括沉积厚度为50nm～300nm的抗氧化层。
11.如权利要求8的方法，其中所述沉积难熔金属层包括沉积从Pt、Ir、IrO2、Ru、RuO2、Au、Ag、Rh、Pd、Ni和Co组成的材料组中选出的材料。
12.如权利要求11的方法，其中所述沉积难熔金属层包括沉积厚度为3nm～50nm的难熔金属层。
13.如权利要求8的方法，其中所述沉积CMR层包括沉积选自PCMO、LPCMO和高温超导材料组成的材料组中的CMR材料。
14.如权利要求13的方法，其中所述沉积CMR层包括沉积厚度为50nm～300nm的CMR材料层。
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