CN100356560C - 半导体装置及其制造方法 - Google Patents
半导体装置及其制造方法 Download PDFInfo
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Abstract
一种半导体装置(100),它具有各引线端子(11a~11h),在各引线端子的露出部分(12a~12h)的前端面(13a~13h)形成切口面(15a~15h),切口面(15a~15h)上实施了能够提高焊料浸润性的电镀。
Description
技术领域
本发明涉及装有半导体元件的半导体装置及该半导体装置的制造方法。
背景技术
以前,如图8所示,提出了采用引线框架的半导体装置200。这种半导体装置200是用树脂219将引线框架210的装有半导体元件侧和各引线端子211间两者模压而成。各引线端子211用接合线(bonding wire)217与半导体元件搭载部216上的半导体元件218连接。又,对各引线端子211的从树脂219露出的部分进行电镀处理,以使得焊料容易附着。
发明内容
但是,引线框架210具有的各引线端子211的前端面213是引线端子211被切断形成的面,在电镀处理后被切断的引线端子211,其前端面213上失去预先实施的电镀,焊锡难以附着。
鉴于存在这样的问题,本发明以提供容易在引线端子的前端面附着焊料的半导体装置及该半导体装置的制造方法为课题。
为了解决上述课题,本发明的半导体装置在具有多个引线端子的引线框架上搭载半导体元件,多个引线端子分别和半导体元件电气连接,搭载半导体元件的引线框架的搭载侧与各引线端子间两者用树脂模压形成,其特征在于,所述引线端子具有没有被所述树脂覆盖的上表面,所述树脂在与所述上表面对应的所述引线端子的侧面之间模压成型,引线端子的前端面用比引线框架材料的焊料浸润性好的金属进行电镀,所述引线端子的前端面由切断面和与所述切断面连续的凹面构成,在所述凹面上实施电镀,焊料可从所述凹面爬到所述上表面。
这样,半导体装置由于对多个引线端子的各个露出部分的前端面进行电镀使其提高了焊料浸润性,引线端子的前端面容易附着焊料。
又,本发明的半导体装置,其特征在于,切断面上没有实施电镀。
又,电镀的金属是金、银、钯以及它们的合金中的任一种。
又,引线端子间的树脂的前端面的位置与引线端子的切断面的位置一致。
又,本发明的半导体装置制造方法,其特征在于,在多个引线端子上预先分别形成通孔,在所述通孔的内壁面实施能够提高焊料浸润性的电镀的引线框架上搭载半导体元件,所述多个引线端子分别与所述半导体元件电连接,将搭载半导体元件的上述引线框架的搭载侧与各引线端子间两者用树脂模压形成使所述通孔露出,所述引线端子具有没被所述树脂覆盖的上表面,所述树脂在与所述上表面对应的所述引线端子的侧面之间模压成型,在形成所述通孔的位置将所述多个引线端子分别切断,以此制造半导体装置,所述半导体装置形成为以所述通孔的内壁面各自的一部分作为所述多个引线端子的前端面的一部分,所形成的所述引线端子的前端面由切断面和与所述切断面连续的凹面构成,在所述凹面上实施电镀,焊料可从所述凹面爬到所述上表面。
这样,由于在通过切断多个引线端子而形成的前端面上实施了能够提高焊料浸润性的电镀,能够得到容易在引线端子的前端面进行焊接的半导体装置。
又,本发明的半导体装置制造方法,其特征在于,在将搭载半导体元件的引线框架的搭载侧与各引线端子间两者用树脂模制时,所述通孔利用模具挡塞。
又,本发明的半导体装置制造方法,其特征在于,所述引线端子间的树脂的前端面的位置与所述引线端子的所述切断面的位置一致。
附图说明
图1是本实施形态的半导体装置100的立体图;
图2是本实施形态的半导体装置100的剖面图;
图3是本实施形态的半导体装置100具有的引线端子11b的露出部分12b的放大图;
图4是本实施形态的半导体装置100的引线端子11a、11b被连接于配线图形2a、2b的情况的示意图;
图5是本实施形态的半导体装置100中使用的引线框架20的结构图;
图6是表示本实施形态的半导体装置100的制造工艺的流程图;
图7是本实施形态的半导体装置100的树脂19用模具50成型时的情况的示意图;
图8是已有的半导体装置200的结构图。
具体实施方式
以下参照附图对本发明的最佳实施形态进行详细说明。为了使得说明容易理解,在各附图中对相同的结构要件尽可能使用相同的参考符号,并省略重复说明。
首先,对本发明的半导体装置的实施形态进行说明。图1是本实施形态的半导体装置100的立体图。图2是沿着与图1所示的引线框架10垂直,通过引线端子11b和引线端子11f的线切断时的(沿图1所示的虚线切断时的)半导体装置100的剖面图。
下面用图1和图2对实施形态的半导体装置进行说明。
半导体装置100由引线框架10、接合线17b、17f、半导体元件18以及树脂19构成。
引线框架10是金属制的框架,使用例如铜合金或铁合金制成。该引线框架10包含8个引线端子11a~11h和半导体元件搭载部16。
半导体元件18是光半导体元件或IC芯片等,用粘接剂粘接搭载于半导体元件搭载部16上。该半导体元件18,其表面上形成接合区(未图示)。
半导体装置100具有多条这种接合线17b、17f等。接合线17b、17f等是细金线。接合线17b、17f等的一端连接于半导体元件18的表面上的某一接合区,另一端连接于某一引线端子11a~11h。
树脂19具有绝缘性,将各引线端子11a~11h的一部分、半导体元件搭载部16、接合线17b、17f等、以及半导体元件18加以密封。又,树脂19也能够防止各接合线17b、17f等相互之间发生短路。
树脂19将搭载半导体元件18的引线框架10的搭载侧与各引线端子11a~11h间模制成型。又,树脂19在模制成型时使得引线框架10的非搭载侧也不露出引线框架10。但是,引线框架10的非搭载侧的树脂19的厚度比引线框架10的搭载侧的树脂19的厚度薄。这是由于在安装于基板时引线端子11a~11h不弯折,不需要将引线端子11a~11h做得长。又,引线端子11a~11h之间的树脂19的厚度大致与引线端子11a~11h的厚度相同。
引线框架10所具有的各引线端子11a~11h的周围,其接近于半导体元件18的一侧用树脂19覆盖,各引线端子11a~11h的离半导体元件18远的一侧形成露出部分12a~12h。
下面用图3对图2所示的引线端子11b的露出部分12b进行说明。
图3是本实施形态的半导体装置100所具有的引线端子11b的露出部分12b的放大图。引线端子11b包含露出部分12b,露出部分12b在前端包含前端面13b。还有,前端面13b由切断面14b和与该切断面14b连续的切口面(凹面)15b构成。
切口面15b是从引线端子11b的露出部分12b的前端切下一个切口形成的。还有,切口面15b由于是从露出部分12b的前端切下一个切口形成的面,因此有这样的名称。
在包含引线端子11b的引线框架10的表面上进行电镀。还有,这里的电镀用焊料浸润性比引线框架10的金属材料好的金属,也即能够提高将半导体元件18和引线端子11a~11h加以连接的接合线17b、17f等的连接性和焊料浸润性两者的金属。具体地说,是金、银、钯以及它们的合金等,也可以是这些金属和合金的多层叠层结构。
前端面13b具有电镀的部分和没有电镀的部分。电镀的部分是切口面15b,没有电镀的部分是切断面14b。因此,切断面14b的焊料浸润性不好,而切口面15b的焊料浸润性良好。
这样在前端面13b上具有电镀的面和没有电镀的面是因为在制造上对整个引线框架10进行电镀之后,才将各引线端子11a~11h切断。因此,由于切断而形成的切断面14b未实施电镀。
上面用图3说明了引线端子11b的露出部分12b,该露出部分12b的结构与其它引线端子11a、11c~11h的露出部分12a、12c~12h相同。因此,引线端子11a、11c~11h的露出部分12a、12c~12h的说明省略。
这样的半导体装置100的引线端子11a~11h与基板上的配线图形电气连接。为将引线端子11a~11h连接于配线图形上,首先将半导体装置100设置于基板上。然后,对引线端子11a~11h的前端面13a~13h和基板的配线图形进行焊接。
图4是本实施形态的半导体装置100引线端子11a、11b被连接于配线图形2a、2b上的情况的示意图。还有,在图4中,省略了将引线端子11c~11h连接于配线图形2c~2h时的情况。
如图4所示,尽管焊料1a、1b焊在引线端子11a、11b的前端面13a、13b和基板上的配线图形2a、2b上,但还是爬到了引线端子11a、11b的露出部分12a、12b的上表面。这由于对切口面15a、15b实施了焊料浸润性良好的电镀。总之,焊料浸润性良好的电镀有助于焊料1a、1b爬上露出部分12a、12b上面。
假如没有该切口面15a、15b,不对前端面13a、13b实施电镀,则焊料1a、1b不能够爬上引线端子11a、11b的露出部分12a、12b的上表面。
这样,引线端子11a、11b由于在前端面13a、13b上具有实施了焊料浸润性良好的电镀的切口面15a、15b,所以容易在引线端子11a、11b的前端面13a、13b焊接焊料1a、1b。又,焊料1a、1b爬上露出部分12a、12b的上表面,引线端子11a、11b与基板的配线图形2a、2b得到可靠连接。还有,上述说明对于引线端子11c~11h与配线图形2c~2h的连接也相同。
半导体装置100由于在引线端子11a~11h的前端面13a~13h具有实施过电镀的切口面15a~15h,因此,引线端子11a~11h的前端面13a~13h的焊料浸润性良好,容易在引线端子11a~11h的前端面13a~13h焊接。
下面对引线框架本身的结构进行详细说明。
图5是本实施形态的半导体装置100中使用的引线框架20的结构图。还有,8个引线端子21a~21h与上述8个引线端子11a~11h只是形状不同,因此省略其说明。又,对半导体元件搭载部16也省略其说明。
引线框架20除了包含8个引线端子21a~21h和半导体元件搭载部16外,还包含哑区(dumb)29。该引线框架20是金属制品,用例如铜合金或铁合金制造。
引线框架20具有的8个引线端子21a~21h分别形成通孔27a~27h。该通孔27a~27h为椭圆状。该引线端子21a~21h各个都不切断。
哑区29连接于引线端子21a~21h,模压时流入各引线端子21a~21h之间的树脂19在哑区29位置上会受到阻止。
如上所述形状的引线框架20,其周围全部施加电镀,理想的是电镀金、银或钯,或这些金属的合金。又,为了容易接线,也实施这样的电镀。
又,由于对引线框架20的周围全部进行电镀,对通孔27a~27h也进行了电镀。
现在分别将8个引线端子21a~21h在形成通孔27a~27h的位置(例如图5的虚线所示的A位置)切断。于是,8个引线端子21a~21h分别形成与用图3进行的说明相同的前端面13a~13h。总之,通孔27a~27h的内壁面28a~28h的一部分(靠近半导体元件18的一侧)形成与图3所示的切口面15a~15h相同的结构,引线端子21a~21h被切断的部分形成与图3所示的切断面14a~14h相同的结构。
因此,切断形成的8个引线端子21a~21h的切断面14a~14h没有实施电镀,切口面15a~15h实施了电镀。
如上所述,引线框架20分别在8个引线端子21a~21h形成通孔27a~27h,该通孔27a~27h的内壁面28a~28h施加了电镀,因此,能够得到引线端子的前端面容易焊上焊料的半导体装置100。
下面对本发明的半导体装置的制造方法的实施形态进行说明。半导体装置100的制造中使用上述引线框架20。
图6是表示本实施形态的半导体装置100的制造工艺的流程图。首先,在用图5说明的引线框架20的半导体元件搭载部16上搭载半导体元件18(S1)。该半导体元件18用粘接剂连接、搭载于半导体元件搭载部16上。
然后进行接线(S2)。在这里,半导体元件18具有的结合区和引线端子21a~21h利用接合线17b、17f等连接。还有,在这里,半导体元件18与引线端子21a~21h的连接用引线接合,但是也不限于此,只要是电连接就可以。从而,也有不用接合线17b、17f等连接的引线端子21a~21h,接合线17b、17f等条数不限于8条。
下面接着进行模压(S3)。进行模压时使用模具。模具的样子用图7说明。
图7是本实施形态的半导体装置100的树脂19用模具50成型时的情况的示意图。引线框架20上搭载半导体元件18,将半导体元件18与引线端子21a~21h电连接的部分被置于由上模50a与下模50b形成的空间内。然后,将树脂19充填于模具50形成的空间中。
这时,上模50a与下模50b将引线框架20的引线端子21a~21h的一部分挟入。又,上模50a与下模50b将引线端子21a~21h挟入使通孔27a~27h被堵塞住。被挟入的引线端子21a~21h的一部分没有被树脂19封住。这是由于树脂19没有流到上模50a和下模50b挟入的引线端子21a~21h的一部分上。从而,挟入引线框架20,使引线端子21a~21h的露出部分12a~12h形成,而且防止形成于引线端子21a~21h上的通孔27a~27h被树脂19所充填。
又,树脂19流入引线端子21a~21h之间。这是因为模具50不能把引线端子21a~21h之间也挟入其中。又,流入引线端子21间的树脂19在哑区29的位置上被堵塞住,不会从其流出。
还有,树脂19也流入引线框架20的没有搭载半导体元件18的一侧。但是,不会流入被模具50挟入的引线端子21的一部分。流入该没有搭载半导体元件18的一侧的树脂19的量比流入搭载该元件的一侧的树脂19的量少。
树脂19固化后,模压后的包含各构成要素的树脂19所密封的密封件被从成型模具50中取出。该密封件在接合线17b、17f等没有相互接触的情况下密封,又,接合线17b、17f等被密封住没有从树脂19中伸出。
接着,将各引线端子21a~21h切断(S4)。引线端子21a~21h在图5虚线所示的A位置切断。换句话说,引线端子21在形成通孔27a~27h的位置上被切断。还有,树脂19流入引线端子21a~21h之间,因此,流出的树脂19与各引线端子21a~21h一起被切断。切断是使用可旋转的薄钻石刀的剪切装置或剪床式切断装置进行的,以使引线端子21a~21h与树脂19的粘接部(连接部分)不受到负载。利用这种装置,将各引线端子21a~21h与各引线端子21a~21h之间的树脂19一起切断形成半导体装置100。
还有,图5的虚线所示的A位置是形成通孔27a~27h的位置。因此,切断形成的半导体装置100的引线端子21a~21h的前端面13a~13h上留下了通孔27a~27h的内壁面28a~28h的一部分。该通孔27a~27h的内壁面28a~28h的一部分形成切口面15a~15h。还有,对该切口面15a~15h实施了电镀。
通过以上所述步骤,可以得到引线端子21a~21h的前端面具备通孔27a~27h的内壁面28a~28h的一部分、即切口面15a~15h的半导体装置100。该切口面15a~15h上实施了电镀,因此,引线端子21a~21h的前端面13a~13h的焊料浸润性良好。因此,能够得到容易在引线端子21a~21h的前端面13a~13h焊接的半导体装置100。
如上所述,本实施形态中,通孔27a~27h采用椭圆形状,但是,并不限于此,也可以采用圆形、长椭圆形、菱形、矩形等其他形状。
本发明的半导体装置由于在引线端子的前端面上实施了能够提高焊料浸润性的电镀,所以容易在引线端子的前端面进行焊接。
又,本发明的半导体装置制造方法,由于在利用切断多个引线端子形成的前端面上实施能够提高焊料浸润性的电镀,因此能够得到容易在引线端子的前端面进行焊接的半导体装置。
工业应用性
本发明可以应用于搭载半导体元件的半导体装置及该半导体装置的制造方法。
Claims (7)
1.一种半导体装置,在具有多个引线端子的引线框架上搭载有半导体元件,各所述多个引线端子分别和半导体元件电连接,搭载所述半导体元件的所述引线框架的搭载侧与各引线端子间两者用树脂模压成型,其特征在于,
所述引线端子具有没有被所述树脂覆盖的上表面,所述树脂在与所述上表面对应的所述引线端子的侧面之间模压成型,
所述引线端子的前端面用比所述引线框架的材料焊料浸润性好的金属进行电镀,
所述引线端子的前端面由切断面和与所述切断面连续的凹面构成,在所述凹面上实施电镀,焊料可从所述凹面爬到所述上表面。
2.根据权利要求1所述的半导体装置,其特征在于,所述切断面上没有实施电镀。
3.根据权利要求1所述的半导体装置,其特征在于,所述电镀使用的是金、银、钯以及它们的合金中的任一种。
4.根据权利要求1所述的半导体装置,其特征在于,所述引线端子间的树脂的前端面的位置与所述引线端子的所述切断面的位置一致。
5.一种半导体装置制造方法,其特征在于,所述方法包括:
在多个引线端子上预先分别形成通孔、在所述通孔的内壁面实施能够使焊料浸润性得到提高的电镀的引线框架上,搭载半导体元件;
各所述多个引线端子分别与所述半导体元件电连接;
将搭载所述半导体元件的所述引线框架的搭载侧与各引线端子间两者用树脂模压成型,使所述通孔露出;
所述引线端子具有没被所述树脂覆盖的上表面,所述树脂在与所述上表面对应的所述引线端子的侧面之间模压成型;
在形成所述通孔的位置将各所述多个引线端子分别切断,以此制造半导体装置;
所述半导体装置形成为以所述通孔的内壁面各自的一部分作为所述多个引线端子的前端面的一部分,所形成的所述引线端子的前端面由切断面和与所述切断面连续的凹面构成,在所述凹面上实施电镀,焊料可从所述凹面爬到所述上表面。
6.根据权利要求5所述的半导体装置制造方法,其特征在于,在将搭载所述半导体元件的所述引线框架的搭载侧与各引线端子间两者用树脂模压成型时,所述通孔利用模具堵塞。
7.根据权利要求5所述的半导体装置制造方法,其特征在于,所述引线端子间的树脂的前端面的位置与所述引线端子的所述切断面的位置一致。
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Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02302068A (ja) * | 1989-05-16 | 1990-12-14 | Nec Corp | トランスファーモールド型混成集積回路 |
JPH0472649U (zh) * | 1990-11-06 | 1992-06-26 | ||
JPH10207467A (ja) * | 1997-01-27 | 1998-08-07 | Citizen Electron Co Ltd | 表面実装型電磁発音体及びその製造方法 |
CN1246963A (zh) * | 1997-02-10 | 2000-03-08 | 松下电子工业株式会社 | 树脂封装型半导体装置及其制造方法 |
JP2001035961A (ja) * | 1999-07-21 | 2001-02-09 | Sony Corp | 半導体装置及びその製造方法 |
Family Cites Families (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0793338B2 (ja) | 1985-11-11 | 1995-10-09 | スタンレー電気株式会社 | ミニモールド型ledの製造方法 |
KR960006710B1 (ko) | 1987-02-25 | 1996-05-22 | 가부시기가이샤 히다찌세이사꾸쇼 | 면실장형 반도체집적회로장치 및 그 제조방법과 그 실장방법 |
JPH03108745A (ja) | 1989-09-22 | 1991-05-08 | Seiko Epson Corp | 半導体装置 |
JPH0472649A (ja) | 1990-07-12 | 1992-03-06 | Nec Corp | 半導体チップ収納ケース |
JPH0555438A (ja) * | 1991-08-26 | 1993-03-05 | Rohm Co Ltd | 電子部品のリード端子構造 |
US5767580A (en) * | 1993-04-30 | 1998-06-16 | Lsi Logic Corporation | Systems having shaped, self-aligning micro-bump structures |
JPH07111307A (ja) | 1993-10-12 | 1995-04-25 | Hitachi Ltd | 半導体装置 |
JP3541491B2 (ja) * | 1994-06-22 | 2004-07-14 | セイコーエプソン株式会社 | 電子部品 |
JPH0864743A (ja) | 1994-08-24 | 1996-03-08 | Sony Corp | リードフレームとこれを用いた半導体装置の製造方法 |
JP3507251B2 (ja) * | 1995-09-01 | 2004-03-15 | キヤノン株式会社 | 光センサicパッケージおよびその組立方法 |
WO1998006063A1 (fr) * | 1996-08-02 | 1998-02-12 | Solaic | Carte a circuit integre a connexion mixte |
DE19639025C2 (de) * | 1996-09-23 | 1999-10-28 | Siemens Ag | Chipmodul und Verfahren zur Herstellung eines Chipmoduls |
KR100254267B1 (ko) * | 1997-03-20 | 2000-05-01 | 유무성 | 비.지.에이패키지및그제조방법 |
FR2778769B1 (fr) * | 1998-05-15 | 2001-11-02 | Gemplus Sca | Carte a circuit integre comportant un bornier d'interface et procede de fabrication d'une telle carte |
JP3553405B2 (ja) * | 1999-03-03 | 2004-08-11 | ローム株式会社 | チップ型電子部品 |
JP2001077268A (ja) | 1999-06-28 | 2001-03-23 | Matsushita Electronics Industry Corp | 樹脂封止型半導体装置およびその製造方法 |
JP3644859B2 (ja) * | 1999-12-02 | 2005-05-11 | 沖電気工業株式会社 | 半導体装置 |
JP2002319011A (ja) * | 2001-01-31 | 2002-10-31 | Canon Inc | 半導体装置、半導体装置の製造方法及び電子写真装置 |
-
2001
- 2001-09-27 JP JP2001297620A patent/JP2003100980A/ja active Pending
-
2002
- 2002-09-27 CN CNB028188616A patent/CN100356560C/zh not_active Expired - Fee Related
- 2002-09-27 KR KR1020047003953A patent/KR100798543B1/ko not_active IP Right Cessation
- 2002-09-27 DE DE10297264T patent/DE10297264B4/de not_active Expired - Fee Related
- 2002-09-27 WO PCT/JP2002/010090 patent/WO2003030259A1/ja active Application Filing
- 2002-09-27 US US10/490,980 patent/US7098081B2/en not_active Expired - Fee Related
Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH02302068A (ja) * | 1989-05-16 | 1990-12-14 | Nec Corp | トランスファーモールド型混成集積回路 |
JPH0472649U (zh) * | 1990-11-06 | 1992-06-26 | ||
JPH10207467A (ja) * | 1997-01-27 | 1998-08-07 | Citizen Electron Co Ltd | 表面実装型電磁発音体及びその製造方法 |
CN1246963A (zh) * | 1997-02-10 | 2000-03-08 | 松下电子工业株式会社 | 树脂封装型半导体装置及其制造方法 |
JP2001035961A (ja) * | 1999-07-21 | 2001-02-09 | Sony Corp | 半導体装置及びその製造方法 |
Also Published As
Publication number | Publication date |
---|---|
US7098081B2 (en) | 2006-08-29 |
DE10297264T5 (de) | 2004-09-16 |
DE10297264B4 (de) | 2008-10-30 |
CN1559085A (zh) | 2004-12-29 |
KR100798543B1 (ko) | 2008-01-28 |
KR20040041164A (ko) | 2004-05-14 |
JP2003100980A (ja) | 2003-04-04 |
US20050003582A1 (en) | 2005-01-06 |
WO2003030259A1 (fr) | 2003-04-10 |
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