CN100377062C - 具有两条时钟线和存储装置的存储系统 - Google Patents
具有两条时钟线和存储装置的存储系统 Download PDFInfo
- Publication number
- CN100377062C CN100377062C CNB2005101064938A CN200510106493A CN100377062C CN 100377062 C CN100377062 C CN 100377062C CN B2005101064938 A CNB2005101064938 A CN B2005101064938A CN 200510106493 A CN200510106493 A CN 200510106493A CN 100377062 C CN100377062 C CN 100377062C
- Authority
- CN
- China
- Prior art keywords
- clock
- memory
- separately
- storage
- clock signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
- 230000001360 synchronised effect Effects 0.000 claims abstract description 15
- 230000005055 memory storage Effects 0.000 claims description 84
- 238000003860 storage Methods 0.000 claims description 31
- 230000002457 bidirectional effect Effects 0.000 claims description 3
- 230000005540 biological transmission Effects 0.000 description 3
- 230000008878 coupling Effects 0.000 description 2
- 238000010168 coupling process Methods 0.000 description 2
- 238000005859 coupling reaction Methods 0.000 description 2
- 241001269238 Data Species 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000002349 favourable effect Effects 0.000 description 1
- 230000008676 import Effects 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- 230000000644 propagated effect Effects 0.000 description 1
Images
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/02—Disposition of storage elements, e.g. in the form of a matrix array
- G11C5/04—Supports for storage elements, e.g. memory modules; Mounting or fixing of storage elements on such supports
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
- G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
- G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
- G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
- G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
- G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
- G11C11/4076—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/06—Arrangements for interconnecting storage elements electrically, e.g. by wiring
- G11C5/063—Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/22—Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
- G11C7/222—Clock generating, synchronizing or distributing circuits within memory device
Abstract
Description
Claims (12)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/955177 | 2004-09-30 | ||
US10/955,177 US7173877B2 (en) | 2004-09-30 | 2004-09-30 | Memory system with two clock lines and a memory device |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1755606A CN1755606A (zh) | 2006-04-05 |
CN100377062C true CN100377062C (zh) | 2008-03-26 |
Family
ID=36089010
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2005101064938A Expired - Fee Related CN100377062C (zh) | 2004-09-30 | 2005-09-30 | 具有两条时钟线和存储装置的存储系统 |
Country Status (3)
Country | Link |
---|---|
US (1) | US7173877B2 (zh) |
CN (1) | CN100377062C (zh) |
DE (1) | DE102005042269B4 (zh) |
Families Citing this family (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7965530B2 (en) * | 2005-05-21 | 2011-06-21 | Samsung Electronics Co., Ltd. | Memory modules and memory systems having the same |
KR101048380B1 (ko) * | 2005-05-21 | 2011-07-12 | 삼성전자주식회사 | 메모리 모듈 장치 |
KR100845525B1 (ko) * | 2006-08-07 | 2008-07-10 | 삼성전자주식회사 | 메모리 카드 시스템, 그것의 데이터 전송 방법, 그리고반도체 메모리 장치 |
KR100909805B1 (ko) | 2006-09-21 | 2009-07-29 | 주식회사 하이닉스반도체 | 멀티포트 메모리 장치 |
US8031539B2 (en) * | 2008-10-09 | 2011-10-04 | Qimonda Ag | Memory device and memory system comprising a memory device and a memory control device |
KR102029682B1 (ko) * | 2013-03-15 | 2019-10-08 | 삼성전자주식회사 | 반도체 장치 및 반도체 패키지 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN1209630A (zh) * | 1997-08-25 | 1999-03-03 | 日本电气株式会社 | 半导体存储装置 |
US5987576A (en) * | 1997-02-27 | 1999-11-16 | Hewlett-Packard Company | Method and apparatus for generating and distributing clock signals with minimal skew |
CN1244018A (zh) * | 1998-08-04 | 2000-02-09 | 三星电子株式会社 | 同步猝发半导体存储器件 |
US20040057331A1 (en) * | 2001-05-25 | 2004-03-25 | Micron Technology, Inc. | Synchronous mirror delay with reduced delay line taps |
Family Cites Families (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6570944B2 (en) * | 2001-06-25 | 2003-05-27 | Rambus Inc. | Apparatus for data recovery in a synchronous chip-to-chip system |
JPH10143424A (ja) * | 1996-11-13 | 1998-05-29 | Mitsubishi Electric Corp | メモリシステム |
US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
US6442644B1 (en) * | 1997-08-11 | 2002-08-27 | Advanced Memory International, Inc. | Memory system having synchronous-link DRAM (SLDRAM) devices and controller |
US6330627B1 (en) * | 1998-01-20 | 2001-12-11 | Kabushiki Kaisha Toshiba | System for fast data transfer between memory modules and controller using two clock lines each having a go line portion and a return line portion |
US6160423A (en) * | 1998-03-16 | 2000-12-12 | Jazio, Inc. | High speed source synchronous signaling for interfacing VLSI CMOS circuits to transmission lines |
US6029252A (en) * | 1998-04-17 | 2000-02-22 | Micron Technology, Inc. | Method and apparatus for generating multi-phase clock signals, and circuitry, memory devices, and computer systems using same |
JP3727778B2 (ja) * | 1998-05-07 | 2005-12-14 | 株式会社東芝 | データ高速転送同期システム及びデータ高速転送同期方法 |
US6349399B1 (en) * | 1998-09-03 | 2002-02-19 | Micron Technology, Inc. | Method and apparatus for generating expect data from a captured bit pattern, and memory device using same |
JP2000194594A (ja) * | 1998-12-28 | 2000-07-14 | Nec Corp | メモリ制御回路 |
US6518794B2 (en) * | 2000-04-24 | 2003-02-11 | International Business Machines Corporation | AC drive cross point adjust method and apparatus |
JP4569915B2 (ja) * | 2000-08-11 | 2010-10-27 | エルピーダメモリ株式会社 | 半導体記憶装置 |
US7313715B2 (en) * | 2001-02-09 | 2007-12-25 | Samsung Electronics Co., Ltd. | Memory system having stub bus configuration |
US6801989B2 (en) * | 2001-06-28 | 2004-10-05 | Micron Technology, Inc. | Method and system for adjusting the timing offset between a clock signal and respective digital signals transmitted along with that clock signal, and memory device and computer system using same |
US6941484B2 (en) * | 2002-03-01 | 2005-09-06 | Intel Corporation | Synthesis of a synchronization clock |
SG120185A1 (en) * | 2004-08-30 | 2006-03-28 | Micron Technology Inc | Delay lock loop phase glitch error filter |
US7180821B2 (en) * | 2004-09-30 | 2007-02-20 | Infineon Technologies Ag | Memory device, memory controller and memory system having bidirectional clock lines |
-
2004
- 2004-09-30 US US10/955,177 patent/US7173877B2/en not_active Expired - Fee Related
-
2005
- 2005-09-06 DE DE102005042269A patent/DE102005042269B4/de not_active Expired - Fee Related
- 2005-09-30 CN CNB2005101064938A patent/CN100377062C/zh not_active Expired - Fee Related
Patent Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5987576A (en) * | 1997-02-27 | 1999-11-16 | Hewlett-Packard Company | Method and apparatus for generating and distributing clock signals with minimal skew |
CN1209630A (zh) * | 1997-08-25 | 1999-03-03 | 日本电气株式会社 | 半导体存储装置 |
CN1244018A (zh) * | 1998-08-04 | 2000-02-09 | 三星电子株式会社 | 同步猝发半导体存储器件 |
US20040057331A1 (en) * | 2001-05-25 | 2004-03-25 | Micron Technology, Inc. | Synchronous mirror delay with reduced delay line taps |
Also Published As
Publication number | Publication date |
---|---|
DE102005042269B4 (de) | 2008-09-18 |
CN1755606A (zh) | 2006-04-05 |
US20060067157A1 (en) | 2006-03-30 |
DE102005042269A1 (de) | 2006-04-13 |
US7173877B2 (en) | 2007-02-06 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
C06 | Publication | ||
PB01 | Publication | ||
C10 | Entry into substantive examination | ||
SE01 | Entry into force of request for substantive examination | ||
C14 | Grant of patent or utility model | ||
GR01 | Patent grant | ||
C41 | Transfer of patent application or patent right or utility model | ||
C56 | Change in the name or address of the patentee | ||
CP01 | Change in the name or title of a patent holder |
Address after: Munich, Germany Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: INFINEON TECHNOLOGIES AG |
|
TR01 | Transfer of patent right |
Effective date of registration: 20120927 Address after: Munich, Germany Patentee after: QIMONDA AG Address before: Munich, Germany Patentee before: Infineon Technologies AG |
|
C41 | Transfer of patent application or patent right or utility model | ||
TR01 | Transfer of patent right |
Effective date of registration: 20151223 Address after: German Berg, Laura Ibiza Patentee after: Infineon Technologies AG Address before: Munich, Germany Patentee before: QIMONDA AG |
|
CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20080326 Termination date: 20170930 |
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CF01 | Termination of patent right due to non-payment of annual fee |