CN100379004C - 闪存存储单元及制造方法 - Google Patents

闪存存储单元及制造方法 Download PDF

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CN100379004C
CN100379004C CNB03810590XA CN03810590A CN100379004C CN 100379004 C CN100379004 C CN 100379004C CN B03810590X A CNB03810590X A CN B03810590XA CN 03810590 A CN03810590 A CN 03810590A CN 100379004 C CN100379004 C CN 100379004C
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CN1653616A (zh
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F·霍夫曼恩
M·斯佩奇特
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Infineon Technologies AG
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    • H—ELECTRICITY
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    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
    • H—ELECTRICITY
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    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H10B41/40—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the peripheral circuit region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

存储单元-形成穿隧晶体管-具有一各别的浮置栅极(7)以及一控制栅极(9)，该个别浮置栅极(7)以及该控制栅极(9)乃位在源极以及漏极掺杂区(14)之间的一沟道区上的一沟槽壁中，而被该等存储单元具有一栅极(12)，其配置在一另外的沟槽中，通过该栅极，位在介于沟槽之间的一半导体脊状部(13)中的沟道区域可以可被驱动。栅极(12)的栅极氧化物(11)可能被做成非常薄。因此，如果经由栅极驱动，尽管是维持好的数据，一高读取电流仍可被获得。

Description

闪存存储单元及制造方法
技术领域
本发明涉及一闪存存储单元以及此存储单元的矩阵排列如一半导体内存，以及涉及一相关联的制造方法。
背景技术
一闪存存储单元具有一晶体管结构包含一浮置栅极以及一控制栅极，其彼此且从半导体材料由薄层的一介电层绝缘。当一适当的电压提供至控制栅极，电荷载体隧道从晶体管沟道区经过薄介电层到浮置栅极上，结果存储单元被程序化。因为晶体管的突增电压由于在浮置栅极上的电荷载体改变，程序化状态可从原始状态被区别，即，单元可被读取。在消磁步骤期间，电荷从浮置栅极藉由相反提供的电位被移除，因此记忆晶体管的原始(未充电的)状态再次达到，至少很趋近。在先前的闪存存储单元例子中，存在晶体管微形化的问题，因为在半导体材料以及浮置栅极之间的隧道氧化物的厚度为了能够满足资料保存的原因不能被减少至8纳米以下。一照比例微形化的此晶体管具有维持相同的栅极氧化物厚度是不可能。
因此本发明的目的是提出详细说明一闪存存储单元，其尽管较小的尺寸，具有一效能比得上传统的闪存存储单元。此外，本发明说明一相关联的制造方法。
此目的是通过具有根据本发明所公开特征的闪存存储单元以及制造一闪存存储单元的方法而达成。
发明内容
闪存存储单元具有一双栅极晶体管具有一非常薄的半导体脊状部，在其一侧上，一浮置栅极以及一控制栅极被配置而在其它侧上，一另外的栅极被配置。此配置中，晶体管特性由这两个栅极决定。在电极之间的半导体脊状部完全用尽电荷载体。如果栅极分别地被驱动，沟道电位是从两侧半导体脊状部不同地被影响。在半导体脊状部的一侧上，有一习惯上的场效晶体管结构，而在其它侧上，一浮置栅极晶体管其经由一控制栅极驱动。习惯上的晶体管结构是被提供用以读取存储单元；其突增电压可藉由浮置栅极晶体管的栅极上的电位被控制。
于下伴随参考随附图标更加详细描述一闪存存储单元以及其制造方法的范例。
附图说明
第1图至第4图显示剖面图，在一较佳制造方法的不同的步骤之后通过闪存存储单元的中间产物。
第5图显示闪存存储单元的配置平面图。
第6图显示一电路图以及电路操作的典型电位的一表格。
具体实施方式
一闪存存储单元的较佳实施例是描述于下基于一较佳的制造方法。第1图显示方法的第一步骤之后经过一中间产物的剖面图。一SOI基板包含一大块硅层1，二氧化硅所制的薄绝缘层2以及一薄主体硅层3较佳地作为一衬底。较佳地，在此例中，首先一附属层4被提供至主体硅层3上，附属层可能为例如氮化硅。该附属层4是通过适当的掩模技术而被刻划，例如一光罩或一阻罩，以使维持部分可被使用作为一掩模而用于蚀刻方向彼此平行的沟槽5。沟槽5是被制造为具有一深度以使主体硅层3藉由每一沟槽完全地适合。沟槽较佳地被制造于绝缘层2之中如第1图所示以获得一较强的偶合在浮置栅极以及控制栅极之间。其可能使用的光刻胶接着被移除。彼此平行配置的一复数的沟槽5被提供以制造不仅一闪存存储单元，而且制造一存储单元数组之类似矩阵的排列。
被提供作为一栅极介电层的第一介电层6随后被制造，较佳地为一氧化物，特别是二氧化硅，为了半导体材料可能被浅薄地氧化而具有一小厚度的目的。在此例中，是否第一介电层6被提供于附属层4的顶部侧边上是不重要的。
浮置栅极7是被制造于比邻第一介电层6藉由一步骤其中首先浮置栅极7的材料，较佳地为掺杂的多晶硅，被配置在沟槽5中。沉积的材料以一已知方法蚀刻回去以形成类似间隔的部分在沟槽5的侧壁。一具有关于沟槽的横向进行的开口的另外的掩模系被使用以在一单独的晶体管的数量级的部位之间蚀刻，因此维持类似间隔的部位提供于浮置栅极在沟槽5的长的方向被阻断于部份中，即，垂直于第1图所画的平面。
下一个方法步骤导致根据第2图的配置。首先，一第二介电层8被使用且刻划，其被提供作为浮置栅极以及控制栅极之间的一介电层且较佳地被使用作为一ONO层(氧-氮-氧层)包含连续的SiO2，Si3N4以及SiO2。控制栅极9的材料接着被沉积，其较佳地再次为掺杂的多晶硅化物。此材料相同地被蚀刻回去，但不阻断在沟槽的长的方向。单独的存储单元的控制栅极因此仍然为电传导性地沿着沟槽相互连接，具有存储单元排列的个别的字符线被形成的结果。
沟槽接着被以电绝缘的材料所制的一沟槽填充物10填补，例如以二氧化硅。在沟槽填充物被导入之前，多晶硅化物可能在沟槽末端至少部分地被移除藉由一另外的掩模技术，为了绝缘彼此单独的字符线。沟槽填充物被平面化于顶部侧，例如藉由CMP(化学机械抛光)。藉由一另外的蚀刻步骤，附属层4被移除至一程度以使附属层一残留的部分仍然如一间隔仅在沟槽填充物10的侧壁。
根据第3图所述的剖面图，使用残留部分的附属层4作为一掩模，另外的沟槽15被蚀刻进入主体硅层3，该沟槽在已经存在且填补的沟槽5之间平行行进。另外的沟槽15的深度仅仅如绝缘层2的顶端侧一般远。一第三介电层11，例如二氧化硅所制，接着被制造在该另外的沟槽15侧壁上。栅极12是以邻接该介电层的方式被制造，较佳地藉由掺杂多晶硅化物再次被沉积且刻划以形成类似间隔的部分。
已经存在于沟槽之间的半导体脊状部13被缩小以使其可能控制电荷载体在半导体脊状部13的半导体材料中从两侧藉由电位在控制栅极9以及栅极12上。栅极12所使用的材料被蚀刻到另外的沟槽15的末端，因此，此处亦，为栅极12，其在一另外的沟槽15的一个别的侧壁上彼此连续而被电传导性地相互连接且形成彼此绝缘的另外的字符线被提供用以读取存储单元。另外的沟槽亦以随后被平面化的一沟槽填充物10填补。
第4图显示一剖面图经由浮置栅极之间区域中的配置，其中在此实施例中，第二介电层8是直接坐落于第一介电层6上。连接控制栅极9至彼此的字符线的中间区域19是配置靠近沟槽的侧壁。浮置栅极7之间的区域中，附属层的部分被移除，且掺杂物的注入被导入半导体脊状部13经由造成的开口以形成掺杂区14用于源极以及漏极。这些掺杂区14接触连接经由开口藉由一步骤，其中较佳地首先一钛以及/或氮化钛所制的扩散阻绝层16被使用且接着接触洞填充物17例如钨所制是以其所知的方法被导入。源极以及漏极区出现在一线行进横向关于长方向的沟槽上电传导性地被连接至彼此藉由以切条类型的模式刻划于顶部侧的一位线18。
第5图显示闪存存储单元在一存储单元矩阵中的排列平面图。第3图以及第4图的剖面区域的切面位置被说明于第5图中。参考符号符合先前图标中的参考符号。此处可看出浮置栅极7被配置在那些半导体脊状部13的部分侧壁上，其位于两连续的掺杂区14之间，在此处提供的沟道区之上。控制栅极9电传导地连接至彼此藉由中间区19以形成自元线。一相关联的栅极12用以驱动沟道区在两侧上是被配置在半导体脊状部13的侧上，其相对于浮置栅极7。位线，其不描述于此平面图中，在顶部侧边以平行切线横向地关于沟槽的长方向行进，那就是说在每一个例子中以垂直第5图中的切割方向行进。
第6图说明此存储单元矩阵的电路图。每一存储单元是通过一双栅晶体管形成。源极以及漏极区被连接至彼此于管中藉由第6图中垂直行进的位线。代替字符线，两驱动线出现于此处以列的方式，为了精确，一线CG-栅极用以驱动控制栅极以及在每一例子中一驱动线Tr-栅极用以驱动习惯上的晶体管结构的栅极，其相对于浮置栅极。
一表格具有适当且典型的程序(Prog)，消去(Erase)以及读取(Read)存储单元的电压值说明于上面第6图电路图中。进入该表格的电压值是分别出现在源极区，在控制栅极，在习惯上晶体管结构的栅极以及源极区。存储单元矩阵呈现一“虚拟基底”结构。分割闪存存储单元为一读取晶体管，为其栅极12被提供，以及分割成一程序化/消除晶体管，为其控制栅极9被提供，具有读取晶体管可被了解具有一特别薄的栅极氧化物(第三介电层11)的优点。当从存储单元经由Tr-栅极线读取时的读取电流明显地大于从传统闪存存储单元读取时的读取电流，由此使得一明显的微形化的存储单元成为可能。
参考符号组件列表
1大片硅层
2绝缘层
3主体硅层
4附属层
5沟槽
6第一介电层
7浮置栅极
8第二介电层
9控制栅极
10沟槽填充物
11第三介电层
12栅极
13半导体脊状部
14掺杂区
15另外的沟槽
16扩散阻绝层
17接触孔填充物
18位线

Claims (6)

1.一种闪存存储单元具有
一沟槽(5)，形成于一半导体主体或一半导体层(3)的一顶部侧边，
一浮置栅极(7)，配置于该沟槽(5)且与全部侧边衔接，该浮置栅极藉由一第一介电层(6)而与该沟槽的一侧壁的半导体材料绝缘，
一控制栅极(9)，配置在沟槽中，该控制栅极藉由一第二介电层(8)而与该浮置栅极(7)绝缘且具有一电导线，以及掺杂区(14)，用于源极以及漏极，配置在沟槽的一纵方向的侧壁的半导体材料中，乃在浮置栅极(7)两侧彼此之间具有一距离，该掺杂区具有接点连接且电传导连接到一各别的位线(18)，
其中
一另外的沟槽(15)乃与该沟槽(5)平行配置，其配置位置至具有浮置栅极(7)的侧壁有一小段距离，从而在沟槽(5)和另外的沟槽(15)之间形成一窄半导体脊状部(13)，该窄半导体脊状部(13)使得能够藉由电位从两侧控制半导体脊状部(13)的半导体材料中的电荷载体，且
一栅极(12)乃被配置在半导体脊状部(13)的一侧壁上的另外的沟槽(15)中，并与浮置电极(7)相对，且藉由一第三介电层(11)半导体材料绝缘，且具有一电导线。
2.一种如权利要求1所述的闪存存储单元的配置，其中
该闪存存储单元形成一具有虚拟接地构造的半导体内存矩阵排列，用于源极以及漏极的掺杂区(14)乃在该矩阵排列的一列中彼此电传导性连接，
该控制栅极(9)，出现于相同沟槽(5)中的矩阵排列的一行中者，乃电传导性地连接到彼此以及
该栅极(12)，其乃与一行电传导性相连的控制栅极(9)相对该浮置栅极(7)，乃同样电传导性地连接至彼此。
3.如权利要求2所述的配置，其中一沟槽(5)的两侧壁都具有浮置栅极(7)以及控制栅极(9)，且
另外的沟槽(15)具有与相关的浮置栅极相对出现的各别的栅极(12)，且出现在一各别的沟槽的两侧上。
4.一种制造闪存存储单元的方法，其中，
在一第一步骤中，一沟槽(5)乃被制造在一半导体主体或一半导体层(3)的一顶部侧边，
在一第二步骤中，一作为一栅极介电层的第一介电层(6)乃至少被使用至该沟槽(5)一侧壁上，且一栅极(7)亦被提供至其上并且被图样化，
在一第三步骤中，一第二介电层(8)乃被用至该浮置栅极(7)以及一控制栅极(9)也被提供至其上，
在一第四步骤中，以一电绝缘沟槽填充物(10)填满该沟槽，其中
在一第五步骤中，一另外的沟槽(15)乃被制造至具有一浮置栅极(7)的该沟槽的每一侧上，且制造方式是以距该沟槽一小距离并与其平行的方式来制造，该小距离使得能够藉由电位从两侧控制半导体材料中的电荷载体，
在一第六步骤中，于该另外的沟槽中，一第三介电层(11)乃被使用于与该浮置栅极相对的一侧上，以及一栅极(12)乃被施用至该介电层，以及
在一第七步骤中，该另外的沟槽(15)乃以一电绝缘沟槽填充物(10)来填满，以及一用以形成源极以及漏极掺杂区(14)的一掺杂注入乃部分被导入在沟槽之间的半导体材料中。
5.如权利要求4所述的方法，其中，
在第一步骤之前，一附属层(4)乃被施用至该半导体主体或者半导体层(3)的顶部侧边，且
该附属层(4)乃被图样化以作为一掩模，用以制造该沟槽(5)以及该另外的沟槽(15)，且在掺杂注入之前至少部分地被移除。
6.如权利要求4或5所述的方法，其中，在第一步骤中，一包含一总体硅层(1)绝缘硅SOI基板、因二氧化硅制造的一薄绝缘层(2)以及一薄主体硅层(3)乃被用作为一基础，以及
该沟槽(5)乃被制造于该绝缘层(2)中。
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