CN100382298C - 电子器件及其制造方法 - Google Patents
电子器件及其制造方法 Download PDFInfo
- Publication number
- CN100382298C CN100382298C CNB2003801064782A CN200380106478A CN100382298C CN 100382298 C CN100382298 C CN 100382298C CN B2003801064782 A CNB2003801064782 A CN B2003801064782A CN 200380106478 A CN200380106478 A CN 200380106478A CN 100382298 C CN100382298 C CN 100382298C
- Authority
- CN
- China
- Prior art keywords
- chip
- substrate
- conductive interconnection
- source
- heat sink
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
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Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
- H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/12—Mountings, e.g. non-detachable insulating substrates
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49575—Assemblies of semiconductor devices on lead frames
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16245—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16265—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being a discrete passive component
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73253—Bump and layer connectors
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/83—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a layer connector
- H01L2224/8319—Arrangement of the layer connectors prior to mounting
- H01L2224/83192—Arrangement of the layer connectors prior to mounting wherein the layer connectors are disposed only on another item or body to be connected to the semiconductor or solid-state body
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01078—Platinum [Pt]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01079—Gold [Au]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/095—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00 with a principal constituent of the material being a combination of two or more materials provided in the groups H01L2924/013 - H01L2924/0715
- H01L2924/097—Glass-ceramics, e.g. devitrified glass
- H01L2924/09701—Low temperature co-fired ceramic [LTCC]
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/19011—Structure including integrated passive components
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/1901—Structure
- H01L2924/1904—Component type
- H01L2924/19041—Component type being a capacitor
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19103—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device interposed between the semiconductor or solid-state device and the die mounting substrate, i.e. chip-on-passive
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
- H01L2924/191—Disposition
- H01L2924/19101—Disposition of discrete passive components
- H01L2924/19102—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device
- H01L2924/19104—Disposition of discrete passive components in a stacked assembly with the semiconductor or solid state device on the semiconductor or solid-state device, i.e. passive-on-chip
Landscapes
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
Claims (11)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
EP02080664 | 2002-12-20 | ||
EP02080664.2 | 2002-12-20 |
Publications (2)
Publication Number | Publication Date |
---|---|
CN1726591A CN1726591A (zh) | 2006-01-25 |
CN100382298C true CN100382298C (zh) | 2008-04-16 |
Family
ID=32668879
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
CNB2003801064782A Expired - Fee Related CN100382298C (zh) | 2002-12-20 | 2003-12-10 | 电子器件及其制造方法 |
Country Status (7)
Country | Link |
---|---|
US (1) | US7196416B2 (zh) |
EP (1) | EP1579502A2 (zh) |
JP (1) | JP2006511080A (zh) |
KR (1) | KR20050095586A (zh) |
CN (1) | CN100382298C (zh) |
AU (1) | AU2003285638A1 (zh) |
WO (1) | WO2004057668A2 (zh) |
Families Citing this family (23)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US20040262368A1 (en) * | 2003-06-26 | 2004-12-30 | Haw Tan Tzyy | Ball grid array solder joint reliability |
US7160758B2 (en) * | 2004-03-31 | 2007-01-09 | Intel Corporation | Electronic packaging apparatus and method |
US7183622B2 (en) * | 2004-06-30 | 2007-02-27 | Intel Corporation | Module integrating MEMS and passive components |
WO2006011068A1 (en) * | 2004-07-19 | 2006-02-02 | Koninklijke Philips Electronics N.V. | Electronic device comprising an integrated circuit and a capacitance element |
JP2006080350A (ja) * | 2004-09-10 | 2006-03-23 | Denso Corp | 半導体装置およびその実装構造 |
US7560309B1 (en) * | 2005-07-26 | 2009-07-14 | Marvell International Ltd. | Drop-in heat sink and exposed die-back for molded flip die package |
TWI324378B (en) * | 2005-10-21 | 2010-05-01 | Freescale Semiconductor Inc | Method of making semiconductor package with reduced moisture sensitivity |
CA2868579C (en) | 2006-03-30 | 2018-01-30 | Esco Corporation | Wear assembly |
US7622811B2 (en) * | 2006-09-14 | 2009-11-24 | Stats Chippac, Inc. | Semiconductor assembly with component attached on die back side |
WO2008099321A1 (en) | 2007-02-14 | 2008-08-21 | Nxp B.V. | Dual or multiple row package |
US7863738B2 (en) * | 2007-05-16 | 2011-01-04 | Texas Instruments Incorporated | Apparatus for connecting integrated circuit chip to power and ground circuits |
US20090230524A1 (en) * | 2008-03-14 | 2009-09-17 | Pao-Huei Chang Chien | Semiconductor chip package having ground and power regions and manufacturing methods thereof |
US7859120B2 (en) * | 2008-05-16 | 2010-12-28 | Stats Chippac Ltd. | Package system incorporating a flip-chip assembly |
US20100044850A1 (en) | 2008-08-21 | 2010-02-25 | Advanced Semiconductor Engineering, Inc. | Advanced quad flat non-leaded package structure and manufacturing method thereof |
US8124447B2 (en) | 2009-04-10 | 2012-02-28 | Advanced Semiconductor Engineering, Inc. | Manufacturing method of advanced quad flat non-leaded package |
US20110163430A1 (en) * | 2010-01-06 | 2011-07-07 | Advanced Semiconductor Engineering, Inc. | Leadframe Structure, Advanced Quad Flat No Lead Package Structure Using the Same, and Manufacturing Methods Thereof |
MY165522A (en) * | 2011-01-06 | 2018-04-02 | Carsem M Sdn Bhd | Leadframe packagewith die mounted on pedetal that isolates leads |
KR101719636B1 (ko) * | 2011-01-28 | 2017-04-05 | 삼성전자 주식회사 | 반도체 장치 및 그 제조 방법 |
US9034692B2 (en) | 2011-03-21 | 2015-05-19 | Stats Chippac Ltd. | Integrated circuit packaging system with a flip chip and method of manufacture thereof |
JP2015046501A (ja) * | 2013-08-28 | 2015-03-12 | 三菱電機株式会社 | 半導体装置 |
CN104157617B (zh) * | 2014-07-29 | 2017-11-17 | 华为技术有限公司 | 芯片集成模块、芯片封装结构及芯片集成方法 |
JP7126563B2 (ja) | 2018-05-04 | 2022-08-26 | テレフオンアクチーボラゲット エルエム エリクソン(パブル) | キャビティバックアンテナエレメント及びアレイアンテナ装置 |
CN109904139B (zh) * | 2019-03-08 | 2020-12-25 | 中国科学院微电子研究所 | 带有柔性转接板的大尺寸芯片系统封装结构及其制作方法 |
Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08125112A (ja) * | 1994-10-26 | 1996-05-17 | Hitachi Ltd | 半導体装置およびその製造方法 |
CN1202983A (zh) * | 1995-11-28 | 1998-12-23 | 株式会社日立制作所 | 半导体器件及其制造方法以及装配基板 |
JPH1154695A (ja) * | 1997-07-31 | 1999-02-26 | Sanyo Electric Co Ltd | 半導体装置 |
US6337510B1 (en) * | 2000-11-17 | 2002-01-08 | Walsin Advanced Electronics Ltd | Stackable QFN semiconductor package |
US20020093087A1 (en) * | 2001-01-15 | 2002-07-18 | Paek Jong Sik | Semiconductor package with stacked dies |
US20020105789A1 (en) * | 2001-02-02 | 2002-08-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package for multi-chip stacks |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH0311747A (ja) * | 1989-06-09 | 1991-01-21 | Toshiba Corp | 半導体装置 |
US6225699B1 (en) | 1998-06-26 | 2001-05-01 | International Business Machines Corporation | Chip-on-chip interconnections of varied characteristics |
DE10041695A1 (de) * | 2000-08-24 | 2002-03-07 | Orient Semiconductor Elect Ltd | Kapselungskonstruktion für einen mit einem Chip und mit einer Unterlage verbundenen Flip-Chip |
SG95637A1 (en) * | 2001-03-15 | 2003-04-23 | Micron Technology Inc | Semiconductor/printed circuit board assembly, and computer system |
US6967395B1 (en) * | 2001-03-20 | 2005-11-22 | Amkor Technology, Inc. | Mounting for a package containing a chip |
US6441483B1 (en) * | 2001-03-30 | 2002-08-27 | Micron Technology, Inc. | Die stacking scheme |
US7064009B1 (en) * | 2001-04-04 | 2006-06-20 | Amkor Technology, Inc. | Thermally enhanced chip scale lead on chip semiconductor package and method of making same |
TW495943B (en) * | 2001-04-18 | 2002-07-21 | Siliconware Precision Industries Co Ltd | Semiconductor package article with heat sink structure and its manufacture method |
US6610560B2 (en) * | 2001-05-11 | 2003-08-26 | Siliconware Precision Industries Co., Ltd. | Chip-on-chip based multi-chip module with molded underfill and method of fabricating the same |
EP1500137A1 (en) | 2002-04-11 | 2005-01-26 | Koninklijke Philips Electronics N.V. | Carrier, method of manufacturing a carrier and an electronic device |
US6987032B1 (en) * | 2002-07-19 | 2006-01-17 | Asat Ltd. | Ball grid array package and process for manufacturing same |
-
2003
- 2003-12-10 CN CNB2003801064782A patent/CN100382298C/zh not_active Expired - Fee Related
- 2003-12-10 WO PCT/IB2003/005976 patent/WO2004057668A2/en active Application Filing
- 2003-12-10 AU AU2003285638A patent/AU2003285638A1/en not_active Abandoned
- 2003-12-10 EP EP03778630A patent/EP1579502A2/en not_active Withdrawn
- 2003-12-10 US US10/539,367 patent/US7196416B2/en not_active Expired - Fee Related
- 2003-12-10 KR KR1020057011243A patent/KR20050095586A/ko not_active Application Discontinuation
- 2003-12-10 JP JP2004561851A patent/JP2006511080A/ja active Pending
Patent Citations (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH08125112A (ja) * | 1994-10-26 | 1996-05-17 | Hitachi Ltd | 半導体装置およびその製造方法 |
CN1202983A (zh) * | 1995-11-28 | 1998-12-23 | 株式会社日立制作所 | 半导体器件及其制造方法以及装配基板 |
JPH1154695A (ja) * | 1997-07-31 | 1999-02-26 | Sanyo Electric Co Ltd | 半導体装置 |
US6337510B1 (en) * | 2000-11-17 | 2002-01-08 | Walsin Advanced Electronics Ltd | Stackable QFN semiconductor package |
US20020093087A1 (en) * | 2001-01-15 | 2002-07-18 | Paek Jong Sik | Semiconductor package with stacked dies |
US20020105789A1 (en) * | 2001-02-02 | 2002-08-08 | Siliconware Precision Industries Co., Ltd. | Semiconductor package for multi-chip stacks |
Also Published As
Publication number | Publication date |
---|---|
CN1726591A (zh) | 2006-01-25 |
US7196416B2 (en) | 2007-03-27 |
JP2006511080A (ja) | 2006-03-30 |
EP1579502A2 (en) | 2005-09-28 |
AU2003285638A1 (en) | 2004-07-14 |
KR20050095586A (ko) | 2005-09-29 |
WO2004057668A3 (en) | 2004-08-12 |
WO2004057668A2 (en) | 2004-07-08 |
US20060099742A1 (en) | 2006-05-11 |
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