CN100386719C - Coordinate transformation method for digital scanning change-over device and processor - Google Patents

Abstract

The present invention relates to a method and a processor used for transforming the coordinates of a digital scanning and transforming device, which is used for transforming rectangular coordinates (x0, y0) into polar coordinates (r, p). The method comprises the steps of initialization, preprocessing, calculation by a CORDIC algorithm, semidiameter correction and phase correction, wherein in calculation by a CORDIC algorithm, the iteration of the CORDIC algorithm is first carried out for (a) times by left shifting operation, and then the iteration of the CORDIC algorithm is carried out for (N-a) times by right shifting operation. The processor is an optimal embodiment for realizing the method, and the processor comprises an input module, a preprocessing module, an iterative operation module, a semidiameter correction module, a phase correction module and an output module. Performance parameters of precision, speed, etc. of the digital scanning and transforming device in a type-B ultrasonic display instrument can be flexibly adjusted by the coordinate transforming method and the processor, and requirements of high precision, large capacity and real-time operation on the display instrument are satisfied.

Description

The coordinate transformation method and the processor that are used for digital scan converter

Technical field

The present invention relates in the electric digital data processing field according to the figure place of data to be processed or data processing method and the device that content is carried out computing, relate in particular to the coordinate transformation method and the processor of the digital scan converter that is used for the B ultrasonic imager.

Background technology

Digital scan converter in the B ultrasonic imager that prior art relates to will be converted to polar data with the rectangular coordinate data showing, can adopt methods such as tabling look-up, use special-purpose coordinate transform chip or structure circuit to realize.There is finite capacity in the method that employing is tabled look-up and the very high shortcoming of cost; Adopt special-purpose coordinate transform chip, exist performance to adjust inflexible shortcoming; Adopt the method that makes up special circuit, because that rectangular coordinate is converted to the common employing of polar coordinates is CORDIC (Coordinate RotationDigital Computer: CORDIC) algorithm, and adopt existing C ORDIC algorithm to realize that rectangular coordinate is to polar conversion, be not enough to realize adjust performance parameters such as precision, speed flexibly, can not satisfy the requirement of high precision, high capacity and real-time working imager.

Summary of the invention

The technical problem to be solved in the present invention is to avoid above-mentioned the deficiencies in the prior art part, and proposes a kind of coordinate transformation method and processor that is used for B ultrasonic imager digital scan converter.

The technical scheme that the present invention solves the problems of the technologies described above employing is, proposes a kind of coordinate transformation method that is used for digital scan converter, in order to the rectangular coordinate value of input (x0, y0) be converted to the polar coordinates value (r, p) output especially, comprises step:

1.. receive x0 from front-end circuit by the input of described device and pretreatment module, y0 carries out assignment and output to constant and the variable of using, and comprising:

Angle variables z (0) is initialized as 0;

Symbolic variable cout _iBe initialized as 1;

According to the rectangular coordinate value (x0 y0) comes initialization phase place judgment variable Xs, Ys, and this (x0 y0) is converted to unsigned number, that is:

If X0＜0, then Xs=1; If Y0＜0, then Ys=1; And (x0, y0)=(| x0|, | y0|);

2.. the CORDIC interative computation module of described device divides two stages to carry out iteration N time according to the constant and the variable of described output:

Phase one: carry out the cordic algorithm iteration a time with shift left operation, that is:

I is from 0 to a-1, is 1 to increase progressively cycle calculations by step-length:

x(i+1)＝2 ⁱ＊x(i)+y(i)；y(i+1)＝|2 ⁱ＊y(i)-x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(2 ⁱ＊y(i)-x(i))；

Subordinate phase: carry out (N-a) inferior cordic algorithm iteration with right-shift operation, that is:

I is 1 to increase progressively cycle calculations by step-length from a to N-1:

x(i+1)＝x(i)+2 ^-i＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))；

3.. the radius correcting module of described device calculates revised radius r according to the output of described N iteration:

$A=\underset{\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="C0314001500152.png,C0314001500153.png"\; state="\{\{state\}\}">N</figure-callout>}}{\mathrm{\&Pi;}}\sqrt{1+2^{-2i}},$ ${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i,$ r＝1/A＊X′ _N；

4.. the phase place correcting module of described device calculates phase place p according to the output of described N iteration, and according to described phase place judgment variable Xs, Ys adjusts correction:

p＝z(N)/2 ^N，

If (Xs, Ys)=(0,0), the p value is not adjusted; If (Xs, Ys)=(1,0), p=π-p;

If (Xs, Ys)=(1,1), p=π+p; If (Xs, Ys)=(0,1), p=2 π-p.

The technical scheme that the present invention solves the problems of the technologies described above employing also comprises, manufactures and designs a kind of coordinate conversion processor that is used for digital scan converter, in order to the rectangular coordinate value (x0, y0) input be converted to the polar coordinates value (r, p) output, especially, comprising:

The input and pretreatment module, receive described rectangular coordinate input value, and produce corresponding constant value N, | x0| and | y0|, and phase place judgment variable Xs and Ys, angle variables z (0) and symbolic variable cout _iInitial value;

The interative computation module, according to described | x0| and | y0|, constant value N, angle variables z (0) and symbolic variable cout _iCarry out N time cordic algorithm iteration; This interative computation module comprises two modules: first module and second module, and described first module realizes a CORDIC interative computation with shift left operation, that is: i is from 0 to a-1, is 1 to increase progressively cycle calculations by step-length:

x(i+1)＝2 ⁱ＊x(i)+y(i)；y(i+1)＝|2 ⁱ＊y(i)-x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(2 ⁱ＊y(i)-x(i))；

This module comprises the circuit unit of realizing each interative computation: two shift left operation devices, two no symbol adder calculators and a signed magnitude arithmetic(al) device are used for described x (i+1), the calculating of y (i+1); A no symbol totalizer is used for the calculating of described z (i+1); A logic controller is used for described cout _I+1Calculating;

Described second module realizes (N-a) inferior CORDIC interative computation with right-shift operation, that is: i is 1 to increase progressively cycle calculations by step-length from a to N-1:

x(i+1)＝x(i)+2 ^-1＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))；

This module comprises the circuit unit of realizing each interative computation: two shift right operation devices, two no symbol adder calculators and a signed magnitude arithmetic(al) device are used for described x (i+1), the calculating of y (i+1); A no symbol totalizer is used for the calculating of described z (i+1); A logic controller is used for described cout _I+1Calculating;

Radius correcting module and phase place correcting module, according to the output of described interative computation module calculate described polar coordinates value (r, p) and output, the multiplicative operator that described radius correcting module or phase place correcting module comprise or shift right operation device are realized column count down:

R=1/A*X ' _NWherein <math><mrow> <mi>A</mi> <mo>=</mo> <munder> <mi>&amp;Pi;</mi> <mi>N</mi> </munder> <msqrt> <mn>1</mn> <mo>+</mo> <msup> <mn>2</mn> <mrow> <mo>-</mo> <mn>2</mn> <mi>i</mi> </mrow> </msup> </msqrt> <mo>,</mo></math> ${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i,$

P=z (N)/2 ^N, if (Xs, Ys)=(0,0), p=p; If (Xs, Ys)=(1,0), p=π-p;

If (Xs, Ys)=(1,1), p=π+p; If (Xs, Ys)=(0,1), p=2 π-p;

Output module, with described r, the output of p value.

Compare with prior art, adopt the present invention to be used for the coordinate transformation method and the processor of digital scan converter, can realize that digital scan converter is adjusted performance parameters such as precision, speed flexibly in the B ultrasonic imager, satisfy requirement high precision, high capacity and the real-time working of developing instrument.

Description of drawings

Fig. 1 is used for the theory diagram of the coordinate transformation method most preferred embodiment of digital scan converter for the present invention.

Fig. 2 is used circuit diagram of interative computation in first computing module of iteration described in the embodiment of the invention.

Fig. 3 is used circuit diagram of interative computation in the preceding computing module of the value of iteration b described in the embodiment of the invention.

Fig. 4 is used circuit diagram of interative computation in the computing module of the value of iteration b described in embodiment of the invention back.

Embodiment

Be described in further detail below in conjunction with the most preferred embodiment shown in the accompanying drawing.

The present invention is used for the coordinate transformation method of digital scan converter, in order to the input a rectangular coordinate value (x0, y0) be converted to the polar coordinates value (r, p) output, comprise step:

1.. receive x0 from front-end circuit by the input of described device and pretreatment module, y0 carries out assignment and output to constant and the variable of using, and comprising:

Angle variables z (0) is initialized as 0;

Symbolic variable cout _iBe initialized as 1;

According to the rectangular coordinate value (x0 y0) comes initialization phase place judgment variable Xs, Ys, and this (x0 y0) is converted to unsigned number, that is:

If X0＜0, then Xs=1; If Y0＜0, then Ys=1; And (x0, y0)=(| x0|, | y0|);

2.. the CORDIC interative computation module of described device divides two stages to carry out iteration N time according to the constant and the variable of described output:

Phase one: carry out the cordic algorithm iteration a time with shift left operation, that is:

I is from 0 to a-1, is 1 to increase progressively cycle calculations by step-length:

x(i+1)＝2 ⁱ＊x(i)+y(i)；y(i+1)＝|2 ⁱ＊y(i)-x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(2 ⁱ＊y(i)-x(i))；

Subordinate phase: carry out (N-a) inferior cordic algorithm iteration with right-shift operation, that is:

I is 1 to increase progressively cycle calculations by step-length from a to N-1:

x(i+1)＝x(i)+2 ^-i＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))；

3.. the radius correcting module of described device calculates revised radius r according to the output of described N iteration:

$A=\underset{\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="C0314001500152.png,C0314001500153.png"\; state="\{\{state\}\}">N</figure-callout>}}{\mathrm{\&Pi;}}\sqrt{1+2^{-2i}},$ ${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i,$ r＝1/A ＊X′ _N；

4.. the phase place correcting module of described device calculates phase place p according to the output of described N iteration, and according to described phase place judgment variable Xs, Ys adjusts correction:

p＝z(N)/2 ^N，

If (Xs, Ys)=(0,0), the p value is not adjusted; If (Xs, Ys)=(1,0), p=π-p;

If (Xs, Ys)=(1,1), p=π+p; If (Xs, Ys)=(0,1), p=2 π-p.

The coordinate transformation method that the present invention is used for digital scan converter further illustrates below:

Cordic algorithm is to finish the rotation of vector by the method for iteration, thereby finishes the computing of transcendental function such as trigonometric function, hyperbolic function, exponential function and inverse function thereof.The general iterative formula of algorithm is:

$\left\{\begin{array}{c}{x}_{i+1}=x_i-d_i{y}_i{2}^{-i}\\ y_{i+1}=y_i+d_i{x}_i{2}^{-i}\\ z_{i+1}=z_i-d_i{\tan }^{-1}\left(2^{-i}\right)\end{array}\right.---\left(1\right)$

Wherein: $d_i=\left\{\begin{array}{ccc}+1& \mathrm{if}& (y_i\&times;x_i)<0\\ -1& & \mathrm{otherwise}\end{array}\right.,i=0,\mathrm{1,2}....N-1$

Algorithm is output as through after N iteration:

$\left\{\begin{array}{c}{X}_N=A\sqrt{x_0^2+y_0^2}\\ Y_N\&RightArrow;0\\ Z_N=z_0+{\tan }^{-1}(y_0/x_0)\\ A=\underset{\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="C0314001500152.png,C0314001500153.png"\; state="\{\{state\}\}">N</figure-callout>}}{\mathrm{\&Pi;}}\sqrt{1+2^{-2i}}\end{array}\right.---\left(2\right)$

If we are x ₀And y ₀Regard horizontal ordinate and ordinate in the rectangular coordinate system as, then pass through N iteration after, x as a result _NAnd z _NCorrespond respectively to its square root (factors A is arranged) and its arc tangent and (a constant z is arranged ₀).If establish z ₀=0, and with x _NMultiply by 1/A, so x _NAnd z _NBe exactly and x ₀And y ₀Radius in the corresponding polar coordinate system and phase place.Algorithm is by forcing initialization vector [x ₀y ₀] approach X-axis and finish rectangular coordinate one polar conversion.

Situation about should be noted that in addition is initialization vector [x ₀y ₀] must be positioned at first quartile, this be because

∑tan ^-1(2 ^-i)＜100° (3)

Thereby, if initialization vector not at first quartile, the result of algorithm iteration just can not approach X-axis.So,, must make corresponding correction to algorithm if initialization vector is positioned at other quadrants.Following research is only limited to the situation of initialization vector at first quartile, and the situation that is positioned at other quadrants can provide explanation in the back.

Scrutinize the CORIC algorithm,, work as y for first equation in the system of equations (1) _i〉=0 o'clock, d _i=-1 and have

x _i+1＝x _i+y _i2 ^-i＝x _i+|y _i|2 ^-i (4)

Can obtain x _I+1＞x _iEqually, work as y _i＜0 o'clock, d _i=1 and have

x _i+1＝x _i-y _i2 ^-i＝x _i+|y _i|2 ^-i (5)

Also can obtain x _I+1＞x _iSo x _iBe an increasing sequence, consider x ₀＞0, so x _iIt is a sequence of positive numbers that increases progressively.

For second equation in the system of equations (1), work as y _i〉=0 o'clock, d _i=-1, but abbreviation is

y _i+1＝y _i-x _i2 ^-(i+1)＝|y _i|-x _i2 ^-(i+1) (6)

Because x _iBe a sequence of positive numbers, so this can think the reducing of two positive numbers; Work as y _i＜0 o'clock, d _i=1, the formula abbreviation is

y _i+1＝y _i+x _i2 ^-(i+1)＝x _i2 ^-(i+1)-|y _i| (7)

This can think the reducing of two unsigned numbers equally.But this moment y _I+1Positive and negative and uncertain, for make it easy to that hardware is realized and and formula (6) be consistent, with formula (6,7) unification be:

y _i+1＝|y _i-x _i2 ^-(i+1)| (8)

At that time, system of equations (1) becomes:

$\left\{\begin{array}{c}{x}_{i+1}=x_i+y_i{2}^{-i}\\ y_{i+1}=|y_i-x_i{2}^{-i}|\\ z_{i+1}=z_i-{\mathrm{cout}}_i{\tan }^{-1}\left(2^{-i}\right)\end{array}\right.---\left(9\right)$

Wherein, ${\mathrm{cout}}_i=\left\{\begin{array}{ccc}-1& \mathrm{if}& y_{i-1}<x_{i-1}{2}^{-(i-1)}\\ 1& & \mathrm{others}\end{array}\right.$

Adopt the cordic algorithm of system of equations (9), can improve the arithmetic speed of algorithm, following table has provided software emulation (precision analysis) and the hardware simulation results (resource consumption, arithmetic speed analysis) when symbolic operation and no symbolic operation are arranged:

	Symbol is arranged	No symbol	Note
				X, y, z word length	16 Bits	16 Bits	Annotate	1
Resource consumption	1754 logical blocks (35%)	1737 logical blocks (34%)	Annotate 2
				The highest realization frequency	27.93MHZ	47.16MHZ	Annotate	2
Radius precision (LSB)	2.31(-2.55 7.38)	1.98(-3.98 0.0)	Annotate 3
				Phase accuracy (LSB)	4.23(-77.78 88.73)	4.62(-88.59 88.73)	Annotate 3

Annotate 1: in simulation process, the word length of x, y expands to 18Bits (moving to left two), and z comprises the 15Bits decimal place.

Annotate 2: emulation realizes in the FPGA of U.S. altera corp (field programmable gate array), and has adopted pipeline organization.

Annotate 3: be absolute average error, be respectively maximum negative sense sum of errors maximum forward error in the bracket.

As can be seen from the above table, by there being symbolic operation to change no symbolic operation into, not improving significantly aspect the precision of consumption, radius and the phase place of resource, but on the highest realization frequency of computing, improving a lot.

There is certain value b in analysis equation group (9), y as can be known _bWidth smaller or equal to (b+1), then y _bMove to right (b+1) position after equal zero, at this moment, x _bRemain unchanged.In the iteration afterwards, because y _iFurther reduce the increase with i, x _iTo remain constant, thereby need not carry out the computing of equation one in the system of equations (9).And this b value can be determined by software emulation.

Further study the CORIC algorithm, we can find that the error main source of algorithm is: at x _i, y _iIn the iterative process, owing to there is right-shift operation (* 2 ^-i) and the cut position error that causes, thereby the lost part precision causes the end product error bigger.Therefore, can improve precision by eliminating the cut position error, method is exactly: replace right-shift operation with shift left operation, be about to system of equations (9) and change following form into:

$\left\{\begin{array}{c}{x}_{i+1}=x_i{2}^i+y_i\\ y_{i+1}=|y_i{2}^i-x_i|\\ z_{i+1}=z_i-{\mathrm{cout}}_i{\tan }^{-1}\left(2^{-i}\right)\end{array}\right.---\left(10\right)$

Wherein, ${\mathrm{cout}}_i=\left\{\begin{array}{ccc}-1& \mathrm{if}& y_{i-1}{2}^{-(i-1)}<x_{i-1}\\ 1& & \mathrm{others}\end{array}\right..$

But thus, can increase required hardware resource greatly, thereby cause the arithmetic speed of algorithm to reduce.

Take all factors into consideration, we can draw the way of dealing with problems: adopt system of equations (10) in preceding a iterative process, adopt system of equations (9) again in the iterative process of back.

It should be noted that owing to adopted shift left operation,, be shown below so after iteration is finished, must revise to the radius that obtains:

${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i---\left(11\right)$

Below two forms provided software emulation (precision analysis) and hardware simulation results (resource consumption, arithmetic speed analysis) when the middle a of system of equations (9) (not adopting shift left operation) and system of equations (10) (employing shift left operation) got different value:

	Do not adopt shift left operation	Adopt shift left operation (a=1)	Note
				X, y, z word length	16 Bits	16 Bits	Annotate	1
Resource consumption	1737 logical blocks (34%)	18541964 logical blocks (37%)	Annotate 2
				The highest realization frequency	47.16MHZ	45.45MHZ	Annotate	2
Radius precision (LSB)	1.98(-3.98 0.0)	1.14(-2.30 0	Annotate 3
				Phase accuracy (LSB)	4.62(-88.59 88.73)	2.40(-51.91 52.06)	Annotate 3

	Adopt shift left operation (a=2)	Adopt shift left operation (a=3)	Note
				X, y, z word length	16 Bits	16 Bits	Annotate	1
Resource consumption	1964 logical blocks (39%)	2142 logical blocks (42%)	Annotate 2
				The highest realization frequency	43.85MHZ	42.73MHZ	Annotate	2
Radius precision (LSB)	-0.52(0 1.04)	-0.33(0 0.66)	Annotate 3
				Phase accuracy (LSB)	1.03(-12.0 12.15)	0.81(-3.26 3.41)	Annotate 3

Annotate 1: in simulation process, when not adopting shift left operation, the word length of x, y expands to 18Bits (2bits moves to left); When adopting shift left operation and a=1, the word length of x, y expands to 19Bits (3bits moves to left); During a=2, the word length of x, y expands to 21Bits (5bits moves to left); During a=3, the word length of x, y expands to 24Bits (8bits moves to left).Z comprises the 15Bits decimal place.

Annotate 2: emulation realizes in the FPGA of U.S. altera corp, and has adopted pipeline organization.

Annotate 3: be absolute average error, be respectively maximum negative sense sum of errors maximum forward error in the bracket.

As can be seen, adopt the number of times of shift left operation from top two forms, promptly a value is high more, and the precision of radius and phase place increases thereupon, and correspondingly, resource consumption also increases thereupon, and the highest frequency of computing descends thereupon.Therefore taking all factors into consideration preferably, this a value is 3.

The present invention is used for the coordinate conversion processor of digital scan converter, in order to the rectangular coordinate value (x0, y0) input be converted to the polar coordinates value (r, p) output, can adopt FPGA to realize, and this coordinate conversion processor comprises:

The input and pretreatment module, receive described rectangular coordinate input value, and produce corresponding constant value N, | x0| and | y0|, and phase place judgment variable Xs and Ys, angle variables z (0) and symbolic variable cout _iInitial value;

The interative computation module, according to described | x0| and | y0|, constant value N, angle variables z (0) and symbolic variable cout _iCarry out N time cordic algorithm iteration; This interative computation module comprises two modules: first module and second module, and described first module realizes a CORDIC interative computation with shift left operation, that is: i is from 0 to a-1, is 1 to increase progressively cycle calculations by step-length:

x(i+1)＝2 ⁱ＊x(i)+y(i)；y(i+1)＝|2 ⁱ＊y(i)-x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(2 ⁱ＊y(i)-x(i))；

This module comprises the circuit unit of realizing each interative computation: two shift left operation devices, two no symbol adder calculators and a signed magnitude arithmetic(al) device are used for described x (i+1), the calculating of y (i+1); A no symbol totalizer is used for the calculating of described z (i+1); A logic controller is used for described cout _I+1Calculating;

Described second module realizes (N-a) inferior CORDIC interative computation with right-shift operation, that is: i is 1 to increase progressively cycle calculations by step-length from a to N-1:

x(i+1)＝x(i)+2 ^-i＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))；

This module comprises the circuit unit of realizing each interative computation: two shift right operation devices, two no symbol adder calculators and a signed magnitude arithmetic(al) device are used for described x (i+1), the calculating of y (i+1); A no symbol totalizer is used for the calculating of described z (i+1); A logic controller is used for described cout _I+1Calculating;

Radius correcting module and phase place correcting module, according to the output of described interative computation module calculate described polar coordinates value (r, p) and output, the multiplicative operator that described radius correcting module or phase place correcting module comprise or shift right operation device are realized column count down:

R=1/A*X ' _NWherein $A=\underset{\mathrm{<figure-callout\; id="1"\; label="N"\; filenames="C0314001500152.png,C0314001500153.png"\; state="\{\{state\}\}">N</figure-callout>}}{\mathrm{\&Pi;}}\sqrt{1+2^{-2i}},$ ${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i,$

P=z (N)/2 ^N, if (Xs, Ys)=(0,0), p=p; If (Xs, Ys)=(1,0), p=π-p;

If (Xs, Ys)=(1,1), p=π+p; If (Xs, Ys)=(0,1), p=2 π-p;

Output module, with described r, the output of p value.

The coordinate conversion processor that the present invention is used for digital scan converter further illustrates below:

For accelerating the arithmetic speed of cordic algorithm, each iteration has all adopted a stage pipeline structure, though independent data of conversion need N cycle like this, but concerning data stream, but can all finish linear transformation (bulk delay N cycle as a result) each cycle, according to processor theory diagram shown in Figure 1, each module is provided specific description below:

Load module: accept the signal x that front-end circuit is sent here ₀, y ₀, the initial work of carrying out the iterative formula computing is carried out assignment to constant and the initializaing variable of using.

Pretreatment module: distinguish signal x ₀, y ₀Symbol, and give Xs and Ys respectively with its symbol.

Interative computation module: carry out computing according to the iterative equation group, can be divided into two submodules:

Iteration first module: carry out computing according to system of equations (10), i.e. cancellation cut position error in iteration, the value of a can be according to the consideration of compromising of the realization speed of resource consumption and algorithm, and the particular circuit configurations of its computing each time comprises as shown in Figure 2:

Be used for x (i+1), two shift left operation devices that y (i+1) calculates, two no symbol adder calculators and a signed magnitude arithmetic(al) device; Be used for the no symbol totalizer that z (i+1) calculates; Be used for cout _I+1A logic controller that calculates.

Iteration second module: carry out computing according to system of equations (9), realize (N-a) inferior CORDIC interative computation with right-shift operation.Consider and do not cancel the cut position error in iteration, the value available software emulation of b obtains, and its implication is, if in the b time iteration, and y _bWidth smaller or equal to (b+1), then y _bMove to right (b+1) position after equal zero, at this moment, x _bRemain unchanged.In the iteration afterwards, because y _iFurther reduce the increase with i, x _iTo remain constant, according to the x that exists corresponding to the b value _iChange, this module can comprise b value front module and b value back module successively.Wherein, the particular circuit configurations of the computing each time of described second module that comprises b value front module comprises as shown in Figure 3:

Be used for x (i+1), two shift right operation devices that y (i+1) calculates, two no symbol adder calculators and a signed magnitude arithmetic(al) device; Be used for the no symbol totalizer that z (i+1) calculates; Be used for cout _I+1A logic controller that calculates.

And b value back module because of during x _iNo longer change, so do not carry out the interative computation of its formula, other then carry out computing according to system of equations (9), and the particular circuit configurations of its computing each time comprises as shown in Figure 4:

Be used for the latch that x (i+1) calculates; Be used for the shift right operation device that y (i+1) calculates, a no symbol adder calculator and a signed magnitude arithmetic(al) device; Be used for the no symbol totalizer that z (i+1) calculates; Be used for cout _I+1A logic controller that calculates.

Radius correcting module: according to system of equations (2) and equation (11), because the radius r that obtains has a factors A and will move to right after the iteration, so will revise radius by a multiplicative operator and a shift operation device

The phase place correcting module: the value according to Xs, Ys (is x ₀, y ₀The quadrant at place) p is revised.

Output module: the radius r and the phase place p that will carry out revising output to back-end circuit.

Claims (8)

1. coordinate transformation method that is used for digital scan converter, in order to the rectangular coordinate value of input (x0, y0) be converted to the polar coordinates value (r, p) output is characterized in that, comprises step:

1.. receive x0 from front-end circuit by the input of described device and pretreatment module, y0 carries out assignment and output to constant and the variable of using, and comprising:

Angle variables z (0) is initialized as 0;

Symbolic variable cout _iBe initialized as 1;

According to the rectangular coordinate value (x0 y0) comes initialization phase place judgment variable Xs, Ys, and this (x0 y0) is converted to unsigned number, that is:

If X0＜0, then Xs=1; If Y0＜0, then Ys=1; And (x0, y0)=(| x0|, | y0|);

2.. the CORDIC interative computation module of described device divides two stages to carry out iteration N time according to the constant and the variable of described output:

Phase one: carry out the cordic algorithm iteration a time with shift left operation, that is:

I is from 0 to a-1, is 1 to increase progressively cycle calculations by step-length:

x(i+1)＝2 ⁱ＊x(i)+y(i)；y(i+1)＝|2 ⁱ＊y(i)-x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(2 ⁱ＊y(i)-x(i))；

Subordinate phase: carry out (N-a) inferior cordic algorithm iteration with right-shift operation, that is:

I is 1 to increase progressively cycle calculations by step-length from a to N-1:

x(i+1)＝x(i)+2 ^-i＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i*tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))；

3.. the radius correcting module of described device calculates revised radius r according to the output of described N iteration:

$A=\underset{N}{\mathrm{\&Pi;}}\sqrt{1+2^{-2i}},$ ${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i,$ r＝1/A＊X′ _N；

4.. the phase place correcting module of described device calculates phase place p according to the output of described N iteration, and according to described phase place judgment variable Xs, Ys adjusts correction:

p＝z(N)/2 ^N，

If (Xs, Ys)=(0,0), the p value is not adjusted; If (Xs, Ys)=(1,0), p=π-p;

If (Xs, Ys)=(1,1), p=π+p; If (Xs, Ys)=(0,1), p=2 π-p.

2. the coordinate transformation method that is used for digital scan converter as claimed in claim 1 is characterized in that: the 2. middle subordinate phase of described step also can be further divided into two interative computation stages of carrying out successively:

The b value last stage: carry out the iteration of (b-a) inferior cordic algorithm with right-shift operation, that is:

I is 1 to increase progressively cycle calculations by step-length from a to b-1:

x(i+1)＝x(i)+2 ^-i＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))；

B value after-stage: carry out the iteration of (N-b) inferior cordic algorithm with right-shift operation, but stop interative computation, that is: to the x variable

I is 1 to increase progressively cycle calculations by step-length from b to N-1:

x(i+1)＝x(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))。

3. the coordinate transformation method that is used for digital scan converter as claimed in claim 1 or 2 is characterized in that:

The described step 2. preferred value of middle a is 3.

4. coordinate conversion processor that is used for digital scan converter, in order to the rectangular coordinate value (x0, y0) input be converted to the polar coordinates value (r, p) output is characterized in that, comprising:

The input and pretreatment module, receive described rectangular coordinate input value, and produce corresponding constant value N, | x0| and | y0|, and phase place judgment variable Xs and Ys, angle variables z (0) and symbolic variable cout _iInitial value;

The interative computation module, according to described | x0| and | y0|, constant value N, angle variables z (0) and symbolic variable cout _iCarry out N time cordic algorithm iteration; This interative computation module comprises two modules: first module and second module, and described first module realizes a CORDIC interative computation with shift left operation, that is: i is from 0 to a-1, is 1 to increase progressively cycle calculations by step-length:

x(i+1)＝2 ⁱ＊x(i)+y(i)；y(i+1)＝|2 ⁱ＊y(i)-x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(2 ⁱ＊y(i)-x(i))；

This module comprises the circuit unit of realizing each interative computation: two shift left operation devices, two no symbol adder calculators and a signed magnitude arithmetic(al) device are used for described x (i+1), the calculating of y (i+1); A no symbol totalizer is used for the calculating of described z (i+1); A logic controller is used for described cout _I+1Calculating;

Described second module realizes (N-a) inferior CORDIC interative computation with right-shift operation, that is: i is 1 to increase progressively cycle calculations by step-length from a to N-1:

x(i+1)＝x(i)+2 ^-i＊y(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

Z (i+1)=z (i)+cout _i* tan ^-12 ^-iCout _I+1=cout _i⊙ sign (y (i)-2 ^-i* x (i)); This module comprises the circuit unit of realizing each interative computation: two shift right operation devices, two no symbol adder calculators and a signed magnitude arithmetic(al) device are used for described x (i+1), the calculating of y (i+1); A no symbol totalizer is used for the calculating of described z (i+1); A logic controller is used for described cout _I+1Calculating;

Radius correcting module and phase place correcting module, according to the output of described interative computation module calculate described polar coordinates value (r, p) and output, the multiplicative operator that described radius correcting module or phase place correcting module comprise or shift right operation device are realized column count down:

R=1/A*X ' _NWherein $A=\underset{N}{\mathrm{\&Pi;}}\sqrt{1+2^{-2i}},$ ${X^{\&prime;}}_N=X_N>>\underset{i=0}{\overset{a}{\mathrm{\&Sigma;}}}i,$

P=z (N)/2 ^N, if (Xs, Ys)=(0,0), p=p; If (Xs, Ys)=(1,0), p=π-p;

If (Xs, Ys)=(1,1), p=π+p; If (Xs, Ys)=(0,1), p=2 π-p;

Output module, with described r, the output of p value.

5. as being used for the coordinate conversion processor of digital scan converter as described in the claim 4, it is characterized in that described second module comprises successively two modules according to the existence of b value:

B value front module comprises the described circuit unit that comprises two shift right operation devices, realizes that with right-shift operation i amounts to (b-a) inferior corresponding CORDIC interative computation from a to b-1;

B value back module, comprise the simplification circuit unit of realizing each interative computation: a latch is used for the calculating of x (i+1); A shift right operation device, a no symbol adder calculator and a signed magnitude arithmetic(al) device are used for the calculating of y (i+1); A no symbol totalizer is used for the calculating of z (i+1); A logic controller is used for cout _I+1Calculating;

Thereby this module realizes the constant CORDIC interative computation of (N-b) inferior x variable with right-shift operation, that is: i is 1 to increase progressively cycle calculations by step-length from b to N-1:

x(i+1)＝x(i)；y(i+1)＝|y(i)-2 ^-i＊x(i)|；

z(i+1)＝z(i)+cout _i＊tan ^-12 ^-i；cout _i+1＝cout _i⊙sign(y(i)-2 ^-i＊x(i))。

6. as being used for the coordinate conversion processor of digital scan converter as described in claim 4 or 5, it is characterized in that:

Described coordinate conversion processor is realized with FPGA.

7. as being used for the coordinate conversion processor of digital scan converter as described in claim 4 or 5, it is characterized in that:

Each iteration adopts a stage pipeline structure in the described interative computation module.

8. described in claim 4 or 5, be used for the coordinate conversion processor of digital scan converter, it is characterized in that:

The preferred value of a is 3 in the described interative computation module.

Images