CN100390697C - Device and method for encrypting protection to instruction using check bit element - Google Patents
Device and method for encrypting protection to instruction using check bit element Download PDFInfo
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- CN100390697C CN100390697C CNB2004100018228A CN200410001822A CN100390697C CN 100390697 C CN100390697 C CN 100390697C CN B2004100018228 A CNB2004100018228 A CN B2004100018228A CN 200410001822 A CN200410001822 A CN 200410001822A CN 100390697 C CN100390697 C CN 100390697C
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Abstract
The present invention relates to a device and a method utilizing check bits to carry out encrypted protection on instructions. The device comprises a check bit generation device, a first check bit position generation device and a check bit insertion device, wherein the check bit generation device generates a check bit according to an instruction to be output; the instruction has many bits; the first check bit position generation device generates check bit insertion positions N(N is positive integer) according to the instruction and a preset rule; the check bit insertion device generates the insertion positions N according to the first check bit position generation device, the check bits are inserted to the (N-1)st bit and the Nth bit of the instruction, and thus, an encrypted instruction is generated.
Description
Technical field
The invention relates to the technical field of processor instruction encipherment protection, refer to a kind of devices and methods therefor that utilizes the inspection bit processor instruction to be carried out encipherment protection especially.
Background technology
Pay attention to the epoch of the intelligence ownership of property at this; the relevant Wise properties such as program of manufacturer in order to protect its arduous exploitation; can the advanced row one of this supervisor be encrypted (encrypting) when off-line (off-line) handles; program after will encrypting again is to be stored to a non-volatile or other Storage Medias; even other people take non-volatile or other Storage Medias that has this encipheror; owing to can't know the process and the disposal route of this encryption; also can't correctly remove to reduce this supervisor, reach the purpose of protection therefrom.
At this kind programmed protection mode; in U.S. USP6; 4032; in No. 073 patent announcement; use a virtual random number producer (Pseudo Random Generator) and foundation one initial value (seedl/seed2); come read-only memory (Read Only Memory; ROM) money section (ROM data) encodes to produce enciphered data (Encoded data); yet this kind information protection mode is done the parameter of encryption because of using random number, synchronous random number producer need be arranged in order to decode.The template (pattern) that needs very many random numbers could prevent effectively that other people from reducing this supervisor, and the virtual random number producer of agreeable flavor work coding and decoding needs quite complicated circuit, and this can increase many costs.If use the virtual random number producer of better simply coding and decoding, though escapable cost, but reduced this supervisor by other people easily, therefore, the design of the condition processor instruction disposal route of well known processor still has many disappearances and gives improved necessity.
Summary of the invention
The object of the present invention is to provide a kind of the utilization to check that bit carries out the devices and methods therefor of encipherment protection to processor instruction, to avoid known technology because of the caused challenge of need complicated hardware circuit, simultaneously, improves the procedure code privacy degrees.
According to a characteristic of the present invention, propose a kind ofly checking that bit carries out the device of encipherment protection to processor instruction, this device comprises one and checks that bit generation device, one first checks that bit position generation device and checks bit insertion device.This inspection bit generation device is to check bit according to the processor instruction of desire output to produce one, and this processor instruction has a plurality of bits; This first inspection bit position generation device is according to this processor instruction and the predetermined insertion position N (N be positive integer) of rule to produce this parity check bit; And this inspection bit to insert device be first to check the insertion position N that bit position generation device is produced according to this, this inspections bit is inserted among the mat woven of fine bamboo strips N-1 bit and N bit of this processor instruction, instruct to produce an encryption processor.
According to another characteristic of the present invention, propose a kind ofly checking that bit carries out the device of encipherment protection to processor instruction, this device comprises one and checks that bit generation device, one first checks that bit position generation device and checks bit insertion device.This processor instruction of checking that the bit generation device is exported according to a desire is checked bit through an inspection calculation apparatus to produce P, and P is the positive integer more than or equal to, and this processor instruction has a plurality of bits; This first check bit position generation device according to this processor instruction and a predetermined rule to produce the insertion position N1 of this inspection bit ... Np (N, P are integer); And, this inspection bit inserts the insertion position N1 that device is produced according to this first inspection bit position generation device ... Np with this P inspection bit, inserts respectively among the Nx-1 bit and Nx bit of this processor instruction, x=1 wherein ... P is to produce encryption processor instruction.
According to a characteristic more of the present invention; propose a kind of to check that bit carries out the device of encipherment protection to processor instruction; each processor instruction has an operation code (op code), and this device comprises one and checks that bit generation device, one first inspection bit position generation device and an inspection bit insert device.This inspection bit generation device is checked bit according to the processor instruction of desire output to produce one, and this processor instruction has a plurality of bits; This first inspection bit position generation device is according to the operation code and the predetermined insertion position N (N be positive integer) of rule to produce this inspection bit of this processor instruction, and wherein, this insertion position N is not the position of this operation code in this processor instruction; And this inspection bit inserts device according to the insertion position N that this first inspection bit position generation device is produced, and this inspection bit is inserted among the N-1 bit and N bit of this processor instruction, to produce encryption processor instruction.
According to another characteristic of the present invention; propose a kind of to check that bit carries out the encipherment protection device to processor instruction; each processor instruction has an operation code (op code), and this device comprises one and checks that bit generation device, one first inspection bit position generation device and an inspection bit insert device.This processor instruction of checking that the bit generation device is exported according to a desire is checked bit through an inspection calculation apparatus to produce P, and this processor instruction has a plurality of bits; This first check bit position generation device according to the operation code of this processor instruction and a predetermined rule to produce the insertion position N1 of this inspection bit ... Np (N, P are integer), wherein, this insertion position N1 ... Np (N, P are integer) is not the position of this operation code in this processor instruction; And this checks that bit inserts device, first checks the insertion position N1 that bit position generation device is produced according to this ... Np, check bit with this P, insert respectively among the Nx-1 bit and Nx bit of this data, wherein x=1 ... P is to produce encryption processor instruction.
According to a characteristic more of the present invention, a kind of method of processor instruction being carried out encipherment protection with parity check bit is proposed, it comprises the following step: (A) processor instruction of foundation one desire output is to produce a parity check bit, and this processor instruction has a plurality of bits; (B) according to this processor instruction and a predetermined rule to produce the insertion position N of this parity check bit; And the insertion position N that (C) is produced according to step (B), the parity check bit that step (A) is produced inserts among the N-1 bit and N bit of this processor instruction, to produce encryption processor instruction.
According to a characteristic more of the present invention, propose a kind of to check that bit carries out the method for encipherment protection to processor instruction, this method comprises the following step: (A) check that through one calculating rule checks bit to produce P according to the processor instruction of desire output, P is the positive integer more than or equal to; (B) according to this processor instruction and predetermined first rule to produce the insertion position N1 of this parity check bit ... Np (N, P are integer); And the insertion position N1 that (C) is produced according to step (B) ... Np, with step (A) this P that produces check and bit to insert among the Nx-1 bit and Nx bit of this processor instruction, wherein x=1 respectively ... P is to produce encryption processor instruction.
According to a characteristic more of the present invention, propose a kind of to check that bit carries out the method for encipherment protection to processor instruction, each processor instruction has an operation code, this method mainly comprises the following step: (A) check bit according to the processor instruction of desire output to produce one, this processor instruction has a plurality of bits; (B) according to the operation code and the predetermined insertion position N (N be positive integer) of rule to produce this inspection bit of this processor instruction, wherein, this insertion position N is not the position of this operation code in this processor instruction; And the insertion position N that (C) is produced according to step (B), the inspection bit that step (A) is produced inserts among the N-1 bit and N bit of this processor instruction, to produce encryption processor instruction.
According to a characteristic more of the present invention, propose a kind of to check that bit carries out the method for encipherment protection to processor instruction, each processor instruction has an operation code, this method mainly comprises the following step: (A) check that through one calculating rule checks bit to produce P according to the processor instruction of desire output, P is the positive integer more than or equal to; (B) be scheduled to first rule to produce the insertion position N1 of this inspection bit according to the operation code and of this processor instruction ... Np (N, P are integer), wherein, this insertion position N1 ... Np is not the position of this operation code in this processor instruction; And the insertion position N1 that (C) is produced according to step (B) ... Np with this P inspection bit, inserts respectively among the Nx-1 bit and Nx bit of this processor instruction, wherein x=1 ... P is to produce encryption processor instruction.
Description of drawings
Fig. 1: the present invention carries out the Organization Chart of encipherment protection device to check bit to processor instruction.
Fig. 2: the insertion position synoptic diagram of one embodiment of the invention.
Fig. 3: the insertion position synoptic diagram of another embodiment of the present invention.
Fig. 4: according to an exemplary applications of the present invention.
Embodiment
Fig. 1 shows that the present invention utilizes and checks that bit carries out the calcspar of encipherment protection device to processor instruction, and it includes one and checks that bit generation device 110, one first checks that bit position generation device 120, checks that bit inserts device 130, one second and checks that bit position generation device 210 and checks bit removal device 220.Wherein, this inspection bit generation device 110, first is checked bit position generation device 120 and checks that bit inserts device 130 processor instruction of desire output is encrypted that second checks bit position generation device 210 and check that bit removal device 220 is then deciphered the processor instruction of encrypting.
Aforementioned inspection bit generation device 110 is checked bit according to the I bit processor instruction of desire output to produce P, and for convenience of description, in the present embodiment, this processor instruction is 31 bits (I=31), and this inspection bit is 1 bit (P=1).And this processor instruction also can be 30 yuan (I=30), and this moment, this inspection bit was 2 bits (P=2).So, this encryption processor instruction is 32 bits, in the read-only memory (ROM) or other non-volatile that conveniently are stored in existing specification.This 31 bit processor instruction can be handled via a mutual exclusion or the lock (XOR) with 31 input ends and an output terminal, can obtain the parity check bit of this 1 bit.
Above-mentioned inspection bit is except being the parity check bit, also can be error correcting code (ErrorCorrection Code, ECC) or Cyclic Redundancy Code (Cyclic Redundancy Code, form such as CRC).
This mat woven of fine bamboo strips one inspection bit position generation device 120 is scheduled to rule to produce this P insertion position N1 that checks bit according to this processor instruction form and ... Np (N, P are integer), for example, produce the Integer N 1 of representing the insertion position with a key assignments (Key) via a functional operation f (K) ... Np, that is this Integer N 1 ... on behalf of the inspection bit of this P bit, Np will be placed on position in the instruction of this I bit processor.
Fig. 2 is the synoptic diagram that this first inspection bit position generation device 120 produces the Integer N of representing the insertion position, first checks form and the predetermined rule of bit position generation device 120 according to processor instruction # 0, to produce the insertion position N of this inspection bit, for example the operation code of processor instruction #0 (OP) is positioned at the 31st to 24 bit, by finding in the operation code (OP) that this is (RI-form) processor instruction of one " working storage-immediate value ", promptly the 23rd to 16 bit is a working storage, and the 15th to 0 bit is the processor instruction form of immediate value.This first check bit position generation device 120 detect this processor instruction for " working storage-immediate value " (RR-form), then calculate the insertion position of checking bit according to the predefined rule.This Integer N of checking the bit position is limited to 23 to 16 in this example, the inspection bit that also is about to 1 bit is placed on working storage coded-bit place (the 23rd to 16 bit), produces the Integer N of representing the insertion position with a key assignments (Key) via a functional operation f (K) again.
For example it is " working storage-working storage " (RR-form) processor instruction to processor instruction # 1 as can be known according to its operation code (OP), and promptly the 23rd to 16 bit is working storage Rd, and the 15th to 8 bit is that working storage Rs 1, the 7 to 0 bit is working storage Rs2.This first check bit position generation device 120 detect this processor instruction for " working storage-working storage " (RR-form), then calculate the insertion position of checking bit according to the predefined rule, then the Integer N with the insertion position is limited to 7 to 0, the inspection bit that also is about to 1 bit is placed on working storage Rs2 coded-bit place (the 7th to 0 bit), produces the Integer N of representing the insertion position with a key assignments (Key) via a functional operation f (K) again.Thus, the Integer N of inspection bit insertion position more is difficult to conjecture.
Fig. 3 is the synoptic diagram that this first inspection bit position generation device 120 produces another embodiment of the Integer N of representing the insertion position, the first inspection bit position generation device 120 is scheduled to rule to produce the insertion position N of this inspection bit according to the order code content and of processor instruction, for example processor instruction #2 is for after carrying out additive operation to a working storage Rs1 and a working storage Rs2, again the tool operation result is stored among the working storage Rd, wherein the operation code of processor instruction #2 (Add) is positioned at the 31st to 24 bit, working storage Rd is positioned at the 23rd to 16 bit, working storage Rs1 is positioned at the 15th to 8 bit, and working storage Rs2 is positioned at the mat woven of fine bamboo strips 7 to 0 bits.120 Integer N with the insertion position of this first inspection bit position generation device are limited to 7 to 0, the inspection bit that also is about to 1 bit is placed on working storage Rs2 coded-bit place (the 7th to 0 bit), produces the Integer N of representing the insertion position with a key assignments (Key) via a functional operation f (K) again.
Processor instruction #3 is for after carrying out subtraction to a working storage Rs1 and a working storage Rs2, again its operation result is stored among the working storage Rd, wherein the operation code of processor instruction #3 (Sub) is positioned at the 31st to 24 bit, working storage Rd is positioned at the 23rd to 16 bit, working storage Rs 1 is positioned at the 15th to 8 bit, and working storage Rs2 is positioned at the 7th to 0 bit.120 Integer N with the insertion position of this first inspection bit position generation device are limited to 15 to 8, the inspection bit that also is about to 1 bit is placed on working storage Rs 1 coded-bit place (the 15th to 3 bit), produces the Integer N of representing the insertion position with a key assignments (Key) via a functional operation f (K) again.
Processor instruction #4 is for after carrying out multiplying to a working storage Rs1 and a working storage Rs2, again its operation result is stored among the working storage Rd, wherein the operation code of processor instruction #4 (Sub) is positioned at the 31st to 24 bit, working storage Rd is positioned at the 23rd to 16 bit, working storage Rs 1 is positioned at the 15th to 8 bit, and working storage Rs2 is positioned at the 7th to 0 bit.120 Integer N with the insertion position of this first inspection bit position generation device are limited to 23 to 16, the inspection bit that also is about to 1 bit is placed on working storage Rd coded-bit place (the 23rd to 16 bit), produces the Integer N of representing the insertion position with a key assignments (Key) via a functional operation f (K) again.
It is the insertion position Nx (x=1 that produced according to this first inspection bit position generation device 120 that this inspection bit inserts device 130 ... P, x is for counting just a bit), the inspection bit of this P bit is inserted among the Nx-1 bit and Nx bit of this I bit processor instruction, to produce one (I+P) bit encryption data.
The aforementioned Integer N of obtaining 1 ... Np also can represent the integer of insertion position with generation through a rotation function computing to the right, or represents the integer of insertion position with generation through a rotation function computing left.Thus, can increase the random degree of the Integer N of representing this insertion position, make this insertion position embarrass extraneous the derivation to learn.
This second inspection bit position generation device 210 is the insertion position N1 that produce this inspection bit with this processor instruction and this predetermined rule ... Np, that is, produce the Integer N 1 of representing the insertion position with key assignments K via a functional operation f (K) ... Np, this Integer N 1 ... on behalf of the inspection bit of this P bit, Np promptly be placed on position in this (I+P) bit encryption processor instruction.(I+P) bit encryption processor instruction is somebody's turn to do in these inspection bit removal device 220 inputs, and second check the insertion position N1 that bit position 210 generation devices are produced according to this ... Np, N1 with input data ... the Np bit is removed, and obtains the processor instruction of deciphering.
Fig. 4 shows an exemplary applications of the technology of the present invention, wherein, program 610 has a plurality of 31 bit processor instructions, this program 610 can be about to the planted inspection bit of 1 bit of each 31 bit processor instruction in this program 610 earlier earlier via technology of the present invention, convert program 620 according to this to, this program 620 is stored in the reservoir 630 again.So, this encipheror 620 is 32 bits, in the read-only memory (ROM) or other non-volatile that conveniently are stored in existing specification.This kind transfer process can be used a software to carry out off-line (off-line) and handle.
And general processor 640 is when this program 620 of execution; it will be by capturing program 620 in this reservoir 630; this second inspection bit position generation device 210 produces the insertion position N that this checks bit; this checks bit removal device 220 these 32 bit encryption processor instructions of input; and second check the insertion position N that bit position 210 generation devices are produced according to this; the N bit of input data is removed, and the processor instruction of acquisition deciphering, to reach the purpose of defence program.
As shown in the above description; the technology of the present invention need not to use this complicated hardware circuit of virtual random number producer (Pseudo Random Generator) as known technology; can reach the purpose of defence program; because hardware circuit is simple than known technology, it is better far beyond known technology that it carries out usefulness simultaneously.
It should be noted that above-mentioned many embodiment give an example for convenience of explanation, the interest field that the present invention advocated should be as the criterion so that claim is described certainly, but not only limits to the foregoing description.
Claims (61)
1. one kind to check that bit carries out the device of encipherment protection to processor instruction, and this device comprises:
One checks the bit generation device, checks bit according to this processor instruction of desire output to produce one, and this processor instruction has a plurality of bits;
One first checks the bit position generation device, and to produce the insertion position N of this inspection bit, this N is a positive integer according to this processor instruction and a predetermined rule for it; And
One checks that bit inserts device, and the insertion position N according to this first inspection bit position generation device is produced inserts this inspection bit among the N-1 and N bit of this processor instruction, to produce encryption processor instruction.
2. device as claimed in claim 1 is characterized in that, also comprises:
One second checks the bit position generation device, its according to this processor instruction and this predetermined rule to produce the insertion position of this inspection bit; And
One checks the bit removal device, imports this processor instruction, and second checks the insertion position N that bit position generation device is produced according to this, so that the N bit of this processor instruction is removed.
3. device as claimed in claim 2 is characterized in that, wherein this first and second check the bit position generation device be according to this processor instruction form and a particular value integer through a rotation function computing to the right to produce the insertion position.
4. device as claimed in claim 2 is characterized in that, wherein this inspection bit position generation device be according to the form of this processor instruction and a particular value integer through a rotation function computing left to produce the insertion position.
5. device as claimed in claim 1 is characterized in that, wherein this processor instruction is 31 bits.
6. device as claimed in claim 1 is characterized in that, inspection bit wherein is a parity check bit.
7. device as claimed in claim 1 is characterized in that, inspection bit wherein is that error correcting code is checked bit.
8. device as claimed in claim 1 is characterized in that, inspection bit wherein is the Cyclical Redundancy Check bit.
9. one kind to check that bit carries out the device of encipherment protection to processor instruction, and this device comprises:
One checks the bit generation device, checks bit through an inspection calculation apparatus to produce P according to this processor instruction of desire output, and P is the positive integer more than or equal to 1, and this processor instruction has a plurality of bit I bits;
One first checks the bit position generation device, its according to this processor instruction and a predetermined rule to produce the insertion position N of this inspection bit
1... N
p, N wherein
PBe positive integer; And
One checks that bit inserts device, first checks the insertion position N that bit position generation device is produced according to this
1... N
p,, insert the N of this processor instruction respectively with this P inspection bit
x-1 bit and N
xAmong the bit, x=1...P wherein is to produce a processor instruction of encrypting.
10. device as claimed in claim 9 is characterized in that it also comprises:
One second checks the bit position generation device, its according to this processor instruction and this predetermined rule to produce the insertion position N of this inspection bit
1... N
pAnd
One checks the bit removal device, imports this processor instruction, and second checks the insertion position N that bit position generation device is produced according to this
1... N
p, so that P inspection bit of this processor instruction removed.
11. device as claimed in claim 9 is characterized in that, inspection calculation apparatus wherein is the parity check device.
12. device as claimed in claim 9 is characterized in that, inspection calculation apparatus wherein is the error correcting code device.
13. device as claimed in claim 9 is characterized in that, inspection calculation apparatus wherein is the Cyclical Redundancy Check device.
14. device as claimed in claim 10 is characterized in that, wherein this first and second check the bit position generation device be according to the form of this processor instruction and a particular value integer through a rotation function computing to the right to produce the insertion position.
15. device as claimed in claim 10 is characterized in that, wherein this inspection bit position generation device be according to the form of this processor instruction and a particular value integer through a rotation function computing left to produce the insertion position.
16. device as claimed in claim 9 is characterized in that, wherein I+P=32.
17. one kind to check that bit carries out the device of encipherment protection to processor instruction, this each processor instruction has an operation code, and this device comprises:
One checks the bit generation device, checks bit according to this processor instruction of desire output to produce one, and this processor instruction has a plurality of bit I bits;
One first checks the bit position generation device, and to produce the insertion position N of this inspection bit, N is a positive integer according to the operation code of this processor instruction and a predetermined rule for it; And
One checks that bit inserts device, and the insertion position N according to this first inspection bit position generation device is produced inserts this inspection bit among the N-1 bit and N bit of this processor instruction, to produce a processor instruction of encrypting.
18. device as claimed in claim 17 is characterized in that, it also comprises:
One second checks the bit position generation device, its according to the operation code of this processor instruction and this predetermined rule to produce the insertion position of this inspection bit; And
One checks the bit removal device, imports the processor instruction of this encryption, and second checks the insertion position N that bit position generation device is produced according to this, so that the N bit of this processor instruction is removed.
19. device as claimed in claim 18 is characterized in that, wherein this first and second check the bit position generation device be according to this processor instruction operation code and a particular value integer through a rotation function computing to the right to produce the insertion position.
20. device as claimed in claim 18 is characterized in that, wherein this first and second check the bit position generation device be according to this processor instruction operation code and a particular value integer through a rotation function computing left to produce the insertion position.
21. device as claimed in claim 17 is characterized in that, wherein this processor instruction is 31 bits.
22. device as claimed in claim 17 is characterized in that, inspection bit wherein is a parity check bit.
23. device as claimed in claim 17 is characterized in that, inspection bit wherein is that error correcting code is checked bit.
24. device as claimed in claim 17 is characterized in that, inspection bit wherein is the Cyclical Redundancy Check bit.
25. one kind to check that bit carries out the device of encipherment protection to processor instruction, this each processor instruction has an operation code, and this device comprises:
One checks the bit generation device, checks bit through an inspection calculation apparatus to produce P according to the processor instruction of desire output, and this processor instruction has a plurality of bit I bits;
One first checks the bit position generation device, its according to the operation code of this processor instruction and a predetermined rule to produce the insertion position N of this inspection bit
1... N
p, this N
PBe positive integer, wherein, this insertion position N
1... N
pBe not the position of this operation code in this processor instruction; And
One checks that bit inserts device, first checks the insertion position N that bit position generation device is produced according to this
1... N
p,, insert the N of this processor instruction respectively with this P inspection bit
x-1 bit and N
xAmong the bit, x=1...P wherein is to produce a processor instruction of encrypting.
26. device as claimed in claim 25 is characterized in that, it also comprises:
One second checks the bit position generation device, its according to the operation code of this processor instruction and this predetermined rule to produce the insertion position N of this inspection bit
1... N
PAnd
One checks the bit removal device, imports the processor instruction of this encryption, and second checks the insertion position N that bit position generation device is produced according to this
1... N
P, so that P inspection bit of this encryption processor instruction removed.
27. device as claimed in claim 25 is characterized in that, inspection calculation apparatus wherein is the parity check device.
28. device as claimed in claim 25 is characterized in that, inspection calculation apparatus wherein is the error correcting code device.
29. device as claimed in claim 25 is characterized in that, inspection calculation apparatus wherein is the Cyclical Redundancy Check device.
30. device as claimed in claim 25 is characterized in that, wherein this first and second check the bit position generation device be according to this processor instruction operation code and a particular value integer through a rotation function computing to the right to produce the insertion position.
31. device as claimed in claim 25 is characterized in that, wherein this first and second check the bit position generation device be according to this processor instruction operation code and a particular value integer through a rotation function computing left to produce the insertion position.
32. device as claimed in claim 25 is characterized in that, wherein I+P=32.
33. one kind to check that bit carries out the method for encipherment protection to processor instruction, this method mainly comprises the following step:
(A) check bit according to this processor instruction of desire output to produce one, this processor instruction has a plurality of bits;
(B) according to this processor instruction and a predetermined rule to produce the insertion position N of this inspection bit; And
(C) the insertion position N that is produced according to step (B), the inspection bit that step (A) is produced insert among the N-1 bit and N bit of this processor instruction, to produce a processor instruction of encrypting.
34. method as claimed in claim 33 is characterized in that, it also comprises the following step:
(D) import the processor instruction of this encryption;
(E) according to this processor instruction and rule to produce the insertion position N of this inspection bit; And
(F) the insertion position N that is produced according to step (E) removes the N bit of this processor instruction.
35. method as claimed in claim 34 is characterized in that, wherein step (B) and (E) be according to the form of this processor instruction and a particular value integer through a rotation function computing to the right to produce the insertion position.
36. method as claimed in claim 34 is characterized in that, wherein step (B) and (E) be according to the form of this processor instruction and a particular value integer through a rotation function computing left to produce the insertion position.
37. method as claimed in claim 33 is characterized in that, wherein this processor instruction is 31 bits.
38. method as claimed in claim 33 is characterized in that, inspection bit wherein is a parity check bit.
39. method as claimed in claim 33 is characterized in that, inspection bit wherein is that error correcting code is checked bit.
40. method as claimed in claim 33 is characterized in that, inspection bit wherein is the Cyclical Redundancy Check bit.
41. one kind to check that bit carries out the method for encipherment protection to processor instruction, this method comprises the following step:
(A) check that through one calculating rule checks bit to produce P according to the processor instruction of desire output, this processor instruction has a plurality of bit I bits, and P is a positive integer;
(B) according to this processor instruction and predetermined first rule to produce the insertion position N of this inspection bit
1... N
p, N wherein
PBe positive integer; And
(C) the insertion position N that is produced according to step (B)
1... N
p, with step (A) this P that produces check bit, insert the N of this processor instruction respectively
x-1 and N
xAmong the bit, x=1...P wherein is to produce a processor instruction of encrypting.
42. method as claimed in claim 41 is characterized in that, it also comprises the following step:
(D) import the processor instruction of this encryption;
(E) according to this processor instruction and this first rule to produce the insertion position N of this inspection bit
1... N
pAnd
(F) the insertion position N that is produced according to step (E)
1... N
p, P the inspection bit that this encryption processor of importing instructs removed.
43. method as claimed in claim 41 is characterized in that, wherein this inspection calculation rule is the parity check rule.
44. method as claimed in claim 41 is characterized in that, wherein this inspection calculation rule is the error correcting code rule.
45. method as claimed in claim 41 is characterized in that, wherein this inspection calculation rule is the Cyclical Redundancy Check rule.
46. method as claimed in claim 42 is characterized in that, wherein step (B) and (E) be according to the form of this processor instruction and a particular value integer through a rotation function computing to the right to produce the insertion position.
47. method as claimed in claim 42 is characterized in that, wherein step (B) and (E) be according to the form of this processor instruction and a particular value integer through a rotation function computing left to produce the insertion position.
48. method as claimed in claim 42 is characterized in that, wherein I+P=32.
49. one kind is carried out the method for encipherment protection with parity check bit to processor instruction, this each processor instruction has an operation code, and this method mainly comprises the following step:
(A) according to this processor instruction of desire output to produce a parity check bit, this processor instruction has a plurality of bit I bits;
(B) according to the operation code of this processor instruction and a predetermined rule to produce the insertion position N of this parity check bit, this N is a positive integer, wherein, this insertion position N is not the position of this operation code in this processor instruction; And
(C) insertionization that is produced according to step (B) is put N, and the parity check bit that step (A) is produced inserts among the N-1 bit and N bit of this processor instruction, to produce a processor instruction of encrypting.
50. method as claimed in claim 49 is characterized in that, it also comprises the following step:
(D) import the processor instruction of this encryption;
(E) according to the operation code of this processor instruction and this rule to produce the insertion position N of this parity check bit; And
(F) the insertion position N that is produced according to step (E) removes the N bit in this encryption processor instruction.
51. method as claimed in claim 50 is characterized in that, wherein step (B) and (E) be according to this processor instruction operation code and a particular value integer through a rotation function computing to the right to produce the insertion position.
52. method as claimed in claim 50 is characterized in that, wherein step (B) and (E) be according to this processor instruction operation code and a particular value integer through a rotation function computing left to produce the insertion position.
53. method as claimed in claim 49 is characterized in that, wherein this processor instruction is 31 bits.
54. one kind to check that bit carries out the method for encipherment protection to processor instruction, this each processor instruction has an operation code, and this method mainly comprises the following step:
(A) check that through one calculating rule checks bit to produce P according to the processor instruction of desire output, this processor instruction has a plurality of bit I bits, and P is a positive integer;
(B) be scheduled to first rule to produce the insertion position N of this inspection bit according to the operation code and of this processor instruction
1... N
p, this N
PBe positive integer, wherein, this insertion position N
1... N
pBe not the position of this operation code in this processor instruction; And
(C) the insertion position N that is produced according to step (B)
1... N
p,, insert the N of this processor instruction respectively with this P inspection bit
x-1 bit and N
xAmong the bit, x=1...P wherein is to produce a processor instruction of encrypting.
55. method as claimed in claim 54 is characterized in that, it also comprises the following step:
(D) import the processor instruction of this encryption;
(E) according to the operation code of this processor instruction and this first rule to produce the insertion position N of this inspection bit
1... N
pAnd
(F) the insertion position N that is produced according to step (E)
1... N
p, P the inspection bit that this encryption processor of importing instructs removed.
56. method as claimed in claim 54 is characterized in that, wherein this inspection calculation rule is the parity check rule.
57. method as claimed in claim 54 is characterized in that, wherein this inspection calculation rule is the error correcting code rule.
58. method as claimed in claim 54 is characterized in that, wherein this inspection calculation rule is the Cyclical Redundancy Check rule.
59. method as claimed in claim 55 is characterized in that, wherein step (B) and (E) be according to this processor instruction operation code and a particular value integer through a rotation function computing to the right to produce the insertion position.
60. method as claimed in claim 55 is characterized in that, wherein step (B) and (E) be according to this processor instruction operation code and a particular value integer through a rotation function computing left to produce the insertion position.
61. method as claimed in claim 55 is characterized in that, wherein, and I+P=32.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100018228A CN100390697C (en) | 2004-01-14 | 2004-01-14 | Device and method for encrypting protection to instruction using check bit element |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100018228A CN100390697C (en) | 2004-01-14 | 2004-01-14 | Device and method for encrypting protection to instruction using check bit element |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1641515A CN1641515A (en) | 2005-07-20 |
| CN100390697C true CN100390697C (en) | 2008-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
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| CN107657958B (en) * | 2017-09-13 | 2020-06-23 | 厦门声连网信息科技有限公司 | Music identification system, device, music management server and method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515307A (en) * | 1994-08-04 | 1996-05-07 | Bell Communications Research, Inc. | Pseudo-random generator |
| CN1180466A (en) * | 1996-03-04 | 1998-04-29 | 诺基亚电信公司 | Improving security of packet-mode transmission in mobile communication system |
| CN1216653A (en) * | 1996-03-18 | 1999-05-12 | 株式会社东芝 | Encoder and decoder |
| US6104811A (en) * | 1996-08-16 | 2000-08-15 | Telcordia Technologies, Inc. | Cryptographically secure pseudo-random bit generator for fast and secure encryption |
-
2004
- 2004-01-14 CN CNB2004100018228A patent/CN100390697C/en not_active Expired - Fee Related
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5515307A (en) * | 1994-08-04 | 1996-05-07 | Bell Communications Research, Inc. | Pseudo-random generator |
| CN1180466A (en) * | 1996-03-04 | 1998-04-29 | 诺基亚电信公司 | Improving security of packet-mode transmission in mobile communication system |
| CN1216653A (en) * | 1996-03-18 | 1999-05-12 | 株式会社东芝 | Encoder and decoder |
| US6104811A (en) * | 1996-08-16 | 2000-08-15 | Telcordia Technologies, Inc. | Cryptographically secure pseudo-random bit generator for fast and secure encryption |
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| Publication number | Publication date |
|---|---|
| CN1641515A (en) | 2005-07-20 |
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