CN100390934C - Method for producing chip fuse and products thereof - Google Patents
Method for producing chip fuse and products thereof Download PDFInfo
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- CN100390934C CN100390934C CNB2005100642644A CN200510064264A CN100390934C CN 100390934 C CN100390934 C CN 100390934C CN B2005100642644 A CNB2005100642644 A CN B2005100642644A CN 200510064264 A CN200510064264 A CN 200510064264A CN 100390934 C CN100390934 C CN 100390934C
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Abstract
The present invention relates to a method for manufacturing a chip fuse. Firstly, a thermal insulation layer is formed on an upper surface of a base plate; secondly, a first metallic layer, a diffusion buffer layer and a second metallic layer are orderly formed on the thermal insulation layer to be used as a fuse part; subsequently, a protective layer is formed on the upper surface of the base plate, which is used for covering the second metallic layer and the diffusion buffer layer, and two end electrodes are formed on two end parts of the base plate, which is used for suppressing improper diffusion when the second metallic layer works by using the diffusion buffer layer; thus, the service life of products can be prolonged.
Description
Technical field
The present invention relates to a kind of manufacture method and finished product thereof of chip fuse, particularly relate to a kind of manufacture method and finished product thereof with chip fuse of diffusing buffer layer.
Background technology
As Fig. 1, chip fuse roughly had thermal insulation layer 12, that a substrate 11, is formed at substrate 11 upper surfaces and electroplates the first metal layer 14, that is formed on the metal film 13 in the thermal insulation layer 12 and the metal film 13, of substrate 11 upper surfaces and electroplate second metal level 15 that is formed on the first metal layer 14, the termination electrode 17 that a protective layer 16 and two that covers second metal level 15 is formed at the both ends of substrate 11 in the past.The material of the first metal layer 14 is copper (Cu), with the material of second metal level 15 be tin (Sn).So, utilize two metal levels 14,15 to be used as fuse portion, the fusing point of the first metal layer 14 is 232 degree, and the fusing point of second metal level 15 is 1064 degree.
When chip fuse was worked, along with electric current increases or the operating time increases, the chip fuse temperature increased thereupon, makes 15 fusions of second metal level and tin is diffused in the first metal layer 14.Along with the metallic tin diffusing capacity increases, the impedance of the first metal layer 14 is also increased thereupon, causes heat that electric current flows through generation significantly to increase with temperature thereupon and climbs to a higher point fast, until the first metal layer 14 fusing and open circuit, to protect other circuit unit.Therefore, the chip fuse effect is that temperature or electric current surpass critical value, and the real-time interrupt circuit working is to protect other circuit unit.
But when in fact working, under the special subcritical value, tin fusion spread condition takes place in second metal level 15 easily, will make second metal level 15 that the situation of fusion diffusion takes place when spending as circuit-line surface temperature 50, but increase with the electronic building brick integration today, and the circuit working temperature is approached 100 degree easily.If things go on like this,, make the improper increase of impedance of the first metal layer 14 and under critical value, do not burning easily, cause the chip fuse lost of life and the situation of burning easily to take place because of the improper metal diffusing of second metal level 15.
Summary of the invention
Because problem in the past, this case inventor thinks and increases by a diffusing buffer layer suppressing the improper diffusion of second metal level in first, second metal level, and then improves the situation of burning easily and prolong life of product.
A purpose of the present invention is to provide a kind of manufacture method and finished product thereof that can effectively suppress the chip fuse of the improper diffusion of metal.
Another object of the present invention is to provide a kind of manufacture method and finished product thereof that can effectively improve the chip fuse of the situation of burning easily.
Another purpose of the present invention is to provide a kind of manufacture method and finished product thereof that can effectively prolong the chip fuse of life of product.
So the manufacture method of chip fuse of the present invention comprises:
(A) form a thermal insulation layer in the upper surface of a substrate, the area of thermal insulation layer is less than the upper surface of substrate;
(B) form a first metal layer on thermal insulation layer, and the two ends of the first metal layer are to extend thermal insulation layer and be positioned on the substrate;
(C) formation one diffusing buffer layer is positioned in the first metal layer on the part of thermal insulation layer top;
(D) form one second metal level on diffusing buffer layer, the fusing point of second metal level is lower than the fusing point of the first metal layer;
(E) form a protective layer on the upper surface of substrate to cover second metal level and diffusing buffer layer; And
(F) form two end electrodes in the both ends of substrate.
Description of drawings
The present invention is described in detail below in conjunction with drawings and Examples:
Fig. 1 is the cross-sectional schematic of chip fuse in the past;
Fig. 2 is the flow chart of the manufacture method preferred embodiment of chip fuse of the present invention;
Fig. 3 is the vertical view of substrate in the present embodiment;
Fig. 4 is the vertical view that forms thermal insulation layer in the present embodiment in the upper surface of substrate;
Fig. 5 and Fig. 6 are respectively the cutaway views that forms metal film in the present embodiment in upper surface of base plate;
Fig. 7 and Fig. 8 are respectively the vertical view and the cutaway views of first photoresist layer behind exposure imaging in the present embodiment;
Fig. 9 and Figure 10 electroplate vertical view and the cutaway view that forms the first metal layer on exposed metal film in the present embodiment;
Figure 11 is the vertical view that removes in the present embodiment behind first photoresist layer;
Figure 12 is the vertical view behind the etching metal film in the present embodiment;
Figure 13 and Figure 14 are respectively vertical view and the cutaway views behind second photoresist layer of exposure imaging in the present embodiment;
Figure 15 is the cutaway view that forms in the present embodiment behind the diffusing buffer layer and second metal level;
Figure 16 is the cutaway view that removes in the present embodiment behind second photoresist layer;
Figure 17, Figure 18 are respectively vertical view and the cutaway views behind the formation protective layer in the present embodiment;
Figure 19 is the upward view that forms backplate in the present embodiment in the lower surface of substrate;
Figure 20 is the cutaway view after the both ends of the surface of substrate form end electrode in the present embodiment;
Figure 21 is the cutaway view of present embodiment chips fuse; And
Figure 22 is the present embodiment chip fuse and the electric current of chip fuse and the curve chart of fusing time in the past.
Embodiment
For convenience of description, select to illustrate among the embodiment hereinafter, yet have the knack of this operator, can on large substrate, form most the chip fuses that are arranged during actual the manufacturing when knowing to make the one chip fuse.Hereinafter, cooperate Fig. 2 that the flow process of embodiment of the manufacture method of chip fuse of the present invention is described.
At first, in step 201, provide a substrate 21 (as Fig. 3).This substrate 21 is rectangular substrate and its material is aluminium oxide (Al
2O
3).
For the heat of avoiding fuse work to produce scatters and disappears from substrate 21, thereby in step 203,, form a thermal insulation layer 23 in the upper surface of substrate 21 as Fig. 4.Thermal insulation layer 23 also is cuboid and its area upper surface less than substrate 21 in this example.Be arranged at the upper surface of substrate 21 during this thermal insulation layer 23 is put, make substrate 21 upper surfaces around exposing and do not covered by thermal insulation layer 23.These routine thermal insulation layer 23 materials are silicon rubber (Silicon Rubber) and form with printing.
Thereafter begin prepare to form fuse portion, the design of fuse portion forms with plating mode in this example, and needs prior to forming the good conducting surface of a conductive effect on substrate 21 upper surfaces, with as electrode.Therefore, in step 203,, form the metal film of a covered substrate 21 upper surfaces in the thin film deposition mode as Fig. 5 and Fig. 6.Metal film contains one and hinders metal film 241 and in order to adhesion and the diffusion that hinders metal diffusing and be positioned at diffusion and hinder plating nuclear species metal film 242 on the metal film 241 in this example, and the material of diffusion obstruction metal film 241 is titanium-tungsten (TiW).In order to make electroplating effect good, the material of electroplating nuclear species metal film 242 is preferably identical with plated metal, so plating nuclear species metal film 242 materials of this example are copper.
Secondly, be the pattern of definition fuse portion, in step 204, cooperate Fig. 7 and Fig. 8 earlier, form one first photoresist layer 25 prior to substrate 21 upper surfaces coating photoresistance and after exposure, development, electroplate preparation formation fuse portion pattern part in the nuclear species metal film 242 to expose.Specifically, in exposure, when developing, remove a left and right both end sides and a mid portion that is connected between both end sides in first photoresist layer 25, make 25 surplus compartment of terrains of first photoresist layer be positioned at two blocks of the front and back side of substrate 21 upper surfaces, make and prepare that to form the corresponding part metals film in fuse position 24 exposed and be the H font.Have the knack of this operator when knowing that first photoresist layer 25 is that example illustrates with the H font though present embodiment makes, still the shape of first photoresist layer 25 changes with fuse design shape difference, should not be subject to the disclosed content of present embodiment.
Then in step 205, substrate 21 is placed in the electroplating bath beginning electro-coppering.So, as Fig. 9 and Figure 10, the copper metal layer (referring to the first metal layer) 26 of on exposed plating nuclear species metal film 242, growing up.
Secondly, in step 206,, remove first photoresist layer 25 that no longer needs, make that the plating nuclear species metal film 242 that is covered by the photoresistance block originally is exposed as Figure 11.Then, in step 207, as Figure 12, elder generation's etching removes exposed plating nuclear species metal film 242, the parcel plating nuclear species metal film 242 that finger is not covered by the first metal layer 26, thereafter, etching removes the exposed part that diffusion hinders metal film 241 again, makes the part thermal insulation layer 23 that is not covered by the first metal layer 26 exposed with part substrate 21 upper surfaces.
Then, preparation forms another metal level of fuse portion again.In the step 208, as Figure 13 and Figure 14, earlier form one second photoresist layer 27 through exposure imaging, make second photoresist layer 27 cover both end sides and the mid portion and the both end sides joining part of the first metal layer 26, the middle section of putting of the mid portion of the first metal layer 26 is exposed with photoresistance.In addition, have the knack of this operator when knowing, though present embodiment discloses first, second photoresist layer 25,27 for the purpose of illustration and forms with steps such as photoresistance coating, exposure and developments, but have the knack of this operator when knowing, first, second photoresist layer 25,27 can otherwise form, as thick film screen printing etc., should not be subject to this enforcement and disclose.
In order to suppress the improper diffusion under low temperature of second metal level, as Figure 15, present embodiment is prior in the step 209, electroplate on the exposed the first metal layer 26 form a diffusing buffer layer 28 after, again in step 210 electrotinning to form second metal level 29.So, grow up in regular turn on the first metal layer 26 exposed parts diffusing buffer layer 28 and second metal level 29.Therefore, be different from the past, present embodiment is more set up a diffusing buffer layer 28 in 26,29 of first, second metal levels, the probability of improper diffusion when belonging to low temperature with reduction Sillim, and second metal level 29 still can diffuse to the first metal layer 26 through diffusing buffer layer 28 under high temperature, to guarantee the chip fuse operate as normal.The material of diffusing buffer layer 28 can be a kind of in titanium nitride (TiN), titanium-tungsten (TiW), silicon nitride (SiN), aluminium arsenide (AlAs), cadmium sulfide (CdS) and the nickel (Ni).The material of diffusing buffer layer 28 is a nickel in the present embodiment, and the thickness that the thickness that the thickness of the first metal layer 26 is about 10～20 microns (μ m), diffusing buffer layer 28 is about 0.1～3 micron and second metal level 29 is about 0.5～3 micron.Again, the first metal layer 26 materials are copper (fusing point 1064 degree) and second metal level, 29 material tin (fusing point 232 degree) in this example, and the fusing point of the first metal layer 26 very is higher than second metal level 29.
After second metal level 29 forms, in step 211, remove first photoresist layer 27 (as Figure 16).
Then, in step 212,, form the mid portion that protective layer 30 is covered in substrate 21 upper surfaces, only allow the both end sides of copper metal layer 26 partly exposed, to be used for forming termination electrode as Figure 17 and Figure 18.In addition, when forming protective layer 30, but more printed patterns is on protective layer 30 upper surfaces, and pattern can be the symbol " F " of representing the fuse electric current.
Thereafter, because the design of the chip fuse of present embodiment is installed on the electronic installation such as circuit board in surface adhering mode (SMT), therefore earlier in step 213,, form two backplates (Backside Electrode) 22 in the and arranged on left and right sides of the lower surface of substrate 21 as Figure 19.The material of this routine backplate 22 is silver (Ag) or a copper (Cu).Have the knack of this skill person when knowing, but this step 213 execution order design requirement and adjusting for example in advance before thermal insulation layer 23 forms or the like, should not be subject to present embodiment and disclose.In addition, this routine chip fuse also can be designed to inserting mode, and then this step 213 can be omitted.
At last, the both ends in substrate 21 form termination electrode in step 214.Specifically, as Figure 20, on the left and right side of substrate 21, form end electrode 31 with sputtering way earlier.This routine end electrode 31 is to have a nichrome film and a monel film from inside to outside.Then, as Figure 21, form termination electrode 32 in the barrel plating mode.Two end electrodes 32 is to insert and put the both ends of substrate 21 respectively in it.This routine termination electrode 32 has a bronze medal metal film, a nickel metal film and a tin metal film from inside to outside.
Therefore, be different from the past that fuse portion constitutes with two metal levels in the chip fuse, this enforcement chip fuse is set up diffusing buffer layer 28 in 26,29 of first and second metal levels, can reduce by second metal level 29 when low-temperature working metal diffusing to the speed and the quantity of the first metal layer 26, as Figure 22, present embodiment chip fuse fusing time and the maximum current that can bear also can obviously increase, and then reach the effect that situation is burnt in effective prolongation life of product and effective improvement easily.
Described before combining, the fuse portion of chip fuse of the present invention sets up diffusing buffer layer 28 and makes three-decker in first, second metal level 26,29, improper diffusion with effective inhibition second metal level 29, reach effective prolongation life of product, increase the effect that to bear the magnitude of current and improve the situation of burning easily, and then avoid frequency domain changing the inconvenience of fuse.
Claims (15)
1. the manufacture method of a chip fuse is characterized in that it comprises:
(A) form a thermal insulation layer in the upper surface of a substrate, the area of thermal insulation layer is less than the upper surface of substrate;
(B) form a first metal layer on thermal insulation layer, and the two ends of the first metal layer are to extend thermal insulation layer and be positioned on the substrate;
(C) formation one diffusing buffer layer is positioned in the first metal layer on the part of thermal insulation layer top;
(D) form one second metal level on diffusing buffer layer, the fusing point of second metal level is lower than the fusing point of the first metal layer;
(E) form a protective layer on the upper surface of substrate to cover second metal level and diffusing buffer layer; And
(F) form two end electrodes in the both ends of substrate.
2. manufacture method as claimed in claim 1 is characterized in that:
The first metal layer material is that the copper and the second metal level material are tin.
3. manufacture method as claimed in claim 1 is characterized in that:
The material of diffusing buffer layer is to select for use by titanium nitride, titanium-tungsten, silicon nitride, aluminium arsenide, cadmium sulfide and nickel one of to be constituted in the group.
4. manufacture method as claimed in claim 1 is characterized in that:
The material of thermal insulation layer is a silicon rubber.
5. manufacture method as claimed in claim 1 is characterized in that step (B) has following substep:
(B-1) form the upper surface of a metal film with thin film deposition in substrate;
(B-2) form one first photoresist layer on metal film, expose so that the both end sides of metal film and is put the mid portion that is connected both end sides middlely;
(B-3) electroplating substrate is with the first metal layer on the exposed part that is formed at metal film; And
(B-4) remove first photoresist layer.
6. manufacture method as claimed in claim 5 is characterized in that:
The diffusion obstruction metal film and that metal film in the substep (B-1) contains an adhesion and obstruction metal diffusing is positioned at the plating nuclear species metal film that spreads on the obstruction metal film, and diffusion obstruction metal film material is a titanium-tungsten.
7. manufacture method as claimed in claim 5 is characterized in that:
Step (B) also has a substep (B-5) and removes the exposed part that metal film is not covered by the first metal layer.
8. manufacture method as claimed in claim 7 is characterized in that step (C) has following substep:
(C-1) form one second photoresist layer, to form two blocks of the both end sides that covers the first metal layer; And
(C-2) electroplating substrate is with the diffusing buffer layer on the mid portion that is formed at the first metal layer.
9. manufacture method as claimed in claim 8 is characterized in that step (D) has following substep:
(D-1) electroplating substrate is to be formed at second metal level on the diffusing buffer layer; And
(D-2) remove second photoresist layer.
10. manufacture method as claimed in claim 1 is characterized in that this method also comprises:
One step (G) is to form two backplates in the both sides of the lower surface of substrate.
11. a chip fuse is characterized in that comprising:
One substrate;
One thermal insulation layer be the upper surface that is positioned at substrate, and the thermal insulation layer area is less than the upper surface of substrate;
One fuse portion, its two ends are to extend thermal insulation layer and be positioned on the substrate, fuse portion has one and is positioned at the first metal layer, on the thermal insulation layer and is positioned at diffusing buffer layer and on the first metal layer and is positioned at second metal level on the diffusing buffer layer;
One protective layer is to cover the part on thermal insulation layer in the fuse portion at least; And
Two end electrodes is the both ends that are formed at substrate respectively.
12. chip fuse as claimed in claim 11 is characterized in that:
The first metal layer material is that the copper and the second metal level material are tin.
13. chip fuse as claimed in claim 11 is characterized in that:
The material of diffusing buffer layer is to select for use by titanium nitride, titanium-tungsten, silicon nitride, aluminium arsenide, cadmium sulfide and nickel one of to be constituted in the group.
14. chip fuse as claimed in claim 11 is characterized in that:
The thermal insulation layer material is a silicon rubber.
15. chip fuse as claimed in claim 11 is characterized in that also comprising:
Two lay respectively at the backplate of the both sides of base lower surface.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100642644A CN100390934C (en) | 2005-04-12 | 2005-04-12 | Method for producing chip fuse and products thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100642644A CN100390934C (en) | 2005-04-12 | 2005-04-12 | Method for producing chip fuse and products thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1848378A CN1848378A (en) | 2006-10-18 |
| CN100390934C true CN100390934C (en) | 2008-05-28 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100642644A Active CN100390934C (en) | 2005-04-12 | 2005-04-12 | Method for producing chip fuse and products thereof |
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| CN (1) | CN100390934C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101232003B (en) * | 2007-01-24 | 2010-06-16 | 乾坤科技股份有限公司 | Chip safety wire and method for making the same |
| WO2010048782A1 (en) * | 2008-10-28 | 2010-05-06 | 南京萨特科技发展有限公司 | Chip type fuse and its manufacturing method |
Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5452842A (en) * | 1993-05-03 | 1995-09-26 | Motorola, Inc. | Tin-zinc solder connection to a printed circuit board or the like |
| US5552757A (en) * | 1994-05-27 | 1996-09-03 | Littelfuse, Inc. | Surface-mounted fuse device |
| JP2001052593A (en) * | 1999-08-09 | 2001-02-23 | Daito Tsushinki Kk | Fuse and its manufacture |
| CN1549291A (en) * | 2003-05-16 | 2004-11-24 | 相互股份有限公司 | Self-healing fuse and producing method thereof |
-
2005
- 2005-04-12 CN CNB2005100642644A patent/CN100390934C/en active Active
Patent Citations (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5452842A (en) * | 1993-05-03 | 1995-09-26 | Motorola, Inc. | Tin-zinc solder connection to a printed circuit board or the like |
| US5552757A (en) * | 1994-05-27 | 1996-09-03 | Littelfuse, Inc. | Surface-mounted fuse device |
| JP2001052593A (en) * | 1999-08-09 | 2001-02-23 | Daito Tsushinki Kk | Fuse and its manufacture |
| CN1549291A (en) * | 2003-05-16 | 2004-11-24 | 相互股份有限公司 | Self-healing fuse and producing method thereof |
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| Publication number | Publication date |
|---|---|
| CN1848378A (en) | 2006-10-18 |
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