CN100391002C - Single programmable read-only memory and method of manufacture - Google Patents
Single programmable read-only memory and method of manufacture Download PDFInfo
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- CN100391002C CN100391002C CNB2005100593629A CN200510059362A CN100391002C CN 100391002 C CN100391002 C CN 100391002C CN B2005100593629 A CNB2005100593629 A CN B2005100593629A CN 200510059362 A CN200510059362 A CN 200510059362A CN 100391002 C CN100391002 C CN 100391002C
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Abstract
The present invention relates to a single programmable read-only memory and a manufacture method thereof. The single programmable read-only memory at least comprises a P-type semiconductor base, an N-type doping region, a P-type first doping layer, a P-type second doping layer, a conductive layer, an N-type first doping layer and an inverse fuse layer, wherein the N-type doping region is arranged in the P-type semiconductor base; the P-type first doping layer is arranged in the P-type semiconductor base and is positioned on the N-type doping region; the P-type second doping layer has a high doping density and is positioned between the N-type doping region and the P-type first doping layer, and the P-type second doping layer forms a strip shape and is used as a bit line; the conductive layer is arranged on the P-type semiconductor base, and the conductive layer forms a strip shape and is vertically staggered with the P-type first doping layer; the N-type first doping layer is arranged in the P-type semiconductor base and is positioned between the conductive layer and the P-type first doping layer as a selective diode element; the inverse fuse layer is arranged between the conductive layer and the N-type first doping layer, and the inverse fuse layer of voltage collapse or not is used as a state to distinguish 0 and 1.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly relevant for a kind of single programmable read-only memory and manufacture method thereof.
Background technology
When the function of computer microprocessor (Microprocessor) is more and more stronger, when program that software carried out and computing were more and more huger, the demand of memory was also just more and more higher.Therefore, how to make the big and cheap memory of capacity, just become semiconductor maker's a big problem to satisfy this demand.According to the difference of read/write function, memory can simply be divided into two classes: read-only memory (ReadOnly Memory; ROM) and random access memory.
Because read-only memory has non-volatile (Non-Volatile) characteristic of not losing wherein stored data because of power interruptions, therefore all must possess this type of memory in many electric equipment products, the normal running when starting shooting to keep electric equipment products.
According to the mode that data deposits in, read-only memory generally can be subdivided into mask-type ROM (Mask ROM) but, single program read-only memory (One Time Programmable ROM; OPTROM) but, the program read-only memory of can erasing (Erasable Programmable ROM; EPROM) but, electronic type program read-only memory (the Electrically Erasable ProgrammableROM that can erase; EEPROM) etc.Wherein, but the single program read-only memory also can write data by the user according to the environment of memory configurations, so it is more convenient than mask-type ROM owing to can just write data after memory leaves factory.
But the known read-only mnemon of a kind of single program is made of a diode and an antifuse layer.But whether the read-only mnemon of this kind single program collapses by antifuse layer, has judged whether be connected with the PN diode between word line and bit line, reach store the numerical digit information order it.
For instance, U.S. Pat 6,185, but No. 122 cases disclose a kind of single program read-only memory of vertical stacking, it is the conductor that alternately piles up many strips on substrate, is provided with a diode and an antifuse layer (Antifuse Layer) then respectively between neighbouring conductor.Diode and antifuse layer promptly constitute a mnemon.Yet in this patent, the PN diode is made of P type doped polysilicon layer and N type doped polysilicon layer.Because polysilicon contains many crystal grain not of uniform size (grain), and the existence of grain boundary is arranged again, so PN connects face characteristic and inconsistent, leakage path is also many simultaneously.Therefore be the PN diode applications of polysilicon on memory cell the time with material, and cause each mnemon characteristic inconsistent easily, and under reverse bias, be easy to generate electric leakage.
Summary of the invention
In view of this, purpose of the present invention is providing a kind of single programmable read-only memory and manufacture method thereof exactly, and is inconsistent to improve the mnemon characteristic, and the problem of leaking electricity easily under reverse bias.
A further object of the present invention provides a kind of single programmable read-only memory and manufacture method thereof, can simplify technology, improves element aggregation degree and reduce manufacturing cost.
The present invention proposes a kind of single programmable read-only memory, comprises second doped layer, the conductive layer of first doped layer, first conductivity type of the first conductive-type semiconductor substrate, the second conductivity type doped region, first conductivity type, first doped layer and the antifuse layer of second conductivity type at least.Wherein, the second conductivity type doped region is arranged in the first conductive-type semiconductor substrate.First doped layer of first conductivity type is arranged in the first conductive-type semiconductor substrate, and is positioned on the second conductivity type doped region.Second doped layer of first conductivity type is arranged between first doped layer of the second conductivity type doped region and first conductivity type, and second doped layer of first conductivity type into strips, is as bit line.Conductive layer is arranged on the first conductive-type semiconductor substrate, this conductive layer into strips and with first conductivity type, the first doped layer vertical interlaced.Second conductivity type, first doped layer is arranged in the first conductive-type semiconductor substrate, and between first doped layer of the conductive layer and first conductivity type.Antifuse layer is arranged between first doped layer of the conductive layer and second conductivity type.
In above-mentioned single programmable read-only memory, first conductivity type is the P type, and then second conductivity type is the N type; First conductivity type is the N type, and then second conductivity type is the P type.And, have a wedge angle at second conductivity type, the first doped layer top.
In addition, in above-mentioned single programmable read-only memory, have more and have the interbedded insulating layer that is arranged on the Semiconductor substrate.This interlayer insulating film has irrigation canals and ditches that are positioned at second conductivity type, second doped layer top, and conductive layer is arranged in the irrigation canals and ditches, and antifuse layer is arranged between interlayer insulating film and the conductive layer.
In above-mentioned single programmable read-only memory, because PN (or NP) diode is formed in the Semiconductor substrate with one deck, its material can be on sign an undertaking crystal silicon Semiconductor substrate, the insulating barrier of monocrystalline silicon Semiconductor substrate, polysilicon crystal of growth silicon (SOI) Semiconductor substrate, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.Therefore, utilize this kind PN (or NP) but to connect the characteristic of the read-only mnemon of single program of face also more consistent, and electrical leakage quantity also can reduce, and can increase element efficiency.
And because the first doped layer Cheng Tazhuan of second conductivity type, breakdown region that therefore can the volitional check antifuse layer is to present good logic state.And, the surface elevation of first doped layer of second conductivity type and be formed with wedge angle, and can utilize the principle of point discharge, make charge concentration at sharp corner, antifuse layer is collapsed easily, and can reduce operating voltage.
In addition, single programmable read-only memory of the present invention, by simple in structure, mnemon is of a size of 4F
2Therefore, can improve the collection base degree of memory component.And, by the material that changes antifuse layer, breakdown voltage and element efficiency that can control storage.
The present invention proposes a kind of manufacture method of single programmable read-only memory, the first conductive-type semiconductor substrate at first is provided, in the first conductive-type semiconductor substrate, down is formed with first doped layer of second conductivity type, first doped layer of first conductivity type, second doped layer and the second conductivity type doped region of first conductivity type in regular turn by the surface.Then, the patterning first conductivity type substrate, be with formation first conductivity type of strip second doped layer and first doped layer that is block first conductivity type, be first doped layer of block second conductivity type.Then, carry out etch process, make the first doped layer top of second conductivity type that is block have a wedge angle, afterwards and on the first conductivity type substrate, finish the deposition or the plated film of antifuse layer.Then, on antifuse layer, plate an etch stop layer, and after forming interlayer insulating film on the etch stop layer, the patterning interlayer insulating film to be forming irrigation canals and ditches that expose etch stop layer, and irrigation canals and ditches and be the first doped layer vertical interlaced of second conductivity type of strip.Afterwards, remove the etch stop layer that irrigation canals and ditches expose, and in irrigation canals and ditches, form a conductive layer.
In the manufacture method of above-mentioned single programmable read-only memory, the patterning first conductive-type semiconductor substrate, second doped layer and first doped layer that is block first conductivity type that are first conductivity type of strip with formation, the step of first doped layer that is block second conductivity type is as follows, at first carry out first Patternized technique, remove first doped layer of part second conductivity type, first doped layer of first conductivity type, second doped layer of first conductivity type, exposing the second conductivity type doped region, and form first doped layer of second conductivity type that is strip, first doped layer that is first conductivity type of strip, second doped layer that is first conductivity type of strip.Then, carry out second Patternized technique, remove first doped layer of part second conductivity type, first doped layer of first conductivity type, with formation be block second conductivity type first doped layer, be first doped layer of block first conductivity type.
In the manufacture method of single programmable read-only memory of the present invention, in Semiconductor substrate, form NPN (or PNP) structure of patterning, use twice photoengraving carving technology defining bit line and silicon turricula then, and form PN (or NP) diode and the bit line of isolating.In the Semiconductor substrate that is formed at PN (or NP) diode with one deck, its material can be monocrystalline silicon Semiconductor substrate, the crystal silicon Semiconductor substrate of signing an undertaking of polysilicon crystal, the soi semiconductor substrate of growth, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.And by simple at memory unit structure, needed light shield number is less, so the cost of memory can reduce.
And, by the first doped layer Cheng Tazhuan, therefore can limit the breakdown region of antifuse layer, to present good logic state at second conductivity type.In addition, utilize etch process, make the surface of first doped layer of second conductivity type be formed with wedge angle, and can utilize the principle of point discharge, make charge concentration, antifuse layer is collapsed easily, and can reduce operating voltage at sharp corner.
In addition, in the manufacture method of single programmable read-only memory of the present invention, because this uses the notion of aiming at voluntarily, and between word line and bit line, form memory unit structure, needed light shield number is few, and adopt that to aim at the mnemon size that notion makes voluntarily less, can improve the aggregation degree of memory component.
In addition, by the material that changes antifuse layer, breakdown voltage and element efficiency that can control storage.And, after being separated out PN (or NP) diode structure, just form antifuse layer, so the material of antifuse layer is easier to change.In addition, be formed with etch stop layer on antifuse layer, this etch stop layer has different etching selectivities with antifuse layer, therefore can keep the thickness of antifuse layer.
In addition, the breakdown voltage of mnemon can be by the thickness decision of antifuse layer, and the thickness of antifuse layer is by the long-pending technology decision in Shen, be not to decide by etch process and chemical mechanical milling tech, therefore that is process margin (Process window) can not be subjected to the influence of etch process and chemical mechanical milling tech, has bigger process margin.
The present invention proposes the manufacture method of another kind of single programmable read-only memory, the first conductive-type semiconductor substrate at first is provided, in the first conductive-type semiconductor substrate, down is formed with first doped layer of second conductivity type, first doped layer of first conductivity type, second doped layer and the second conductivity type doped region of first conductivity type in regular turn by the surface.Then, the patterning first conductive-type semiconductor substrate, be second doped layer, first doped layer that is block first conductivity type and first doped layer that is block second conductivity type of first conductivity type of strip with formation, and on the first conductive-type semiconductor substrate, form interlayer insulating film.Then, the patterning interlayer insulating film is with irrigation canals and ditches of first doped layer that form to expose second conductivity type, and irrigation canals and ditches and second conductivity type, the first doped layer vertical interlaced that is strip, and at irrigation canals and ditches bottom and sidewall formation antifuse layer.Afterwards, in irrigation canals and ditches, form conductive layer.
In the manufacture method of above-mentioned single programmable read-only memory, the patterning first conductive-type semiconductor substrate, second doped layer and first doped layer that is block first conductivity type that are first conductivity type of strip with formation, the step of first doped layer that is block second conductivity type is as follows, at first carry out first Patternized technique, remove first doped layer of part second conductivity type, first doped layer of first conductivity type, second doped layer of first conductivity type, exposing the second conductivity type doped region, and form first doped layer of second conductivity type that is strip, first doped layer that is first conductivity type of strip, second doped layer that is first conductivity type of strip.Then, carry out second Patternized technique, remove first doped layer of part second conductivity type, first doped layer of first conductivity type, with formation be block second conductivity type first doped layer, be first doped layer of block first conductivity type.
In the manufacture method of above-mentioned single programmable read-only memory, after the step of the patterning first conductivity type substrate with on the first conductivity type substrate, form interlayer insulating film before, more comprise and carry out etch process, make the first doped layer top of second conductivity type that is block have a wedge angle.
In the manufacture method of single programmable read-only memory of the present invention, in substrate, form NPN (or PNP) structure of patterning, use twice photoengraving carving technology defining bit line and silicon turricula then, and form monocrystalline silicon PN (or NP) diode and the bit line of isolating.Because PN (or NP) diode is formed in the Semiconductor substrate with one deck, its material can be monocrystalline silicon Semiconductor substrate, the crystal silicon Semiconductor substrate of signing an undertaking of polysilicon crystal, the soi semiconductor substrate of growth, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.And because memory unit structure is simple, needed light shield number is less, so the cost of memory can reduce.
In addition, define wordline patterns (irrigation canals and ditches) after, just form antifuse layer, so the material of antifuse layer is easier to change, and thickness can't be subjected to the etch process influence.And, by the material that changes antifuse layer, breakdown voltage and element efficiency that can control storage.
In addition, the breakdown voltage of mnemon can be by the thickness decision of antifuse layer, and the thickness of antifuse layer is by the long-pending technology decision in Shen, be not to decide by etch process and chemical mechanical milling tech, therefore that is process margin (Process window) can not be subjected to the influence of etch process and chemical mechanical milling tech, has bigger process margin.
For above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, a preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below
Description of drawings
Figure 1A is the perspective view of the single programmable read-only memory of first embodiment of the invention.
Figure 1B and Fig. 1 C are to be the profile of A-A ' line among Figure 1A and the profile of B-B ' line respectively.
Fig. 1 D is the schematic equivalent circuit of single programmable read-only memory of the present invention.
Fig. 2 A to Fig. 9 A, Fig. 2 B to Fig. 9 B are to be the process section of A-A ' line among Figure 1A and the process section of B-B ' line respectively.
Figure 10 A is the perspective view of the single programmable read-only memory of second embodiment of the invention.
Figure 10 B and Figure 10 C are to be the profile of A-A ' line among Figure 10 A and the profile of B-B ' line respectively.
Figure 11 A to Figure 12 A, Figure 11 B to Figure 12 B are to be the process section of A-A ' line among Figure 10 A and the process section of B-B ' line respectively.
Figure 13 A is the perspective view of the single programmable read-only memory of third embodiment of the invention.
Figure 13 B and Figure 13 C are to be the profile of A-A ' line among Figure 13 A and the profile of B-B ' line respectively.
Figure 14 A to Figure 16 A, Figure 14 B to Figure 16 B are to be the process section of A-A ' line among Figure 13 A and the process section of B-B ' line respectively.
100: Semiconductor substrate 102:N type doped region
103:P type doped region 104:P type doped layer
104a:P
+ Doped region 104b:P doped region
105:N type doped region 106,106a:N type doped layer
107,111,115: photoresist layer 108,108a: antifuse layer
109,113,118: irrigation canals and ditches 110: etch stop layer
112: interlayer insulating film 112a: the boron-phosphorosilicate glass layer
112b: silicon oxide layer 114: conductive layer
116: wedge angle 120: protective layer
Embodiment
First embodiment
Figure 1A is the perspective view of the single programmable read-only memory of first embodiment of the invention.Figure 1B and Fig. 1 C are to be the profile of A-A ' line among Figure 1A and the profile of B-B ' line respectively.Fig. 1 D is the schematic equivalent circuit of single programmable read-only memory of the present invention.
See also Figure 1A to Fig. 1 C, single programmable read-only memory of the present invention is made of P type semiconductor substrate 100, N type doped region 102, P type doped layer 104, N type doped layer 106, antifuse layer 108, etch stop layer 110, interlayer insulating film 112, conductive layer 114.
N type doped region 102 is arranged in the P type semiconductor substrate 100.P type doped layer 104 is arranged in the P type semiconductor substrate 100, and is positioned on the N type doped region 102, and this P type doped layer 104 is into strips.And, for example be by P in the P type doped layer 104
+ Doped region 104a and P doped region 104b constitute.P
+The impurity concentration of doped region 104a is big than P doped region 104b, and P
+It is also dark than P doped region 104b that the impurity of doped region 104a injects the degree of depth.P doped region 104b is the p type island region as diode, P
+ Doped region 104a is as bit line.
N type doped layer 106 for example is to be arranged in the P type semiconductor substrate 100, and between conductive layer 114 and P type doped layer 104.N type doped layer 106 for example is into tower shape (Tower Shape), and its surface elevation and be formed with a wedge angle 116.And the P doped region 104b of N type doped layer 106 and P type doped layer 104 constitutes the PN diode.Owing to 106 one-tenth tower shapes of N type doped layer, therefore can limit the breakdown region of antifuse layer 108, to present good logic state.And, the surface elevation of N type doped layer 106 and be formed with wedge angle 116, and can utilize the principle of point discharge, make charge concentration at wedge angle 116 places, antifuse layer 108 is collapsed easily, and can reduce operating voltage.
In above-mentioned single programmable read-only memory, because the PN diode is formed in the Semiconductor substrate 100, because PN (or NP) diode is formed in the Semiconductor substrate with one deck, its material can be monocrystalline silicon Semiconductor substrate, the crystal silicon Semiconductor substrate of signing an undertaking of polysilicon crystal, the soi semiconductor substrate of growth, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.Therefore, but it is also more consistent to utilize this kind PN to connect the characteristic of the read-only mnemon of single program of face, and electrical leakage quantity also can reduce, and can increase element efficiency.
And, owing to 106 one-tenth tower shapes of N type doped layer, therefore can limit the breakdown region of antifuse layer 108, to present good logic state.And, the surface elevation of N type doped layer 106 and be formed with wedge angle 116, and can utilize the principle of point discharge, make charge concentration at wedge angle 116 places, antifuse layer 108 is collapsed easily, and can reduce operating voltage.
In addition, single programmable read-only memory of the present invention, because simple in structure, mnemon is of a size of 4F
2Therefore, can improve the collection base degree of memory component.And, by the material that changes antifuse layer 108, breakdown voltage and element efficiency that can control storage.
In addition, in the above-mentioned single programmable read-only memory, be to be that example explains in P type substrate, to form the NPN structure, certain single programmable read-only memory of the present invention also can form the positive-negative-positive structure in N type substrate.
Then, seeing also Fig. 1 D is the schematic equivalent circuit of single programmable read-only memory of the present invention, and the method for operation of single programmable read-only memory is described.
Single programmable read-only memory of the present invention is to be that example explains with 3 * 3 mnemons.Shown in Fig. 1 D, three parallel word line WL1～WL3 stride across three parallel bit line BL1～BL3.And, be formed with mnemon Q1～Q9 at word line WL1～WL3 and bit line BL1～BL3 staggered place respectively.Each mnemon is made of a PN diode and a resistance.
In following explanation, be with sequencing or to read mnemon Q5 be that example explains.A kind of method for programming of single programmable read-only memory of the present invention when carrying out sequencing, applies bias voltage less than 0 at selected word line WL2, for example is the bias voltage less than-5 volts, and non-selected word line WL1, WL3 float; Selected bit line BL2 applies the bias voltage greater than 0, for example is the bias voltage greater than 5 volts, and non-selected bit line BL1, BL3 float.So selected mnemon Q5 produces collapse, and is defined as numerical digit information " 0 "; Non-selected mnemon Q1～Q4, Q6～Q9 do not produce collapse, and is defined as numerical digit information " 1 ".
Another method for programming of single programmable read-only memory of the present invention then is to apply bias voltage less than 0 in selected word line WL2, for example is the bias voltage less than-5 volts, non-selected word line WL1, WL3 ground connection; Selected bit line BL2 applies the bias voltage greater than 0, for example is the bias voltage greater than 5 volts, and non-selected bit line BL1, BL3 apply little back bias voltage, for example are-2 volts bias voltages.So selected mnemon Q5 produces collapse, and is defined as the numerical digit information " 0 "; Non-selected mnemon Q1～Q4, Q6～Q9 do not produce collapse, and is defined as numerical digit information " 1 ".
Another method for programming of single programmable read-only memory of the present invention then is that non-selected word line WL1, WL3 float in selected word line WL2 ground connection; Selected bit line BL2 applies the bias voltage greater than 0, for example is the bias voltage greater than 10 volts, non-selected bit line BL1, BL3 ground connection.So selected mnemon Q5 produces collapse, and is defined as numerical digit information " 0 "; Non-selected mnemon Q1～Q4, Q6～Q9 do not produce collapse, and is defined as numerical digit information " 1 ".
The read method of single programmable read-only memory of the present invention then is that non-selected word line WL1, WL3 float in selected word line WL2 ground connection; Selected bit line BL2 applies, and for example is 3.3 volts bias voltage, non-selected bit line BL1, BL3 ground connection.Still is " 1 " with judgement mnemon for " 0 " by the current sensor Isens that reads out.If mnemon is " 0 " state, then mnemon collapse, current sensor Isens is bigger; If mnemon is one state, then mnemon is not collapsed, and current sensor Isens is less.
The manufacture method of single programmable read-only memory of the present invention then, is described.Fig. 2 A to Fig. 9 A, Fig. 2 B to Fig. 9 B are to be the process section of A-A ' line among Figure 1A and the process section of B-B ' line respectively.
Seeing also Fig. 2 A and Fig. 2 B, semi-conductive substrate 100 is provided, for example is the P type semiconductor substrate.In this Semiconductor substrate 100, form a N type doped region 102 then.The formation method of this N type doped region 102 for example is an ion implantation, and the impurity of injection comprises arsenic, phosphorus or nitrogen, and implantation dosage for example is 5 * 10
17/ cm
3, injecting the degree of depth for example is 2500 dusts.
Then, on N type doped region 102, form P type doped region 103.And, for example be by P in the P type doped region 103
+ Doped region 104a and P doped region 104b constitute.P
+The impurity concentration of doped region 104a is big than P doped region 104b, and P
+It is also dark than P doped region 104b that the impurity of doped region 104a injects the degree of depth.P doped region 104b is the p type island region as diode, P
+Doped region 104a is as bit line.This P
+The formation method of doped region 104a and P doped region 104b for example is an ion implantation, and the impurity of injection comprises boron or boron difluoride, and implantation dosage for example is respectively 7 * 10
19/ cm
3And 5 * 10
18/ cm
3
Then, on P type doped region 103, form N type doped region 105.The formation method of this N type doped region 105 for example is an ion implantation, and the impurity of injection comprises arsenic, phosphorus or nitrogen, and implantation dosage for example is 5 * 10
18/ cm
3, injecting the degree of depth for example is 500 dusts.
Afterwards, carry out a tempering process, make the impurity of the injection Semiconductor substrate 100 that becomes, with activation N type doped region 105, P type doped region 103 (P doped region 104b and P
+Doped region 104a) with N type doped region 102.The temperature of this tempering process for example is 1000 ℃.
See also Fig. 3 A and Fig. 3 B, form the photoresist layer 107 of one deck patterning on Semiconductor substrate 100, the photoresist layer 107 of this patterning for example is to be the strip layout, extends toward Y direction (shown in Figure 1A).Then, be mask with this patterning photoresist layer 107, carry out etch process, remove part semiconductor substrate 100 up to the surface that exposes N type doped region 102 at least, and form irrigation canals and ditches 109.Behind etch process, P type doped region 103 is separated into strip and forms P type doped layer 104 by irrigation canals and ditches 109.In the present embodiment, etch depth for example is the 2000 Izod right sides, and forms N type doped region 102, the P doped region 104b of thickness 500 dusts, the P of thickness 500 dusts by thickness 500 dusts in Semiconductor substrate 100
+The stacked structure that the N type doped region 105 of doped region 104a and thickness 500 dusts constitutes.Employed etching gas for example is the etching gas of chloride, hydrogen chloride or bromine in this etch process.
See also Fig. 4 A and Fig. 4 B, remove patterning photoresist layer 107 after, carry out another etch process, remove part N type doped region 105, and make the surface of N type doped region 105 have a wedge angle 116.Employed etching gas for example is the etching gas of chloride, hydrogen chloride or bromine in this etch process.Can make N type doped region 105 have wedge angle 116 by flow, ratio or the pressure of control etching gas.
See also Fig. 5 A and Fig. 5 B, form the photoresist layer 111 of another layer patternization on Semiconductor substrate 100, the photoresist layer 111 of this patterning for example is to be the strip layout, extends toward directions X (shown in Figure 1A).Then, be mask with this patterning photoresist layer 111, carry out etch process, remove part semiconductor substrate 100 up to the surface that exposes P type doped layer 104 at least, and form irrigation canals and ditches 113.Behind etch process, N type doped region 105 is separated into the block N type doped layer 106 that is isolated from each other by irrigation canals and ditches 109 and irrigation canals and ditches 111.In the present embodiment, etch depth for example is the 750 Izod right sides.Employed etching gas for example is the etching gas of chloride, hydrogen chloride or bromine in this etch process.
See also Fig. 6 A and Fig. 6 B, remove patterning photoresist layer 111 after, on Semiconductor substrate 100, form one deck antifuse layer 108, one deck etch stop layer 110 and interlayer insulating film 112 in regular turn.The formation method of antifuse layer 108 for example is the long-pending method in chemical gaseous phase Shen.The material of this antifuse layer 108 for example is a silica, and its thickness for example is 100 dusts.Certainly, the material of antifuse layer 108 also can be high-k (dielectric constant is greater than a 4) material, comprises silicon nitride, silicon oxynitride, aluminium oxide or hafnium oxide.The formation method of etch stop layer 110 for example is the long-pending method in chemical gaseous phase Shen.The material of this etch stop layer 110 comprises with the material of antifuse layer 108 having different etching selectivity persons.The material of etch stop layer 110 for example is a silicon nitride, and its thickness for example is 100 dusts.Interlayer insulating film 112 is made of one deck boron-phosphorosilicate glass layer 112a and one deck silicon oxide layer 112b.Wherein the thickness of boron-phosphorosilicate glass layer 112a for example is 2000 dusts; The thickness of silicon oxide layer 112b for example is 2000 dusts.The formation method of interlayer insulating film 112 for example is after for example being one deck boron-phosphorosilicate glass material layer of 4000 dusts with chemical gaseous phase Shen long-pending method formation thickness earlier, carry out a flatening process, remove the boron-phosphorosilicate glass material layer of 2000 dusts, and form thickness 2000 dusts and have the boron-phosphorosilicate glass layer 112a of flat surfaces, and then utilize the electricity slurry to strengthen the long-pending method in chemical gaseous phase Shen, and be reacting gas source with the adjacent esters of silicon acis of tetraethyl (tetra-ethyl-ortho-silicate), the silicon oxide layer 112b of formation thickness 200 dusts on boron-phosphorosilicate glass layer 112a.The method that removes planarization boron-phosphorosilicate glass material layer for example is a chemical mechanical milling method.Certainly, interlayer insulating film 112 also can be a single layer structure, and its material also can be other insulating material that are used for semiconductor substrate processing.
See also Fig. 7 A and Fig. 7 B, form one deck patterning photoresist layer 115 on interlayer insulating film 112, the photoresist layer 115 of this patterning for example is to be the strip layout, extends toward directions X (shown in Figure 1A).Then, be mask with this patterning photoresist layer 115, carry out etch process, remove part interlayer insulating film 112 to form irrigation canals and ditches 118.Wherein, irrigation canals and ditches 118 are positioned at N type doped layer 106 tops.In this etch process, because etch stop layer 110 has different etching selectivities with interlayer insulating film 112, so the etching meeting stops at etch stop layer 110.
Seeing also Fig. 8 A and Fig. 8 B, is mask with patterning photoresist layer 115, removes 118 exposed portions etch stop layers 110 of irrigation canals and ditches, up to exposing antifuse layer 108.The method that removes partially-etched stop layer 110 for example is a wet etching, when the material of etch stop layer 110 is silicon nitride, is as etching solution with hot phosphoric acid.Because etch stop layer 110 has different etching selectivities with antifuse layer 108, so the thickness of antifuse layer 108 can be because of etching change too greatly, so the thickness of antifuse layer 108 can obtain good control.When removing partially-etched stop layer 110, also there is a spot of interlayer insulating film 112 to be removed, and makes irrigation canals and ditches 118 become big.And, in this etch process, removing etch stop layer 110 drift angle of antifuse layer 108 is come out on every side fully, the thickness that facilitates the use antifuse layer 108 is controlled breakdown voltage.Remove patterning photoresist layer 115 afterwards.
See also Fig. 9 A and Fig. 9 B, in irrigation canals and ditches 118, form conductive layer 114.The material of this conductive layer comprises doped semiconductor, doped polycrystalline silicon, metal material (for example copper, tungsten).The formation method of conductive layer 114 for example is one deck conductor material layer (being not) fill up irrigation canals and ditches 118 prior to forming on the Semiconductor substrate 100, then remove irrigation canals and ditches 118 with conductor material layer and form it.The method that removes irrigation canals and ditches 118 conductor material layer in addition for example is etch-back method or chemical mechanical milling method.Afterwards, on Semiconductor substrate 100, form layer protective layer 120.The material of this protective layer 120 for example is silicon nitride or silica, and its formation method for example is the long-pending method in chemical gaseous phase Shen.Subsequent technique is known by known techniques person, does not repeat them here.
In the manufacture method of single programmable read-only memory of the present invention, in Semiconductor substrate 100, form the NPN structure of patterning, use twice photoengraving carving technology defining bit line and silicon turricula then, and form the PN diode and the bit line of isolation.Because PN (or NP) diode is formed in the Semiconductor substrate with one deck, its material can be monocrystalline silicon, Semiconductor substrate, the crystal silicon Semiconductor substrate of signing an undertaking of polysilicon crystal, the soi semiconductor substrate of growth, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.And because memory unit structure is simple, needed light shield number is less, so the cost of memory can reduce.
And, owing to 106 one-tenth tower shapes of N type doped layer, therefore can limit the breakdown region of antifuse layer 108, to present good logic state.In addition, utilize etch process, make the surface of N type doped layer 106 be formed with wedge angle 116, and can utilize the principle of point discharge, make charge concentration, antifuse layer 108 is collapsed easily, and can reduce operating voltage at wedge angle 116 places.
In addition, in the manufacture method of single programmable read-only memory of the present invention, because this uses the notion of aiming at voluntarily, and between word line and bit line, form memory unit structure, needed light shield number is few, and adopt that to aim at the mnemon size that notion makes voluntarily less, can improve the aggregation degree of memory component.
In addition, by the material that changes antifuse layer 108, breakdown voltage and element efficiency that can control storage.And, after being separated out the PN diode structure, just form antifuse layer 108, so the material of antifuse layer 108 is easier to change.In addition, be formed with etch stop layer 110 on antifuse layer 108, this etch stop layer 110 has different etching selectivities with antifuse layer 108, therefore can keep the thickness of antifuse layer 108.
In addition, the breakdown voltage of mnemon can be by the thickness decision of antifuse layer 108, and the thickness of antifuse layer 108 is by the long-pending technology decision in Shen, be not to decide by etch process and chemical mechanical milling tech, therefore that is process margin (Process window) can not be subjected to the influence of etch process and chemical mechanical milling tech, has bigger process margin.
Second embodiment
Figure 10 A is the perspective view of the single programmable read-only memory of second embodiment of the invention.Figure 10 B and Figure 10 C are to be the profile of A-A ' line among Figure 10 A and the profile of B-B ' line respectively.In Figure 10 A to Figure 10 C, the identical person with Figure 1A to Fig. 1 C of member gives identical label, and omits its explanation.At this difference at the present embodiment and first embodiment.
See also Figure 10 A to Figure 10 C, present embodiment directly is not provided with antifuse layer 108 and etch stop layer 110 (shown in Figure 1A to Fig. 1 C) in regular turn on Semiconductor substrate 100, but interlayer insulating film 112 directly is set on Semiconductor substrate 100.This insulating barrier 112 has irrigation canals and ditches 118 and directly exposes N type doped layer 106.Antifuse layer 118a is arranged in the irrigation canals and ditches 118, and covers irrigation canals and ditches 118 sidewalls and bottom.Conductive layer 114 is arranged at antifuse layer 108a and goes up and fill up irrigation canals and ditches 118.
In above-mentioned single programmable read-only memory, because the PN diode is formed in the Semiconductor substrate 100, because PN (or NP) diode is formed in the Semiconductor substrate with one deck, its material can be monocrystalline silicon Semiconductor substrate, the crystal silicon Semiconductor substrate of signing an undertaking of polysilicon crystal, the soi semiconductor substrate of growth, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.
And, owing to 106 one-tenth tower shapes of N type doped layer, therefore can limit the breakdown region of antifuse layer 108a, to present good logic state.And, the surface elevation of N type doped layer 106 and be formed with wedge angle 116, and can utilize the principle of point discharge, make charge concentration at wedge angle 116 places, antifuse layer 108a is collapsed easily, and can reduce operating voltage.
In addition, present embodiment is compared with first embodiment, because structure is simpler, so technology is easier and can reduce cost.And, by the material that changes antifuse layer 108a, breakdown voltage and element efficiency that can control storage.
In addition, in the above-mentioned single programmable read-only memory, be to be that example explains in the P type semiconductor substrate, to form the NPN structure, certain single programmable read-only memory of the present invention also can form the positive-negative-positive structure in the N type semiconductor substrate.
The manufacture method of the single programmable read-only memory of second embodiment then, is described.Figure 11 A to Figure 12 A, Figure 11 B to Figure 12 B are to be the process section of A-A ' line among Figure 10 A and the process section of B-B ' line respectively.
Figure 11 A and Figure 11 B are connected in Fig. 5 A of first embodiment and the technology after Fig. 5 B.The preceding technology of Figure 11 A and Figure 11 B is identical with the technology of Fig. 2 A of first embodiment and Fig. 2 B to Fig. 5 A and Fig. 5 B, does not repeat them here.
See also Figure 11 A and Figure 11 B, remove patterning photoresist layer 111 after, at Semiconductor substrate 100 last layer interlayer insulating films 112.Interlayer insulating film 112 can be that the double-decker as first embodiment also can be single layer structure or sandwich construction, and its material can be any insulating material that is used for semiconductor technology.Then, form the irrigation canals and ditches 118 that expose N type doped layer 106 in interlayer insulating film 112, these irrigation canals and ditches 118 for example are to be the strip layout, go up at directions X (shown in Figure 10 A) and extend.In this etch process, the wedge angle on N type doped layer 106 surfaces can be because of etch process passivation a little.
See also Figure 12 A and Figure 12 B, after (irrigation canals and ditches 118 bottoms and sidewall) forms antifuse layer 108a in irrigation canals and ditches 118, on Semiconductor substrate 100, form the conductive layer 114 that fills up irrigation canals and ditches 118.The formation method of antifuse layer 108a and conductive layer 114 for example is to amass method after one deck dielectric materials layer of irrigation canals and ditches 118 is not filled up in formation on the Semiconductor substrate 100 with chemical gaseous phase Shen earlier, on Semiconductor substrate 100, form the conductor material layer fill up irrigation canals and ditches 118, then utilize chemical mechanical milling method to remove dielectric materials layer beyond the irrigation canals and ditches 118 and conductor material layer and form it.Subsequent technique is known by known techniques person, does not repeat them here.
In the manufacture method of single programmable read-only memory of the present invention, owing to after defining wordline patterns (irrigation canals and ditches 118), just form antifuse layer 108a, so the material of antifuse layer 108a is easier to change, and thickness can't be subjected to etch process and influences.And, by the material that changes antifuse layer 108a, breakdown voltage and element efficiency that can control storage.
In addition, the breakdown voltage of mnemon can be by the thickness decision of antifuse layer 108a, and the thickness of antifuse layer 108a is by the long-pending technology decision in Shen, be not to decide by etch process and chemical mechanical milling tech, therefore that is process margin (Process window) can not be subjected to the influence of etch process and chemical mechanical milling tech, has bigger process margin.
In addition, present embodiment is compared with first embodiment, owing to do not need to form etch stop layer, so technology is easier and can reduce cost.
The 3rd embodiment
Figure 13 A is the perspective view of the single programmable read-only memory of third embodiment of the invention.Figure 13 B and Figure 13 C are to be the profile of A-A ' line among Figure 13 A and the profile of B-B ' line respectively.In Figure 13 A to Figure 13 C, the identical person with Figure 1A to Fig. 1 C of member gives identical label, and omits its explanation.At this difference at present embodiment and first embodiment, second embodiment.
See also Figure 13 A to Figure 13 C, in the present embodiment, N type doped layer 106a is not formed with wedge angle, and has smooth surface.
In above-mentioned single programmable read-only memory, because the PN diode is formed in the Semiconductor substrate 100, monocrystalline silicon Semiconductor substrate, the sign an undertaking crystal silicon Semiconductor substrate of polysilicon crystal, the soi semiconductor substrate of its material for growing up, therefore it is more consistent that formed PN connects the character of face, and the electric leakage under reverse bias also can reduce.Therefore, but it is also more consistent to utilize this kind PN to connect the characteristic of the read-only mnemon of single program of face, and electrical leakage quantity also can reduce, and can increase element efficiency.
And present embodiment is compared with first embodiment, second embodiment, because structure is simpler, so technology is easier and can reduce cost.And, by the material that changes antifuse layer 108a, breakdown voltage and element efficiency that can control storage.
In addition, in the above-mentioned single programmable read-only memory, be to be that example explains in the P type semiconductor substrate, to form the NPN structure, certain single programmable read-only memory of the present invention also can form the positive-negative-positive structure in the N type semiconductor substrate.
The manufacture method of the single programmable read-only memory of the 3rd embodiment then, is described.Figure 14 A to Figure 16 A, Figure 14 B to Figure 16 B are to be the process section of A-A ' line among Figure 13 A and the process section of B-B ' line respectively.
Figure 14 A and Figure 14 B are connected in Fig. 3 A of first embodiment and the technology after Fig. 3 B.The preceding technology of Figure 14 A and Figure 14 B is identical with the technology of Fig. 2 A of first embodiment and Fig. 2 B to Fig. 3 A and Fig. 3 B, does not repeat them here.
See also Figure 14 A and Figure 14 B, remove patterning photoresist layer 107 after, on Semiconductor substrate 100, form the photoresist layer 111 of another layer patternization, the photoresist layer 111 of this patterning for example is to be the strip layout, goes up at directions X (as shown in FIG. 13A) and extends.Then, be mask with this patterning photoresist layer 111, carry out etch process, remove part semiconductor substrate 100 up to the surface that exposes P type doped layer 104 at least, and form irrigation canals and ditches 113.Behind etch process, N type doped region 105 is separated into the block N type doped layer 106a that is isolated from each other by irrigation canals and ditches 109 and irrigation canals and ditches 111.This N type doped layer 106a has smooth surface.
See also Figure 15 A and Figure 15 B, remove patterning photoresist layer 111 after, at Semiconductor substrate 100 last layer interlayer insulating films 112.Interlayer insulating film 112 can be that the double-decker as first embodiment also can be single layer structure or sandwich construction, and its material can be any insulating material that is used for semiconductor substrate processing.Then, form the irrigation canals and ditches 118 that expose N type doped layer 106a in interlayer insulating film 112, these irrigation canals and ditches 118 for example are to be the strip layout, extend at directions X (as shown in FIG. 13A).
See also Figure 16 A and Figure 16 B, after (irrigation canals and ditches 118 bottoms and sidewall) forms antifuse layer 108a in irrigation canals and ditches 118, on Semiconductor substrate 100, form the conductive layer 114 that fills up irrigation canals and ditches 118.The formation method of antifuse layer 108a and conductive layer 114 for example is to amass method after one deck dielectric materials layer of irrigation canals and ditches 118 is not filled up in formation on the Semiconductor substrate 100 with chemical gaseous phase Shen earlier, on Semiconductor substrate 100, form the conductor material layer fill up irrigation canals and ditches 118, then utilize chemical mechanical milling method to remove dielectric materials layer beyond the irrigation canals and ditches 118 and conductor material layer and form it.Subsequent technique is known by known techniques person, does not repeat them here.
In the manufacture method of single programmable read-only memory of the present invention, in Semiconductor substrate 100, form the NPN structure of patterning, use twice photoengraving carving technology defining bit line and silicon turricula then, and form the PN diode and the bit line of isolation.Because PN (or NP) diode is formed in the Semiconductor substrate with one deck, its material can be monocrystalline silicon Semiconductor substrate, the crystal silicon Semiconductor substrate of signing an undertaking of polysilicon crystal, the soi semiconductor substrate of growth, therefore formed PN (or NP) connects the character of face than U.S. Pat 6,185, No. 122 case unanimities, and the electric leakage under reverse bias is much lower on the order of magnitude compared with polysilicon diode.And because memory unit structure is simple, needed light shield number is less, so the cost of memory can reduce.
And, in the manufacture method of single programmable read-only memory of the present invention, because this uses the notion of aiming at voluntarily, and between word line and bit line, form memory unit structure, needed light shield number is few, and adopt that to aim at the mnemon size that notion makes voluntarily less, can improve the aggregation degree of memory component.
In addition, define wordline patterns (irrigation canals and ditches 118) after, just form antifuse layer 108a, so the material of antifuse layer 108a is easier to change, and thickness can't be subjected to the etch process influence.And, by the material that changes antifuse layer 108a, breakdown voltage and element efficiency that can control storage.
In addition, the breakdown voltage of mnemon can be by the thickness decision of antifuse layer 108, and the thickness of antifuse layer 108 is by the long-pending technology decision in Shen, be not to decide by etch process and chemical mechanical milling tech, therefore that is process margin (Process window) can not be subjected to the influence of etch process and chemical mechanical milling tech, has bigger process margin.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; anyly have the knack of this skill person; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.
Claims (27)
1. single programmable read-only memory is characterized in that it comprises:
One first conductive-type semiconductor substrate;
One second conductivity type doped region is arranged in this first conductive-type semiconductor substrate;
One first conductivity type, first doped layer is arranged in this first conductive-type semiconductor substrate, and is positioned on this second conductivity type doped region;
One first conductivity type, second doped layer be arranged between this second conductivity type doped region and this first conductivity type, first doped layer, and this first conductivity type, second doped layer into strips, is as bit line;
One conductive layer is arranged on this first conductive-type semiconductor substrate, and this first conductive layer interlocks into strips and with this first conductivity type, first doped layer;
One second conductivity type, first doped layer is arranged in this first conductive-type semiconductor substrate, and between this conductive layer and this first conductivity type, first doped layer; And
One antifuse layer is arranged between this conductive layer and this second conductivity type, first doped layer.
2. single programmable read-only memory according to claim 1 is characterized in that wherein said first conductivity type is the P type; And this second conductivity type is the N type.
3. single programmable read-only memory according to claim 1 is characterized in that wherein said first conductivity type is the N type; And this second conductivity type is the P type.
4. single programmable read-only memory according to claim 1 is characterized in that the wherein said second conductivity type first doped layer top has a wedge angle.
5. single programmable read-only memory according to claim 1 is characterized in that the material of wherein said antifuse layer comprises silica.
6. single programmable read-only memory according to claim 1, the material that it is characterized in that wherein said antifuse layer comprise that dielectric constant is greater than 4 high dielectric constant material.
7. single programmable read-only memory according to claim 6, the material that it is characterized in that wherein said antifuse layer comprise silicon nitride, silicon oxynitride, aluminium oxide and hafnium oxide one of them.
8. single programmable read-only memory according to claim 1, the material that it is characterized in that wherein said conductive layer comprises one of them of conductiving doping semiconductor, doped polycrystalline silicon and metal material.
9. single programmable read-only memory according to claim 1 is characterized in that the impurity concentration of the impurity concentration of wherein said first conductivity type, second doped layer greater than this first conductivity type, first doped layer.
10. single programmable read-only memory according to claim 1 is characterized in that it more comprises:
Interbedded insulating layer is arranged on this Semiconductor substrate, and this interlayer insulating film has irrigation canals and ditches that are positioned at this second conductivity type, first doped layer top, and this conductive layer is arranged in these irrigation canals and ditches, and this antifuse layer is arranged between this interlayer insulating film and this conductive layer.
11. the manufacture method of a single programmable read-only memory is characterized in that it comprises:
One first conductive-type semiconductor substrate is provided, in this first conductive-type semiconductor substrate, down is formed with one second conductivity type, first doped layer, one first conductivity type, first doped layer, one first conductivity type, second doped layer and one second conductivity type doped region in regular turn by the surface;
This first conductive-type semiconductor substrate of patterning, with formation be strip this first conductivity type, second doped layer, be block this first conductivity type, first doped layer and be this block second conductivity type, first doped layer;
Carry out an etch process, make this second conductivity type, the first doped layer top that is block have a wedge angle;
On this first conductivity type substrate, form an antifuse layer;
On this antifuse layer, form an etch stop layer;
On this etch stop layer, form interbedded insulating layer;
This interlayer insulating film of patterning is with irrigation canals and ditches of this etch stop layer of formation exposure, and these irrigation canals and ditches are staggered with this second conductivity type, first doped layer that is strip;
Remove this etch stop layer that these irrigation canals and ditches expose; And
In these irrigation canals and ditches, form a conductive layer.
12. the manufacture method of single programmable read-only memory according to claim 11, it is characterized in that this first conductive-type semiconductor substrate of wherein said patterning, with formation be strip this first conductivity type, second doped layer, be block this first conductivity type, first doped layer and comprise with the step that is block this second conductivity type, first doped layer:
Carry out one first Patternized technique, remove this second conductivity type, first doped layer of part, this first conductivity type, first doped layer and this first conductivity type, second doped layer, exposing this second conductivity type doped region, and form this second conductivity type, first doped layer of being strip, be this first conductivity type, first doped layer of strip and be this first conductivity type, second doped layer of strip; And
Carry out one second Patternized technique, remove this second conductivity type, first doped layer of part and this first conductivity type, first doped layer, be this block second conductivity type, first doped layer and be this block first conductivity type, first doped layer with formation.
13. the manufacture method of single programmable read-only memory according to claim 11 is characterized in that wherein said first conductivity type is the P type; And this second conductivity type is the N type.
14. the manufacture method of single programmable read-only memory according to claim 11 is characterized in that wherein said first conductivity type is the N type; And this second conductivity type is the P type.
15. the manufacture method of single programmable read-only memory according to claim 11 is characterized in that the material of wherein said antifuse layer comprises silica.
16. the manufacture method of single programmable read-only memory according to claim 11, the material that it is characterized in that wherein said antifuse layer comprise that dielectric constant is greater than 4 high dielectric constant material.
17. the manufacture method of single programmable read-only memory according to claim 16, the material that it is characterized in that wherein said antifuse layer comprise silicon nitride, silicon oxynitride, aluminium oxide and hafnium oxide one of them.
18. the manufacture method of single programmable read-only memory according to claim 16 is characterized in that the impurity concentration of the impurity concentration of wherein said first conductivity type, second doped layer greater than this first conductivity type, second doped layer.
19. the manufacture method of a single programmable read-only memory,, it is characterized in that it comprises:
One first conductive-type semiconductor substrate is provided, in this first conductive-type semiconductor substrate, down is formed with one second conductivity type, first doped layer, one first conductivity type, first doped layer, one first conductivity type, second doped layer and one second conductivity type doped region in regular turn by the surface;
This first conductive-type semiconductor substrate of patterning, with formation be strip this first conductivity type, second doped layer, be block this first conductivity type, first doped layer and be this block second conductivity type, first doped layer;
On this first conductivity type substrate, form interbedded insulating layer;
This interlayer insulating film of patterning is with irrigation canals and ditches of this second conductivity type, first doped layer of formation exposure, and these irrigation canals and ditches are staggered with this second conductivity type, first doped layer that is strip;
Form an antifuse layer in this irrigation canals and ditches bottom with sidewall; And
In these irrigation canals and ditches, form a conductive layer.
20. the manufacture method of single programmable read-only memory according to claim 19, it is characterized in that this first conductivity type substrate of wherein said patterning, with formation be strip this first conductivity type, second doped layer, be block this first conductivity type, first doped layer and comprise with the step that is block this second conductivity type, first doped layer:
Carry out one first Patternized technique, remove this second conductivity type, first doped layer of part, this first conductivity type, first doped layer and this first conductivity type, second doped layer, exposing this second conductivity type doped region, and form this second conductivity type, first doped layer, this first conductivity type, first doped layer that is strip and this first conductivity type, second doped layer that is strip that is strip; And
Carry out one second Patternized technique, remove this second conductivity type, first doped layer of part and this first conductivity type, first doped layer, be block this second conductivity type, second doped layer and this first conductivity type, first doped layer that is bulk with formation.
21. the manufacture method of single programmable read-only memory according to claim 19, be characterised in that after the step of this first conductive-type semiconductor substrate of wherein said patterning with on this first conductivity type substrate, form this interlayer insulating film before, more comprise:
Carry out an etch process, make this second conductivity type, the first doped layer top that is block have a wedge angle.
22. the manufacture method of single programmable read-only memory according to claim 19 is characterized in that wherein said first conductivity type is the P type; And this second conductivity type is the N type.
23. the manufacture method of single programmable read-only memory according to claim 19 is characterized in that wherein said first conductivity type is the N type; And this second conductivity type is the P type.
24. the manufacture method of single programmable read-only memory according to claim 19 is characterized in that the material of wherein said antifuse layer comprises silica.
25. the manufacture method of single programmable read-only memory according to claim 19, the material that it is characterized in that wherein said antifuse layer comprise that dielectric constant is greater than 4 high dielectric constant material.
26. the manufacture method of the single programmable read-only memory of stating according to claim 25, the material that it is characterized in that wherein said antifuse layer comprise silicon nitride, silicon oxynitride, aluminium oxide and hafnium oxide one of them.
27. the manufacture method of single programmable read-only memory according to claim 19 is characterized in that the impurity concentration of the impurity concentration of wherein said first conductivity type, second doped layer greater than this first conductivity type, first doped layer.
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| CN104795397B (en) * | 2014-01-21 | 2018-11-16 | 中芯国际集成电路制造(上海)有限公司 | Storage unit, memory and its layout structure |
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| US5331196A (en) * | 1991-08-19 | 1994-07-19 | Micron Technology, Inc. | One-time, voltage-programmable, logic element |
| US6185122B1 (en) * | 1998-11-16 | 2001-02-06 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| CN1407627A (en) * | 2001-08-29 | 2003-04-02 | 力旺电子股份有限公司 | Non-volatility memory unit with separate bit line structure |
| US20030223291A1 (en) * | 2002-01-09 | 2003-12-04 | Tower Semiconductor, Ltd. | Multi-bit programmable memory cell having multiple anti-fuse elements |
| CN1157792C (en) * | 2001-02-02 | 2004-07-14 | 索尼公司 | Once programmable semiconductor nonvolatile memory device and making method thereof |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5331196A (en) * | 1991-08-19 | 1994-07-19 | Micron Technology, Inc. | One-time, voltage-programmable, logic element |
| US6185122B1 (en) * | 1998-11-16 | 2001-02-06 | Matrix Semiconductor, Inc. | Vertically stacked field programmable nonvolatile memory and method of fabrication |
| CN1157792C (en) * | 2001-02-02 | 2004-07-14 | 索尼公司 | Once programmable semiconductor nonvolatile memory device and making method thereof |
| CN1407627A (en) * | 2001-08-29 | 2003-04-02 | 力旺电子股份有限公司 | Non-volatility memory unit with separate bit line structure |
| US20030223291A1 (en) * | 2002-01-09 | 2003-12-04 | Tower Semiconductor, Ltd. | Multi-bit programmable memory cell having multiple anti-fuse elements |
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