CN100394357C - Power-saving mode adjusting method and its logic chip and computer system - Google Patents
Power-saving mode adjusting method and its logic chip and computer system Download PDFInfo
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- CN100394357C CN100394357C CNB2005101271957A CN200510127195A CN100394357C CN 100394357 C CN100394357 C CN 100394357C CN B2005101271957 A CNB2005101271957 A CN B2005101271957A CN 200510127195 A CN200510127195 A CN 200510127195A CN 100394357 C CN100394357 C CN 100394357C
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Abstract
The present invention relates to a power-saving mode adjusting method which is used between a CPU and a peripheral element controller in a computer system, and the peripheral element controller is connected with a peripheral element. Firstly, the present invention enters into a work state according to the CPU; the peripheral element and the peripheral element controller entering into a power-saving mode send out signals to the CPU unit at intervals of a first time span; subsequently, the present invention comes into a first idle state according to the CPU, and the peripheral element and the peripheral element controller coming into an electricity-saving mode send out signals to the CPU at intervals of a second time span; the second time span is longer than the first time span.
Description
Technical field
The present invention relates to a kind of power-saving mode adjusting method, particularly a kind of power-saving mode adjusting method between CPU (central processing unit) in the computer system and the peripheral cell controller.
Background technology
The motherboard of general personal computer or notebook computer, its basic comprising mainly by CPU (central processing unit) (Central Processing Unit hereinafter to be referred as: CPU), control various device chipset (Chipset) and some peripheral circuits formed, its CPU (central processing unit) is the core of whole computer system, most principal work is the running of handling and control between the whole computing machine each several part each other, and the computing of carrying out logic; Chipset then is the running of being responsible between contact CPU (central processing unit) and other peripherals, the combination of chipset also has a lot of different modes, two of the common employings of motherboard factories at present are one group mode, be used for being responsible for the most function of motherboard itself, these two main chips are called north bridge chips (North Bridge Chip) and South Bridge chip (South Bridge Chip), wherein north bridge chips is responsible for the bus of high speeds all on the contact. host plate, the usefulness of its bus mostly is 2GBps to 5GBps, and South Bridge chip is responsible for the communication between the I/O bus, be responsible for part more at a slow speed in the coupled system, and link up with ROM-BIOS (BIOS), the usefulness of its bus mostly is 10MBps between the 1GBps.
See also Fig. 1, it is each arrangements of components block scheme on the motherboard 1.Thus shown in the block scheme, we can find out clearly that motherboard 1 is with the framework of CPU (central processing unit) 11 as system, CPU (central processing unit) 11 is connected in the chipset of being made up of north bridge chips 121 and South Bridge chip 122 12, wherein (Front Side Bus FSB) 101 connects each other with CPU (central processing unit) (CPU) 11 north bridge chips 121 with a preposition bus; Connect each other and with AGP bus 103 and AGP (Accelerated Graphics Port with rambus 102 and primary memory (Main Memory) 13, AGP) 14 link up, and South Bridge chip 122 is with pci bus 104 and PCI interfaces (Peripheral ComponentInterconnect, PCI) 15 interconnect, ISA (IndustryStandard Architecture) interface 16 in addition that is connected with South Bridge chip in addition, USB (universal serial bus) (Universal Serial Bus, hereinafter to be referred as USB) interface 17, IDE (Integrated Drive Electronics) interface 18, mouse 19 and keyboard 20, and present more novel on the market motherboard, also be connected with Serial Advanced Technology Attachment interface (Serial Advanced Technology Attachment, SATA) 21 on the South Bridge chip.
Therefore, CPU (central processing unit) 11 must and the chipset 12 that constituted of north bridge chips 121 and South Bridge chip 122 between cooperatively interact whole computer system is operated normally, and make and to be external in the control that various electronic installations on the computer system can be subjected to CPU (central processing unit) 11 by various interface, for example: LCD, CD-ROM drive, hard disk, floppy disk, the peripherals of keyboard and mouse etc., and usually do not carry out any program and be external under the situation that the interfacing equipment of computer system not have to operate in whole computer system, can enter idle state (idle state) by duty through CPU (central processing unit) after the regular hour 11, to alleviate the burden of central processing unit under long-time running, and after CPU (central processing unit) 11 is entering idle state the demand of delivery capable of reducing power source, to reach whole computer system power saving and to prolong the time that battery that the portable computer system is equipped with uses.
In addition, present many on the market computer interface equipment has all possessed the very fast and easy-to-use USB transmission interface of transmission speed mostly and the usb host controller 1220 in the computer system South Bridge chip 122 is connected.
And usb host controller 1220 has the idle mechanism of oneself in addition, when usb host controller 1220 is found to have need not execution work, just can enter idle state and be failure to actuate, after the fixedly Preset Time of timer located therein 12201 arrives, just from idle state, be waken up and initiatively go to read and be stored in corresponding to its description unit (Descriptor) data that connect USB device (not shown) and whether renewal is arranged and need execution work in the primary memory (Main Memory) 13.And being carried out access, primary memory 13 just can allow CPU (central processing unit) get back to duty by idle state, and too short fixedly Preset Time will make CPU (central processing unit) 11 can't treat for a long time at idle state electricity-saving function to be had a greatly reduced quality, but but long fixedly Preset Time can make the usefulness of usb host controller 1220 not remarkable.Like this, not only can't make personal computer reach the requirement of power saving, also the battery life that therefore makes portable computer system (as: notebook computer, individual action digital assistants) be equipped with shortens for it, and shortcoming how to improve above-mentioned technological means is a development fundamental purpose of the present invention.
Summary of the invention
According to above-mentioned purpose, the invention provides a kind of power-saving mode adjusting method, be applied between the CPU (central processing unit) and peripheral cell controller in the computer system, wherein the peripheral cell controller is connected to peripheral cell, power-saving mode adjusting method comprises the following step: enter duty according to CPU (central processing unit), the peripheral cell and the peripheral cell controller that enter in the battery saving mode send signal every very first time length to CPU (central processing unit); And enter first idle state according to CPU (central processing unit), and the peripheral cell and the peripheral cell controller that enter battery saving mode send signal every second time span to CPU (central processing unit), and wherein second time span is greater than very first time length.
This power-saving mode adjusting method of the present invention, also comprise the following step: when this peripheral cell controller enters battery saving mode and this CPU (central processing unit) when entering second idle state, this peripheral cell controller sends this signal every the 3rd time span to this CPU (central processing unit); And enter battery saving mode and this CPU (central processing unit) when entering the 3rd idle state when this peripheral cell controller, this peripheral cell controller sends this signal every the 4th time span to this CPU (central processing unit), wherein the 3rd time span is greater than this very first time length and less than this second time span, and the 4th time span is greater than this very first time length and less than this second time span and the 3rd time span.
This power-saving mode adjusting method of the present invention, its applied this computer system also comprises internal memory, store the execution work listings data of corresponding this peripheral cell in this internal memory, and after this peripheral cell controller sent this signal to this CPU (central processing unit), the data processing that this CPU (central processing unit) is carried out was this execution work listings data that reads in this internal memory.
This power-saving mode adjusting method of the present invention, wherein this peripheral cell is mouse, keyboard or the tabulating machine that utilizes USB (universal serial bus) to transmit, and this peripheral cell controller is USB host controller and is integrated in the South Bridge chip that core logic chipset comprises, and this peripheral cell controller has comprised can be to the timer of this very first time length or this second time span counting.
This power-saving mode adjusting method of the present invention, wherein this South Bridge chip detects this CPU (central processing unit) and is in this duty or this first idle state, make this timer to send signal to select corresponding this very first time length or this second time span to this CPU (central processing unit) according to testing result.
The present invention provides a kind of core logic chipset in addition, be applied in the computer system, computer system includes CPU (central processing unit) and internal memory and is connected with peripheral cell, wherein stored has the execution work listings data, core logic chipset comprises: power source management controller, signal is connected in CPU (central processing unit), and it can detect CPU (central processing unit), and judges that CPU (central processing unit) is in running order or first idle state; And peripheral cell controller, signal is connected in CPU (central processing unit) and is connected in power source management controller, this peripheral cell controller is after entering battery saving mode, be positioned duty according to this CPU (central processing unit), then very first time length is sent signal at interval, and then make this CPU (central processing unit) read execution work listings data in the internal memory, carry out with the work of controlling this peripheral cell; Be in this first idle state according to this CPU (central processing unit), then second time span is sent signal at interval, and then reads the execution work listings data in the internal memory, carries out with the work of control peripheral cell, and wherein second time span is greater than very first time length.
This core logic chipset of the present invention, wherein this peripheral cell controller is a USB host controller, it can be controlled this peripheral cell, this peripheral cell controller comprises timer, make this peripheral cell controller after entering this battery saving mode, when being in one second idle state, can also the 3rd time span send signal, and then make this CPU (central processing unit) read this execution work listings data in this internal memory according to this CPU (central processing unit); When being in one the 3rd idle state according to this CPU (central processing unit), the 4th time span is sent signal at interval, and then make this CPU (central processing unit) read this execution work listings data in this internal memory, wherein the 3rd time span is greater than this very first time length and less than this second time span; The 4th time span is greater than this very first time length and less than this second time span and the 3rd time span.
The present invention provides a kind of computer system that battery saving mode is adjusted that has in addition, comprising: CPU (central processing unit); Peripheral cell; Core logic chipset comprises: power source management controller, signal are connected in CPU (central processing unit) so that CPU (central processing unit) is detected, and judge that CPU (central processing unit) is in running order or idle state; And peripheral cell controller, signal is connected in peripheral cell and is connected in power source management controller, this peripheral cell controller is in this duty according to CPU (central processing unit) after entering battery saving mode, then very first time length is sent signal to this CPU (central processing unit) at interval; Be in this idle state according to this CPU (central processing unit), then second time span is sent signal to this CPU (central processing unit) at interval, and wherein this second time span is greater than this very first time length.
Computer system of the present invention, also comprise internal memory, this stored has the execution work listings data, and this peripheral cell controller also comprises timer, this peripheral cell controller is after entering this battery saving mode, when being in this duty according to this CPU (central processing unit), then very first time length is sent signal at interval, and then make this CPU (central processing unit) read this execution work listings data in this internal memory, when being in this idle state according to this CPU (central processing unit), then second time span is sent signal at interval, and then this execution work listings data that this CPU (central processing unit) is read in this internal memory is carried out with the work of controlling this peripheral cell.
Computer system of the present invention, wherein this computer system is portable computer or desk-top computer, and this peripheral cell is a universal serial bus device.
Description of drawings
The present invention obtains more deep understanding by following accompanying drawing and detailed description:
Fig. 1 is each arrangements of components block scheme on the motherboard.
Fig. 2 is each element block diagram in the applied computer system of this power-saving mode adjusting method of the present invention.
Fig. 3 (a) improves the first preferred embodiment schematic flow sheet that the shortcoming of prior art develops this power-saving mode adjusting method that for the present invention.
Fig. 3 (b) for this USB (universal serial bus) master controller with at interval should very first time length and this second time span this CPU (central processing unit) is sent the signal block diagram that this reads the execution work listings data.
Fig. 4 (a) improves the second preferred embodiment schematic flow sheet that the shortcoming of prior art develops this power-saving mode adjusting method that for the present invention.
Fig. 4 (b) for this USB (universal serial bus) master controller with at interval should very first time length, this second time span and the 3rd time span send the signal block diagram that this reads the execution work listings data to this CPU (central processing unit).
Fig. 5 (a) improves the 3rd preferred embodiment schematic flow sheet that the disappearance of prior art develops this power-saving mode adjusting method that for the present invention.
Fig. 5 (b) for this USB (universal serial bus) master controller with at interval should very first time length, this second time span, the 3rd time span and the 4th time span send the signal that this reads the execution work listings data to this CPU (central processing unit).
Wherein, description of reference numerals is as follows:
Motherboard 1 CPU (central processing unit) 11 chipsets 12
Primary memory 13 AGP interfaces 14 peripheral component connecting interfaces 15
17 IDE interfaces 18,16 USB interfaces, ISA interface
Mouse 19 keyboards 20 STAT interfaces 21
Preposition bus 101 rambus 102 AGP buses 103
Pci bus 104 north bridge chips 121 South Bridge chips 122
The first idle state C3, the second idle state C2 the 3rd idle state C1
Duty C0 CPU (central processing unit) 31 core logic chipsets 32
Installed System Memory 33 universal serial bus devices 34,35
3223 very first time of timer length T 1 second time span T2
The 3rd time span T3 the 4th time span T4 power management master controller 3222
Embodiment
See also Fig. 2, it is each element block diagram in the applied computer system of power-saving mode adjusting method of the present invention, from figure, can clearly find out, power-saving mode adjusting method is between the CPU (central processing unit) 31 and core logic chipset 32 that is applied in the computer system to be comprised, wherein the bridging chip group of core logic chipset 32 for being made up of north bridge chips 321 and South Bridge chip 322.And on computer system, all can be connected with peripheral cell usually, in this figure, the universal serial bus device 34 of peripheral cell the most often to use now, 35 (for example: mouse, keyboard, tabulating machine and recreation joystick or the like ...) represent, and universal serial bus device 34,35 mainly send signal by 3221 pairs of CPU (central processing unit) 31 of the USB host controller that is comprised in the South Bridge chip 322, make CPU (central processing unit) 31 read the stored execution work listings data of Installed System Memory 33 that is positioned at computer system by north bridge chips 321, and then make universal serial bus device 34,35 can be at the content in the execution work listings data, the work in the execution work listings data.In addition, in South Bridge chip 322, also include power source management controller 3222, be connected in CPU (central processing unit) 31 with signal, power source management controller 3222 can detect CPU (central processing unit) 31, so that South Bridge chip 322 is learnt CPU (central processing unit) 31 in running order or idle states.And the present invention wherein principal character be, the USB host controller 3221 that in South Bridge chip 322, is comprised and the universal serial bus device 34 of its control, 35 enter battery saving mode after, situation when USB host controller 3221 can be in duty and this idle state at CPU (central processing unit) 31 respectively, allow USB host controller 3221 interval very first time length and second time span ground trigger CPU (central processing unit) 31 by timer (Timer) 3223, CPU (central processing unit) 31 can read the execution work listings data that is stored in the Installed System Memory 33 by north bridge chips 321.Wherein, second time span can be greater than very first time length.Like this, just, can make CPU (central processing unit) 31 prolong the time that is in idle state; And CPU (central processing unit) 31 is when being in duty, and therefore USB host controller 3221 can not make usefulness lower yet, and then can reach purpose of power saving, below more just feature of the present invention be illustrated with different embodiment.
See also Fig. 3 (a), it improves the first preferred embodiment schematic flow sheet that the shortcoming of prior art develops the power-saving mode adjusting method that for the present invention.At first, USB host controller 3221 enters battery saving mode with its universal serial bus device of controlling 34 or 35; Judge via the power source management controller in South Bridge chip 322 3222 whether CPU (central processing unit) 31 enters duty, if power source management controller 3222 judges that CPU (central processing unit) 31 is when being in this duty, then USB host controller 3221 is in running order according to CPU (central processing unit) 31, and CPU (central processing unit) 31 is sent the signal that reads the execution work listings data every very first time length; If power source management controller 3222 judges that CPU (central processing unit) 31 are when being in first idle state, then USB host controller 3221 is in first idle state according to CPU (central processing unit) 31 and CPU (central processing unit) 31 is sent the signal that reads the execution work listings data every second time span.Like this, the USB host controller 3221 that is comprised in the South Bridge chip 322 just can be different according to CPU (central processing unit) 31 state, allow the timer 3223 (Timer) in the USB host controller 3221 go CPU (central processing unit) 31 is sent signal, make the content of execution work listings data in the CPU (central processing unit) 31 reading system internal memories 33 to make USB host controller 3221 every different time spans.And following more just the present invention be described in detail at the described technical characterictic of first preferred embodiment.
Can know understanding by above-mentioned technical descriptioon, the USB host controller that comprised in the South Bridge chip 322 3221 can be according to CPU (central processing unit) 31 residing duties, go CPU (central processing unit) 31 sent with very first time length and read the execution work listings data; And can go CPU (central processing unit) 31 is sent the signal that reads the execution work listings data after second time span at interval according to CPU (central processing unit) 31 residing first idle states.And in order to improve the shortcoming that prior art is mentioned, principal character of the present invention is exactly to be the USB host controller 3221 that comprised in the above-mentioned South Bridge chip 322, go CPU (central processing unit) 31 is sent the signal that reads the execution work listings data in order to the interval very first time length and second time span, with the execution work inventory in the reading system internal memory 33; And very first time length needs the purpose greater than second time span, then is that to rest on time of duty long for the time ratio that can make CPU (central processing unit) 31 rest on idle state.CPU (central processing unit) 31 is when being in different conditions, USB host controller 3221 can send the signal relation that reads the execution work listings data to CPU (central processing unit) 31 in the mode of the interval very first time length or second time span, forms the block scheme shown in Fig. 3 (b).Can find out clearly from figure that when CPU (central processing unit) 31 enters duty C0 by the first idle state C3 the second time span T2 can convert very first time length T 1 to originally; And when CPU (central processing unit) 31 entered the first idle state C3 by duty C0, then very first time length T 1 converted the second time span T2 to.Therefore, under the principle of the second time span T2 greater than very first time length T 1, CPU (central processing unit) 31 rests on the time span of the first idle state C3 can be longer than the time span that rests on duty C0, like this, power-saving mode adjusting method of the present invention has improved the shortcoming of prior art really, and then reaches fundamental purpose of the present invention.
Please again referring to Fig. 4 (a), it improves the second preferred embodiment schematic flow sheet that the shortcoming of prior art develops the power-saving mode adjusting method that for the present invention.Process flow diagram can be clearly seen that thus, and at first, USB host controller 3221 enters a battery saving mode with its universal serial bus device of controlling 34 or 35; Then, judge via the power source management controller in South Bridge chip 322 3222 whether CPU (central processing unit) 31 enters duty, if power source management controller 3222 judges that CPU (central processing unit) 31 is in running order, then USB host controller 3221 can be according to CPU (central processing unit) 31 residing duties and to send the signal that reads the execution work listings data to CPU (central processing unit) 31 every very first time length; If power source management controller 3222 judges that CPU (central processing unit) 31 is to be in second idle state, then USB host controller 3221 can be according to CPU (central processing unit) 31 residing second idle states and to send the signal that reads the execution work listings data every the 3rd time span to CPU (central processing unit) 31.In this example, be in CPU (central processing unit) 31 different with first preferred embodiment enters second idle state by duty, and the main difference of second idle state and first idle state is when CPU (central processing unit) 31 is in first idle state, and each element in the computer system (for example: volatile ram, hard disk etc..) all is to be in low-voltage supply and low usefulness state; And CPU (central processing unit) 31 is if be in second idle state, still having subelement in the computer system is to be in normal operating mode (for example: volatile memory is idle and hard disk also is in normal condition), therefore, when entering second idle state according to CPU (central processing unit) 31, USB host controller 3221 is corresponding to send the signal that reads the execution work listings data with the 3rd time span at interval to CPU (central processing unit) 31, and wherein the 3rd length time can be greater than the second length time and less than very first time length.USB host controller 3221 sends the block scheme of signal relation formation shown in Fig. 4 (b) that reads the execution work listings data with interval very first time length T 1, the second time span T2 and the 3rd time span T3 to CPU (central processing unit) 31.
See also Fig. 5 (a) again, it improves the 3rd preferred embodiment schematic flow sheet that the shortcoming of prior art develops the power-saving mode adjusting method that for the present invention, thus process flow diagram we can clearly find out, at first, USB host controller 3221 enters a battery saving mode with its universal serial bus device of controlling; Judge via the power source management controller in South Bridge chip whether CPU (central processing unit) 31 enters duty, if it is in running order that power source management controller is judged CPU (central processing unit) 31, then USB host controller 3221 is in running order and CPU (central processing unit) 31 is sent the signal that reads the execution work listings data every very first time length according to CPU (central processing unit) 31; If power source management controller judges CPU (central processing unit) 31 and be in the 3rd idle state, then USB host controller 3221 is in the 3rd idle state according to CPU (central processing unit) 31 and CPU (central processing unit) 31 is sent the signal that reads the execution work listings data every the 4th time span.In the present embodiment, the different CPU (central processing unit) 31 that are with above-mentioned preferred embodiment enter the 3rd idle state by duty, with the 4th time span CPU (central processing unit) 31 is sent the signal that reads the execution work listings data and USB host controller 3221 is corresponding, wherein the 4th length time can be greater than the second length time and less than the first and the 3rd time span.USB host controller 3221 sends the block scheme of signal relation formation shown in Fig. 5 (b) that reads the execution work listings data with interval very first time length T 1, the second time span T2, the 3rd time span T3 and the 4th time span T4 to CPU (central processing unit) 31, because of the part technical descriptioon is all identical with the foregoing description, so do not repeat them here.
Comprehensive the above; via first preferred embodiment; after the explanation of second preferred embodiment and the 3rd preferred embodiment; we can clearly find; power-saving mode adjusting method of the present invention can enter duty and idle state or enter the depth degree of idle state according to CPU (central processing unit); the USB host controller that utilizes in the South Bridge chip to be comprised makes CPU (central processing unit) under different state of living in and correspondingly give different time spans and CPU (central processing unit) is sent the signal that reads the execution work listings data; its topmost purpose all be for make CPU (central processing unit) time of idle state can greater than in working order time to reach less electricity consumption; and utilize technological means of the present invention to improve the shortcoming of prior art really; and then finish the main purpose of the present invention; but the preferred embodiment that the above is only invented for the present invention; be not in order to limit the present invention's invention; and technological thought of the present invention more can be applied to the desk-top computer of general family expenses widely; numeral action assistant; in the computer system of notebook computer or the like; therefore; the present invention carries out various modifications by those skilled in the art, the claimed scope of right neither disengaging appending claims.
Claims (10)
1. a power-saving mode adjusting method is applicable to computer system, and this computer system is provided with CPU (central processing unit) and peripheral cell, and this peripheral cell is connected with the peripheral cell controller, and this power-saving mode adjusting method comprises the following step:
When this peripheral cell controller enters battery saving mode and this CPU (central processing unit) when entering duty, this peripheral cell controller sends signal every very first time length to this CPU (central processing unit), and then makes this CPU (central processing unit) carry out data processing action; And
When this peripheral cell controller enters battery saving mode and this CPU (central processing unit) when entering first idle state, this peripheral cell controller sends this signal every second time span to this CPU (central processing unit), and then wakes this CPU (central processing unit) up and carry out this data processing action;
Wherein, this second time span is greater than this very first time length.
2. this power-saving mode adjusting method as claimed in claim 1 also comprises the following step:
When this peripheral cell controller enters battery saving mode and this CPU (central processing unit) when entering second idle state, this peripheral cell controller sends this signal every the 3rd time span to this CPU (central processing unit); And
When this peripheral cell controller enters battery saving mode and this CPU (central processing unit) when entering the 3rd idle state, this peripheral cell controller sends this signal every the 4th time span to this CPU (central processing unit), wherein the 3rd time span is greater than this very first time length and less than this second time span, and the 4th time span is greater than this very first time length and less than this second time span and the 3rd time span.
3. this power-saving mode adjusting method as claimed in claim 1, its applied this computer system also comprises internal memory, store the execution work listings data of corresponding this peripheral cell in this internal memory, and after this peripheral cell controller sent this signal to this CPU (central processing unit), the data processing action that this CPU (central processing unit) is carried out was for reading this execution work listings data in the internal memory.
4. this power-saving mode adjusting method as claimed in claim 1, wherein this peripheral cell is mouse, keyboard or the tabulating machine that utilizes USB (universal serial bus) to transmit, and this peripheral cell controller is USB host controller and is integrated in the South Bridge chip that core logic chipset comprises, and this peripheral cell controller has comprised can be to the timer of this very first time length or this second time span counting.
5. this power-saving mode adjusting method as claimed in claim 4, wherein this South Bridge chip detects this CPU (central processing unit) and is in this duty or this first idle state, make this timer to send signal to select corresponding this very first time length or this second time span to this CPU (central processing unit) according to testing result.
6. one kind has the core logic chipset that battery saving mode is adjusted, be applied in the computer system, this computer system includes CPU (central processing unit) and internal memory and is connected with peripheral cell, and wherein this stored has the execution work listings data, and this core logic chipset comprises:
Power source management controller, signal are connected in this CPU (central processing unit), and it can detect this CPU (central processing unit), and judge that this CPU (central processing unit) is in running order or first idle state; And
The peripheral cell controller, signal is connected in this peripheral cell and is connected in this power source management controller, after this peripheral cell controller enters battery saving mode, be in this duty according to this CPU (central processing unit), then very first time length is sent signal at interval, and then make this CPU (central processing unit) read this execution work listings data in this internal memory, carry out with the work of controlling this peripheral cell; Be in this first idle state according to this CPU (central processing unit), then second time span is sent signal at interval, and then make this CPU (central processing unit) read this execution work listings data in this internal memory, carry out with the work of controlling this peripheral cell, wherein this second time span is greater than this very first time length.
7. this core logic chipset as claimed in claim 6, wherein this peripheral cell controller is a USB host controller, it can be controlled this peripheral cell, this peripheral cell controller comprises timer, make this peripheral cell controller after entering this battery saving mode, when being in one second idle state according to this CPU (central processing unit), at interval the 3rd time span be sent signal, and then makes this CPU (central processing unit) read this execution work listings data in this internal memory; When being in one the 3rd idle state according to this CPU (central processing unit), the 4th time span is sent signal at interval, and then make this CPU (central processing unit) read this execution work listings data in this internal memory, wherein the 3rd time span is greater than this very first time length and less than this second time span; The 4th time span is greater than this very first time length and less than this second time span and the 3rd time span.
8. one kind has the computer system that battery saving mode is adjusted, and comprising:
CPU (central processing unit);
Peripheral cell;
Core logic chipset comprises:
Power source management controller, signal are connected in this CPU (central processing unit) so that this CPU (central processing unit) is detected, and judge that this CPU (central processing unit) is in running order or idle state; And
The peripheral cell controller, signal is connected in this peripheral cell and is connected in this power source management controller, this peripheral cell controller is in this duty according to this CPU (central processing unit) after entering battery saving mode, then very first time length is sent signal to this CPU (central processing unit) at interval; Be in this idle state according to this CPU (central processing unit), then second time span is sent signal to this CPU (central processing unit) at interval, and wherein this second time span is greater than this very first time length.
9. computer system as claimed in claim 8, also comprise internal memory, this stored has the execution work listings data, and this peripheral cell controller also comprises timer, this peripheral cell controller is after entering this battery saving mode, when being in this duty according to this CPU (central processing unit), then very first time length is sent signal at interval, and then make this CPU (central processing unit) read this execution work listings data in this internal memory, when being in this idle state according to this CPU (central processing unit), then second time span is sent signal at interval, and then this execution work listings data that this CPU (central processing unit) is read in this internal memory is carried out with the work of controlling this peripheral cell.
10. computer system as claimed in claim 8, wherein this computer system is portable computer or desk-top computer, and this peripheral cell is a universal serial bus device.
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| CN101980103A (en) * | 2010-10-29 | 2011-02-23 | 威盛电子股份有限公司 | Power state management method and related computer system |
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2005
- 2005-11-28 CN CNB2005101271957A patent/CN100394357C/en active Active
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5369771A (en) * | 1991-12-23 | 1994-11-29 | Dell U.S.A., L.P. | Computer with transparent power-saving manipulation of CPU clock |
| CN1122465A (en) * | 1994-09-28 | 1996-05-15 | 三星电子株式会社 | Power-supply controller of computer |
| CN1595332A (en) * | 2003-09-08 | 2005-03-16 | 三星电子株式会社 | Computer system and a control method thereof |
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