CN100395876C - Manufacturing method of power metal oxide semiconductor field-effect transistor - Google Patents
Manufacturing method of power metal oxide semiconductor field-effect transistor Download PDFInfo
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- CN100395876C CN100395876C CNB031594220A CN03159422A CN100395876C CN 100395876 C CN100395876 C CN 100395876C CN B031594220 A CNB031594220 A CN B031594220A CN 03159422 A CN03159422 A CN 03159422A CN 100395876 C CN100395876 C CN 100395876C
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Abstract
The present invention provides a manufacture method of a power metal oxide semiconductor field effect transistor. The manufacture method uses different ion sources to adjust the growing speed of insulation layers positioned at the different parts of a trench. A base material of a first conductive type is first provided, an epitaxial layer of the first conductive type is formed above the base material, and a main body area of a second conductive type is formed on the built crystal layer. Then, the main body area, the built crystal layer and the base material are etched to form a trench, an ion implantation process is carried out to the side wall or the bottom of the trench, and then, an insulation layer is formed at the surface of the trench to be used as a liner of the trench. Subsequently, a source electrode area of the first conductive type is formed in a position adjacent to the trench in the main body area. Finally, a conductive material is deposited in the trench to be used as a grid electrode of a double-diffused transistor of the trench.
Description
Technical field
The present invention relates to a kind of manufacture method of mos field effect transistor, and particularly relate to a kind of manufacture method with power metal oxide semiconductor field-effect transistor of irrigation canals and ditches structure.
Background technology
(double diffused MOS is that (metal on semiconductor field effect transistor MOSFET), utilizes diffusion to form its transistor area to a kind of mos field effect transistor DMOS) to double-diffused transistor.Double-diffused transistor is used under the requirement of low forward pressure drop, provide higher per unit area electric current as the power transistor that is used for high-tension power integrated circuit usually.
One particular type of double-diffused transistor is a so-called irrigation canals and ditches double-diffused transistor (trench DMOS transistor) 100, shown in Figure 1A.The grid 104 of irrigation canals and ditches double-diffused transistor 100 is formed among the irrigation canals and ditches 116a, and these irrigation canals and ditches 116a extends between source electrode 106 and the drain electrode 108, is etched to N from P type doped body zone 102
-Type doping epitaxial layer 103 and forming.The surface of irrigation canals and ditches 116a, and is filled in wherein with polysilicon 114 as liner by coating one thin silicon oxide layer 112.The channel of this irrigation canals and ditches double-diffused transistor 100 (tunnel) can be formed at the both sides of its irrigation canals and ditches 116a, and its drain electrode and source current I
Ds122a then can vertically transmit along its channel.Therefore, drain electrode and source current I
Ds122a sets out from source electrode 106, in regular turn by P type doped body zone 102, N
-Type doping epitaxial layer 103 and N
+Type doping base material 101 arrives drain electrode 108 at last.The relevant patent of irrigation canals and ditches double-diffused transistor is disclosed in United States Patent (USP) the 5th, 072, and 266,5,541,425 and 5,866, among No. 931.
The irrigation canals and ditches double-diffused transistor 100 of prior art has conducting resistance (on resistance) problem of higher usually.Therefore in order to solve the problem of high conducting resistance, the irrigation canals and ditches double-diffused transistor of another kind of similar structures is suggested, shown in Figure 1B.Please refer to Figure 1B, the irrigation canals and ditches double-diffused transistor 100 among irrigation canals and ditches double-diffused transistor 110 and Figure 1A, both differences are in the etch depth difference in both irrigation canals and ditches.Irrigation canals and ditches 116b is 102 beginning etchings from P type doped body zone, pass N earlier
-Behind the type doping epitaxial layer 103, partially-etched again N
+Type doping base material 101 and forming.
Similarly, the channel of irrigation canals and ditches double-diffused transistor 110 can be formed at the both sides of its irrigation canals and ditches 116b, and its drain-source current I
Ds122b then can vertically transmit along its channel.Be compared to the irrigation canals and ditches 116a among Figure 1A, the many etchings of irrigation canals and ditches 116b N
-Type doping epitaxial layer 103 and N
+Type doping base material 101, so irrigation canals and ditches double-diffused transistor 110 provides than long channel for I
Ds122b transmits.That is to say that the irrigation canals and ditches double-diffused transistor 110 among Figure 1B utilizes its long channel to reduce its conducting resistance, to improve the high conducting resistance problem of the irrigation canals and ditches double-diffused transistor 100 among Figure 1A.
In general, good irrigation canals and ditches double-diffused transistor will have low on-resistance and high-breakdown-voltage.Yet, for the irrigation canals and ditches double-diffused transistor, normally a kind of between the two balance of low on-resistance and high-breakdown-voltage (breakdown voltage) relation, when wherein one when improving, other one understand variation usually, are difficult to both and take into account.
With the irrigation canals and ditches double-diffused transistor 110 among Figure 1B, though it has improved the problem of the high conducting resistance of prior art, but because the bottom of its irrigation canals and ditches 116b is too near drain electrode 108, make its puncture voltage reduce on the contrary, therefore increased it possibility of electrical breakdown takes place because of low grid voltage.As previously mentioned, double-diffused transistor is used to generally can use the high voltage that is higher than more than 30 volts to operate as the power transistor that is used for high-tension power integrated circuit usually.In some special applications, as employed power transistor in the LCD, its operating voltage is 48 volts high voltage more.Therefore, these high-tension operating environments have more increased the probability that electrical breakdowns take place irrigation canals and ditches double-diffused transistor 110.
Summary of the invention
The manufacture method that the purpose of this invention is to provide a kind of power metal oxide semiconductor field-effect transistor is in order to the problem of low conducting voltage of can't taking into account of the double-diffused transistor that improves prior art and high-breakdown-voltage.
Another object of the present invention then provides a kind of manufacture method of power metal oxide semiconductor field-effect transistor, has the double-diffused transistor of low conducting voltage and high-breakdown-voltage in order to production.
In order to realize above-mentioned purpose of the present invention, a kind of manufacture method of power metal oxide semiconductor field-effect transistor is proposed.Irrigation canals and ditches double-diffused transistor among the present invention, its irrigation canals and ditches begin vertical etching to its substrate by body region, and the present invention also imposes an ion disposing process to these irrigation canals and ditches, utilize different ion source adjustment to be positioned at the growth speed of insulating barrier of the different parts of irrigation canals and ditches, for example suppress the growth speed of insulating barrier at trench sidewall, and improve the growth speed of insulating barrier, perhaps improve the growth speed of insulating barrier simultaneously in the irrigation canals and ditches bottom in the irrigation canals and ditches bottom.So make irrigation canals and ditches double-diffused transistor of the present invention, not only channel extends to substrate, and the insulating barrier thickness that is positioned at irrigation canals and ditches bottoms also is positioned at the thickness of trench sidewall greater than insulating barrier, except the probability that the electrical breakdown that can reduce prior art takes place, and can take into account the advantage of low on-resistance, to improve its drain electrode and source current.
Manufacture method of the present invention is the base material that one first conduction type is provided earlier, and the epitaxial layer that forms one first conduction type again and forms the body region of one second conduction type on this epitaxial layer on base material.This body region of etching, epitaxial layer and base material are to form irrigation canals and ditches then, and this irrigation canals and ditches autonomous agent zone extends to base material, and with the sidewall of these irrigation canals and ditches of nitrogen implanting ions of a predetermined angular, or plant bottom or its compound mode of these irrigation canals and ditches with argon ion cloth.Behind implanting ions, carry out an annealing process.Then, form the liner of an insulating barrier on the surface of these irrigation canals and ditches as irrigation canals and ditches.Then, among body region, form the source region of first conduction type with the irrigation canals and ditches position adjacent.At last, deposit a conductive material among irrigation canals and ditches, as the grid of this irrigation canals and ditches double-diffused transistor.
According to a preferred embodiment of the present invention, the material of the insulating barrier of irrigation canals and ditches double-diffused transistor is a silica, and when carrying out above-mentioned implanting ions, is 2.5 * 10 with the concentration of nitrogen ion
14Cm
-3, it is 12kV that cloth is planted energy, and cloth plants the conditions that angle 318 is 30 degree, cloth is planted the sidewall of nitrogen ion in irrigation canals and ditches, to form the growth speed of insulating barrier after suppressing at the sidewall of irrigation canals and ditches.According to another preferred embodiment of the present invention, then utilize argon ion to carry out ion disposing process, to help to quicken the growth speed of insulating barrier.
It should be noted that these two kinds in order to suppress and to increase the ion disposing process of insulating barrier growth speed, except both use separately, also can optionally apply to respectively among the same irrigation canals and ditches double-diffused transistor, be not limited in indivedual independent uses.
The present invention extends to substrate with the irrigation canals and ditches degree of depth of the irrigation canals and ditches double-diffused transistor of prior art, again its irrigation canals and ditches are utilized an ion disposing process, make the thickness that is positioned at the irrigation canals and ditches bottom of its insulating barrier be positioned at the thickness of trench sidewall greater than it, therefore not only can obtain lower conducting resistance, increase its drain electrode and source current, and can take into account and have higher puncture voltage.Applied dry ecthing procedure of the present invention and ion disposing process, be all the technology of knowing in the manufacture of semiconductor now, do not need special equipment or fabrication steps can implement manufacture method of the present invention, improve the problem of only high conducting resistance of prior art irrigation canals and ditches double-diffused transistor and low breakdown voltage effectively.
Description of drawings
Below in conjunction with accompanying drawing,, will make technical scheme of the present invention and other beneficial effects apparent by the specific embodiment of the present invention is described in detail.
In the accompanying drawing,
Figure 1A is depicted as the schematic diagram of the irrigation canals and ditches double-diffused transistor of prior art;
Figure 1B is depicted as the schematic diagram of the another kind of irrigation canals and ditches double-diffused transistor of prior art;
Figure 2 shows that the flow chart of manufacture method of the present invention; And
Fig. 3 A to 3G is depicted as the schematic diagram corresponding to the irrigation canals and ditches double-diffused transistor of the step among Fig. 2.
Embodiment
The present invention and can take into account the advantage of low on-resistance except the probability that the electrical breakdown that can reduce prior art takes place, to improve drain electrode and source current.
Ion is introduced the technology that silicon substrate reduces or increase the oxidation rate of silicon substrate develop out, wherein comprise the method for utilizing implanting ions to introduce.For example, in " IEEE Electron Device Letters " article " Simultaneous Growth ofDifferent Thickness Gate Oxides in Silicon CMOSProcessing " of the 16th the 7th phase of volume, people such as author Doyle just provide a kind of the nitrogen ion are implanted the planar silicon wafer, to form the processing procedure of the gate oxide of different-thickness simultaneously on wafer.
Therefore, the present invention imposes an ion disposing process to the irrigation canals and ditches of an irrigation canals and ditches double-diffused transistor, utilize different ion source adjustment to be positioned at the growth speed of insulating barrier of the different parts of irrigation canals and ditches, and these irrigation canals and ditches begins vertical etching to its substrate by body region.So, make the irrigation canals and ditches double-diffused transistor, not only its channel extends to substrate, and its insulating barrier thickness of being positioned at the irrigation canals and ditches bottom also is positioned at the thickness of trench sidewall greater than its insulating barrier.
Figure 2 shows that the flow chart of manufacture method of the present invention, Fig. 3 A to 3G is depicted as the schematic diagram corresponding to the irrigation canals and ditches double-diffused transistor of the step among Fig. 2.Below utilize Fig. 2 and cooperate Fig. 3 A to 3G, explain the manufacture method with irrigation canals and ditches double-diffused transistor of polycrystalline silicon germanium grid of the present invention.
At first, provide a N
+Type doping base material 302 (steps 202), building crystal to grow forms a N then
-Type doping epitaxial layer 304 is in N
+On the type doping base material 302 (step 204).Afterwards again in this N
-On the type doping epitaxial layer 304, form a P type doped body zone 306 (steps 206), as shown in Figure 3A.
Then, utilize this P type doped body zone 306 of a dry ecthing procedure etching, N
-Type doping epitaxial layer 304 and N
+Type doping base material 302 is to form irrigation canals and ditches 312 (step 208), shown in Fig. 3 B.This dry ecthing procedure utilize earlier one firmly shielding (hard mask) layer (among Fig. 3 B expression) be covered in P type doped body zone 306, this hard screen of pictureization makes it expose an opening to define the position of irrigation canals and ditches 312 in P type doped body zone 306 again.The opening that exposed of this hard screen of dry ecthing begins etching from the surface in P type doped body zone 306, and extends to N then
-Type doping epitaxial layer 304 and N
+Type doping base material 302 just forms these irrigation canals and ditches 312 at last.
Shown in Fig. 3 C, remove above-mentioned in order to carry out carrying out the sidewall 314 of an ion disposing process, to form the growth speed of insulating barriers after suppressing at the sidewall 314 of irrigation canals and ditches 312 after the hard screen that dry ecthing procedure uses in irrigation canals and ditches 312.According to a preferred embodiment of the present invention, the material of the insulating barrier of this irrigation canals and ditches double-diffused transistor is a silica, and when carrying out above-mentioned implanting ions, is 2.5 * 10 with the concentration of nitrogen ion
14Cm
-3, it is 12kV that cloth is planted energy, and cloth plant angle 318 be 30 the degree conditions, cloth is planted the sidewall 314 of nitrogen ion in irrigation canals and ditches 312.
Then, when the growth insulating layer of silicon oxide, this moment, insulating layer of silicon oxide was positioned at the thickness of the bottom 316 of irrigation canals and ditches 312, will be in insulating layer of silicon oxide be positioned at irrigation canals and ditches 312 sidewall 314 thickness twice, suppressed the growth speed of insulating layer of silicon oxide significantly at the sidewall 314 of irrigation canals and ditches 312.So, can avoid causing drain-source current I because the insulating barrier of the sidewall 314 of irrigation canals and ditches 312 is too thick
DsThe problem that reduces.Under the prerequisite of the thickness of insulating layer of the sidewall 314 that does not increase irrigation canals and ditches 312, increase the thickness of insulating barrier separately, to improve the problem of prior art low breakdown voltage in the bottom 316 of irrigation canals and ditches 312.
On the other hand, except as mentioned above, sidewall 314 to irrigation canals and ditches 312 carries out an ion disposing process, for example use the nitrogen implanting ions, with outside the growth speed that suppresses its insulating barrier (step 209), on the contrary, also can carry out another ion disposing process to the bottom 316 of irrigation canals and ditches 312, for example use argon ion cloth to plant, to increase the growth speed (step 209) of its insulating barrier.It should be noted that these two kinds in order to suppress and to increase the ion disposing process of insulating barrier growth speed, except both use separately, also can optionally apply to respectively among the same irrigation canals and ditches double-diffused transistor, be not limited in indivedual independent uses.
Shown in Fig. 3 D, be depicted as and carry out the bottom 316 of an ion disposing process, to form the growth speed of insulating barrier after increasing in the bottom 316 of irrigation canals and ditches 312 in irrigation canals and ditches 312.According to another preferred embodiment of the present invention, utilize argon ion to carry out ion disposing process this moment, to help to quicken the growth speed of insulating barrier.Similarly, so can avoid causing drain electrode and source current I because the insulating barrier of the sidewall 314 of irrigation canals and ditches 312 is too thick
DsThe problem that reduces.Under the prerequisite of the thickness of insulating layer of the sidewall 314 that does not increase irrigation canals and ditches 312, increase the thickness of insulating barrier separately, to improve the problem of prior art low breakdown voltage in the bottom 316 of irrigation canals and ditches 312.
Then, one silica layer 322 be formed on the surface in P type doped body zone 306 and irrigation canals and ditches 312 around (step 210).This silicon oxide layer 322 is an insulating barrier of using as liner.At this moment, because irrigation canals and ditches 312 have passed through the processing of ion disposing process, so the thickness of the silicon oxide layer 322 of the bottom 316 of irrigation canals and ditches 312, meeting is greater than the thickness of the silicon oxide layer 322 of the sidewall 314 of irrigation canals and ditches 312.
And, use above-mentioned sidewall 314 to carry out ion disposing process if select separately to irrigation canals and ditches 312, then because the ion that this moment, cloth was planted is with a predetermined angular, for example angle 318, implant among the sidewall 314, therefore irrigation canals and ditches 312 are more little the closer to the influence of the suffered implanting ions of its bottom 316 parts, and make that the past more irrigation canals and ditches of thickness 312 bottoms 316 of this silicon oxide layer 322 can be thick more, shown in Fig. 3 E.In order to explain orally convenient and to highlight feature of the present invention, Fig. 3 F then and Fig. 3 G also continue to use the shape of silicon oxide layer 322 among Fig. 3 E in the lump, promptly use the above-mentioned situation that the sidewall 314 of irrigation canals and ditches 312 is carried out ion disposing process to illustrate with independent selection.
Then, utilize photoresistance 332 to define N again
+The position in type doped source zone 324, this N
+The position in type doped source zone 324 is arranged in P type doped body zone 306, and adjacent with irrigation canals and ditches 312.Utilize ion disposing process to implant alloy again, for example phosphorus or arsenic are to form this N
+Type doped source zone 324, afterwards and remove above-mentioned photoresistance 332 (step 212).Certainly, after implanting ions, also can impose annealing (annealing) processing procedure to repair it because of the impaired lattice structure of implanting ions.
At last, carry out the chemical vapor deposition process of a polycrystalline silicon germanium, with conductive material, for example polysilicon 326 is filled among the irrigation canals and ditches 312, as the grid (step 214) of this irrigation canals and ditches double-diffused transistor.As know known to this skill person, this irrigation canals and ditches double-diffused transistor can be at its N when finishing
+ Add source electrode 334 on the type doped source zone 324, and at its N
+The basal surface of type base material 302 forms a drain electrode layer 336.And in this embodiment, the present invention is to be that the N type mixes and second conduction type is that the P type is doped to example with first conduction type.Yet know this skill person when knowing, among the embodiment that the present invention can be applicable to also that first conduction type mixes for the P type and second conduction type mixes for the N type.And, the P type mixes and the N type mixes alloy that employed alloy is not limited in the present embodiment to be mentioned, the alloy of having used of various prior aries all can apply among the present invention.
The present invention extends to substrate with the irrigation canals and ditches degree of depth of the irrigation canals and ditches double-diffused transistor of prior art, again its irrigation canals and ditches are utilized an ion disposing process, make the thickness that is positioned at the irrigation canals and ditches bottom of its insulating barrier be positioned at the thickness of trench sidewall greater than it, therefore not only can obtain lower conducting resistance, increase its drain electrode and source current I
Ds, and can take into account and have higher puncture voltage.Applied dry ecthing procedure of the present invention and ion disposing process, be all the technology of knowing in the manufacture of semiconductor now, do not need special equipment or fabrication steps can implement manufacture method of the present invention, improve the problem of only high conducting resistance of prior art irrigation canals and ditches double-diffused transistor and low breakdown voltage effectively.
The above; for the person of ordinary skill of the art; can make other various corresponding changes and distortion according to technical scheme of the present invention and technical conceive, and all these changes and distortion all should belong to the protection range of accompanying Claim of the present invention.
Claims (6)
1. the manufacture method of a power metal oxide semiconductor field-effect transistor is characterized in that, this manufacture method comprises the following step at least:
The base material of one conduction type is provided;
The epitaxial layer that forms one first conduction type is on this base material;
The body region that forms one second conduction type is on this epitaxial layer;
This body region of etching, this epitaxial layer and this base material, to form at least one irrigation canals and ditches, wherein these irrigation canals and ditches extend to this base material from this body region;
With the sidewall of these irrigation canals and ditches of nitrogen implanting ions of a predetermined angular, or plant bottom or its compound mode of these irrigation canals and ditches with argon ion cloth;
After this implanting ions, carry out an annealing process;
Form the liner of an insulating barrier as these irrigation canals and ditches;
The source region that forms at least one first conduction type is among this body region and adjacent with these irrigation canals and ditches; And
Deposit a conductive material among these irrigation canals and ditches and cover on this insulating barrier, to form an area of grid.
2. manufacture method according to claim 1 is characterized in that, this insulating barrier is a silicon oxide layer.
3. manufacture method according to claim 1 is characterized in that, this manufacture method more comprises the step of an alloy among this conductive material of mixing.
4. manufacture method according to claim 1 is characterized in that, the step of this body region of this etching and this epitaxial layer is to utilize this body region of dry ecthing procedure etching and this epitaxial layer, to form this irrigation canals and ditches.
5. manufacture method according to claim 1 is characterized in that, this step that forms this source region comprises at least:
Form a photoresist layer on this body region;
This photoresist layer of patterning; And
At least one alloy of implanting ions is to form the source region of this first conduction type among this body region;
This source region and adjacent wherein with these irrigation canals and ditches.
6. manufacture method according to claim 1 is characterized in that, this step that deposits this electric conducting material is to utilize a chemical vapor deposition process, deposits this electric conducting material among these irrigation canals and ditches and cover on this insulating barrier, to form this area of grid.
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| CNB031594220A CN100395876C (en) | 2003-09-16 | 2003-09-16 | Manufacturing method of power metal oxide semiconductor field-effect transistor |
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Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN101764061B (en) * | 2008-12-26 | 2012-05-30 | 马克斯半导体股份有限公司 | Power metal-oxide-semiconductor field effect transistor structure and processing method thereof |
| US8264066B2 (en) * | 2009-07-08 | 2012-09-11 | Taiwan Semiconductor Manufacturing Company, Ltd. | Liner formation in 3DIC structures |
| TWI455315B (en) * | 2011-01-13 | 2014-10-01 | Anpec Electronics Corp | A ditch - type power transistor with a low gate / drain capacitance |
| CN112582264A (en) * | 2019-09-27 | 2021-03-30 | 深圳市卓朗微电子有限公司 | Improved method for forming low gate capacitance trench power transistor by nitrogen ion implantation of silicon oxide layer |
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