CN100395881C

CN100395881C - Nonvolatile memories and methods of fabrication

Info

Publication number: CN100395881C
Application number: CNB2004100588753A
Authority: CN
Inventors: 丁逸
Original assignee: MAOXI ELECTRONIC CO Ltd TAIWAN
Current assignee: MAOXI ELECTRONIC CO Ltd TAIWAN
Priority date: 2003-07-30
Filing date: 2004-07-30
Publication date: 2008-06-18
Anticipated expiration: 2024-07-30
Also published as: JP2005051244A; CN1585109A; TW200516727A; TWI247390B

Abstract

To fabricate a nonvolatile memory, a select gate (140) is formed over a semiconductor substrate. A dielectric (810, 1010, 1030) is formed over the select gate. A floating gate layer (160), e.g. doped polysilicon, is formed over the select gate. The floating gate layer is removed from over at least a portion of the select gate. A dielectric (1510), e.g., ONO, is formed over the floating gate layer, and a control gate layer (170) is formed over this dielectric. The control gate layer has an upward protrusion over the select gate. Then another layer (1710), e.g. silicon nitride, is formed on the control gate layer, but the protrusions of the control gate layer are exposed. The exposed portion of the control gate layer is etched selectively until the control gate layer is removed from over at least a portion of the select gate. Then another layer (1910) is formed on the exposed portion of the control gate layer. This is thermally grown silicon dioxide in some embodiments. Then the silicon nitride is removed. The control gate layer, the ONO, and the floating gate layer are etched selectively to the silicon dioxide to define the control and floating gates.

Description

Non-voltile memory and manufacture method thereof

Technical field

The present invention relates to a kind of non-voltile memory and manufacture method thereof, relate in particular to a kind of integrated circuit and manufacture method thereof that contains non-voltile memory.

Background technology

The present invention is the part of the 10/393rd, No. 212 U.S. patent application case of on March 19th, the 2003 application application case that continues, and it is incorporated herein by reference.

Fig. 1 shows the profile of a flash cell, and it is described in checked and approved No. the 6th, 057,575, the United States Patent (USP) of Jenq on May 2nd, 2000.This memory cell is formed at semiconductor substrate 120 and top thereof, silicon dioxide layer 130 thermosettings are on semiconductor substrate 120, select lock 140 to be formed on the silicon dioxide layer 130, silicon dioxide layer 150 thermosettings are on the zone that the not selected lock of semiconductor substrate 120 covers, ONO layer 154 (the sandwich interlayer of silicon dioxide layer, silicon nitride layer and silicon dioxide layer) is formed to be selected on the lock 140, floating gate 160 is formed on the dielectric layer 150,154, and the part of floating gate 160 is covered in to be selected on the lock 140.

ONO layer 164 is formed at floating gate and selects on the lock, and control sluice 170 is formed on the ONO layer 164, and control sluice is covered in floating gate 160 and selects on the lock 140.N+ source electrode and drain region 174,178 are formed in the semiconductor substrate 120.

Utilize hot electron injection method (hot electron injection), to floating gate 160, set the program of memory cell by the channel region 180 (a p type island region territory of semiconductor substrate 120) of this storage cell.Utilize the Fu Ernuohan electronics to wear method (Fower-Nordheim tunneling of electrons) then, from floating gate 160 to the source region 178, this memory cell of erasing.

This memory cell is utilized Alignment Process (self-aligned) manufacturing voluntarily, and wherein floating gate 160 defines with single shielding with a left side and the right hand edge of control sluice 170.

Another voluntarily Alignment Process be described in the 603rd～606 page of IEDM Technical Digest 1989, people such as Naruke institute principal coordinates is entitled as in the article of " A New Flash-Erase EEPROM Cell with a SidewallSelect-Gate on Its Source Side ".In the former technology, floating gate and control sluice at first form a stacked structure.Select lock to form a sidewall spacers on the sidewall that comprises floating gate and control sluice structure then.

Summary of the invention

Aim at storage organization (different pattern in these structures defines with single shielding) voluntarily by the present invention includes, yet the present invention is not limited by said structure.

In certain embodiments, a floating gate layer (for example: doped polysilicon layer) be formed on the selection lock, select to remove on the lock from least a portion by this floating gate layer.In certain embodiments, this action is finished by no light shield etching.(for example: the ONO layer) be formed on the floating gate layer, and a control sluice layer is formed on this dielectric layer, this control sluice layer is selecting to have a upwardly projecting portion on the lock to one dielectric layer.Then, another layer as: silicon nitride layer is formed on the control sluice layer, but the ledge of control sluice layer is exposed to the open air, and it deposits by a silicon nitride and subsequent cmp (CMP) is finished, and wherein CMP stops on the ledge of this control sluice layer.To the silicon nitride exposed portion of this control sluice layer of etching optionally, select to remove on the lock from least a portion up to this control sluice layer.Then, another layer is formed at the exposed portion of this control sluice layer, and in some embodiment, it is the silicon dioxide of thermosetting.Then, remove silicon nitride, to silicon dioxide optionally this control sluice layer of etching, ONO layer and floating gate layer, with definition control sluice and floating gate.

Specifically, the invention provides a kind of method of manufacturing one integrated circuit, this integrated circuit comprises a non-volatile memory cell, it comprises one first conduction lock, one second conduction lock and a conduction floating gate of insulation each other, the method comprising the steps of: (a) form this first conduction lock on the semiconductor substrate, and form a dielectric medium on a sidewall of this first conduction lock, so that this first conduction lock and the insulation of this floating gate; (b) form a FG layer on this first conduction lock, wherein this floating gate comprises the part of this FG layer; (c) remove this FG layer at least a portion of this first conduction lock certainly; (d) form one second conduction lock layer on this FG layer, so that at least a portion of this second conduction lock to be provided, this second conduction lock has a part of P1 that protrudes on this first conduction lock; (e) form a nitration case on this second conduction lock layer, this ledge P1 is exposed to the open air and do not covered fully by this nitration case; (f) this nitration case tool is optionally removed the second conduction lock layer that is positioned at this part P1, remove this second conduction lock layer at least a portion with this first conduction lock certainly; (g) form a protective layer on the vertical sidewall of this second conduction lock layer that adjoins this first conduction lock; And (h) this protective layer tool is optionally removed to this nitration case of small part, this second conduction lock layer and this FG layer.

According to the method for above-mentioned conception, wherein step (g) comprises this second conduction lock layer and another material is reacted to form this protective layer.

According to the method for above-mentioned conception, wherein this reactions steps comprises the oxidation of this second conduction lock layer.

According to the method for above-mentioned conception, wherein this reactions steps comprises the chemical reaction of this second a conduction lock layer and a metal, and follows removing of unreacted metal behind this chemical reaction.

According to the method for above-mentioned conception, wherein also comprise and remove in this first conduction first side of lock but not this nitration case on second side of this first conduction lock, this second conduction lock layer and this FG layer, this second side is with respect to this first side.

Method according to above-mentioned conception, wherein also comprise in this semiconductor substrate of this floating gate of one first regions and source on this second side of adjoining this first conduction lock that forms this internal storage location, and in this semiconductor substrate of this first conduction lock of one second regions and source of this internal storage location of formation on this first side of adjoining this first conduction lock.

According to the method for above-mentioned conception, wherein internal storage location is the part of memory cell array, and each internal storage location comprises one first conduction lock, the one second conduction lock and a floating gate of insulation each other; Wherein step (a) comprises the one or more first conduction brake cables of formation, and each brake cable provides at least a portion of each first conduction lock; Wherein each floating gate comprises at least a portion of this FG layer; Wherein step (c) removes this FG layer at least a portion of each first conduction lock; Wherein this second conduction lock layer provides at least a portion of each second conduction lock; Wherein the result of step (d) comprises a part that protrudes on each first conduction lock for this second conduction lock layer; Wherein the result of step (e) exposes to the open air on each first conduction lock for this second conduction lock layer; Wherein step (f) removes this second conduction lock layer from least a portion top of each first conduction lock; Wherein step (g) forms this protective layer on this second conduction lock layer that adjoins each first conduction lock.

The present invention is not limited to above embodiment.Further feature of the present invention will be described in down.

Description of drawings

Fig. 1 is the profile of the storage cell of a prior art.

Fig. 2 is the vertical view of the middle level structure that obtained in the internal memory manufacturing of one embodiment of the invention.

Fig. 3 is the perspective view of the internal memory of Fig. 2 in the technology.

Fig. 4～Fig. 8 is the profile of the internal memory of Fig. 2 in the technology.

Fig. 9 is the perspective view of the internal memory of Fig. 2 in the technology.

Figure 10～Figure 20 A is the profile of the internal memory of Fig. 2 in the technology.

Figure 20 B is the vertical view of the structure of Figure 20 A.

Figure 21～Figure 26 B is the profile of the internal memory of Fig. 2 in the technology.

Figure 26 C is the vertical view of the structure of Figure 26 A.

Figure 27～Figure 29 B is the profile of the internal memory of Fig. 2 in the technology.

Figure 29 C is the vertical view of the structure of Figure 29 A.

Figure 30～Figure 31 is the profile of the internal memory of Fig. 2 in the technology.

Figure 32 is the circuit diagram of the internal memory of Fig. 2.

Figure 33 is the vertical view of storage array according to an embodiment of the invention.

120: the substrate that semiconductor substrate/P mixes

130: silicon dioxide layer/dielectric layer

140: select lock/polysilicon layer/selection brake cable

150: silicon dioxide layer/floating gate dielectric layer

154:ONO layer/dielectric layer

160: floating gate/polysilicon layer

The 164:ONO layer

170: control sluice/polysilicon layer/control brake cable

174: drain region/bit line zone

178: source region/source electrode line

180: the channel region of memory cell

220: substrate isolates zone/dielectric layer/ditch oxidation layer

410: silicon dioxide layer/pad oxide

420: silicon nitride layer

220P: the jut of silicon dioxide layer

220T: isolation trenches

220.1: silicon dioxide layer

220.2: silicon dioxide layer

604:N type zone

120W:P type wellblock

710: active area

810: silicon nitride layer

1010: silicon dioxide layer

1030: silicon nitride layer

The 1510:ONO layer

1512: the internal memory neighboring area

1520: brake-pole dielectric layer/oxide layer

1512H: high voltage transistor zone

1512L: low-voltag transistor zone

1522: the wellblock

170.1: the polysilicon layer jut

170C: pothole

1710: silicon nitride/nitration case

1910: protective layer/oxide layer

2010: anti-reflecting layer

2020: photoresist layer/shielding

2502: photoresist layer

2620: photoresist layer

2720: photoresist layer

The neighboring area of 1512N:NMOS zone/NMOS

The neighboring area of 1512P:PMOS zone/PMOS

1522P:P type wellblock

1522N:N type wellblock

1522: the wellblock

2730N:NMOS transistor source/drain region

2720: photoresist layer

2820: photoresist layer

2730P:PMOS transistor source/drain region

2904: silicon dioxide layer/dielectric layer

2910: silicon nitride layer/clearance wall

2920: photoresist layer

3104: interlayer dielectric layer/insulator

3110: conductive layer/bit line

3210: memory cell

Embodiment

Here the embodiment that is narrated is in order to explain the present invention, but does not limit the present invention.The present invention is not limited to special material, treatment step or size.

Fig. 2 be according to a preferred embodiment of the present invention in, be shown in the vertical view of some features of separate-gate flash array in the technology, Fig. 3 is the figure that inspects that shows supplementary features.Each memory cell comprises a floating gate 160, a control sluice 170 and a selection lock 140.Floating gate 160, control sluice 170 and selection lock 140 are insulated from each other, and insulate with semiconductor substrate 120 (for example, monocrystalline silicon).Each control sluice 170 is that a control brake cable also is the part of label 170, extends through array in the Y direction.In certain embodiments, the Y direction is a column direction, and each control brake cable 170 provides control sluice to give row of memory cell.Different control brake cables 170 perhaps can, also perhaps cannot be electrically connected.Under control sluice, the position of each floating gate 160 is shown in Fig. 2 with a cross spider.Each selects lock 140 also is the part of label 140 for selecting brake cable, extends through array in the Y direction.Extend in directions X in substrate isolates zone 220 (an effect area of isolation).In certain embodiments, this directions X is hurdle (bit line) direction.Whole array is crossed in each substrate isolates zone 220, and each selects brake cable 140 and each control brake cable 170 to cross the whole of substrate isolates zone 220.

The longitudinal sectional drawing of follow-up icon display obtained transitional structure during internal memory is made.Section plane is shown among Fig. 2 with line X-X ', Y1-Y1 ' and Y2-Y2 '.Line X-X ' is with between the directions X process substrate isolates zone 220.Line Y1-Y1 ' passes through to select brake cable 140 with the Y direction.Line Y2-Y2 ' passes through control brake cable 170 with the Y direction.

In one embodiment, the manufacturing of internal memory is as follows: isolated substrate zone 220 is formed at the substrate 120 that P mixes with shallow trench isolation (" STI ") technology.More particularly, as shown in Figure 4 (Y1-Y1 ' section).One silicon dioxide layer 410 (pad oxide) is formed at substrate 120 with thermal oxidation or other technology, and silicon nitride layer 420 is deposited on the pad oxide 410, and silicon nitride layer 420 uses photoresistance shielding (no icon) lithographic patterning, in order to definition isolation trenches 220T.Pad oxide 410 and the opening etching of semiconductor substrate 120 by silicon nitride layer 420.As a result, isolation trenches 220T is formed on the substrate 120, and each isolation trenches 220T crosses whole memory array with directions X.

Silicon nitride layer 420 carries out timing Wet-type etching (timed wet etch), to excavate the vertical edge of silicon nitride layer from isolation trenches 220T, sees Fig. 5 (Y1-Y1 ' section).Pad oxide 410 is also excavated from irrigation canals and ditches in this step.

Thin layer of silicon dioxide 220.1 thermosettings are in the silicon face of deposition, with the edge of mild isolation trenches 220T.Then, silicon dioxide layer 220.2 utilizes high-density electric slurry technology (HDP) deposition.Silicon dioxide layer 220.2 fills up irrigation canals and ditches and covers silicon nitride layer 420 at first.Silicon dioxide layer 220.2 utilizes chemical mechanical milling method (CMP) to polish, and grinds to terminate in silicon nitride layer 420.One smooth top end surface provides in this.

At follow-up icon, among Fig. 2 and Fig. 3, silicon dioxide layer 220.1 and 220.2 is shown as an individual layer 220.

As shown in Figure 5, silicon dioxide layer 220 is projected on the substrate 120 with the amount of the thickness that is equal to silicon nitride layer 420 and combines with pad oxide 410.The jut of silicon dioxide layer 220 is presented at 220P.

Silicon nitride layer 420 is to remove (Fig. 6, Y1-Y1 ' section) to silicon dioxide layer 220 tool selectivity, and this can utilize Wet-type etching to finish (as utilizing phosphoric acid).

Alloy injects semiconductor substrate 120, to form a N type zone 604 under memory array.Alloy injects substrate simultaneously around array, to form the N type zone (no icon) that a top end surface by semiconductor substrate 120 extends to N type zone 604.These injections have been created p type wells district (P well) 120W who isolates fully and have been given storage array.N type zone 604 there is no and is shown in follow-up icon.

Silicon dioxide layer 220 carries out etching (Fig. 7, Y1-Y1 ' section).This etching comprises a horizontal direction, and makes the sidewall of silicon dioxide layer 220, excavates laterally from zone 710 (not substrate regions that occupied by irrigation canals and ditches 220T) initiatively.This etching can be first-class tropism's wet etching.The hydrofluoric acid of buffered oxide etch or dilution (DHF) etching can be used in some example.This etching will make the capacitive coupling between between floating gate and control sluice improve, and sees application on October 1st, 2002, No. the 10/262nd, 785, the U.S. patent application case of Yi-Ding, and incorporate reference in this.

The ledge 220P of silicon dioxide layer 220 there is no and etches away, and continues to protrude on the top end surface of semiconductor substrate 120.In the technology (technology of minimum feature 0.18) of 0.18 μ m, the exemplary final thickness of jut 220P is 0.12 μ m.If not point out in addition, then the exemplary 0.18 μ m technology that is of a size of.

Pad oxide 410 removes when silicon dioxide layer 220 etchings.

Silicon dioxide layer 130 thermosettings are given the selection transistor in the exposed areas of semiconductor substrate 120 so that dielectric layer to be provided.The exemplary thickness of silicon dioxide layer 130 is 120

As shown in Figure 8 (Y1-Y1 ' section), the polysilicon layer 140 of a conduction is formed on the structure with similar shape depositing operation (conformal deposition process) (for example Low Pressure Chemical Vapor Deposition " LPCVE ").Polysilicon layer 140 is filled the clearance wall between silicon dioxide layer protuberance 220P.Contact owing to be deposited on the polysilicon segment of silicon dioxide protuberance 220P sidewall, so the polysilicon layer top end surface is smooth.

Non-similar shape depositing operation (non-conformal deposition processes) is no matter be known or be about to all can utilizing of invention.If the top end surface of polysilicon layer 140 is not smooth, it is generally acknowledged that polysilicon layer 140 can be after deposition, utilize technology that oneself knows (for example, be coated with a photoresist layer in polysilicon layer 140, with same etch rate while etching photoresist layer and polysilicon layer, Remove All then until photoresist layer) planarization.The lower surface of polysilicon layer 140 is a non-flat forms, when it at the jut 220P of silicon dioxide layer dipping and heaving.

The exemplary final thickness of the polysilicon layer 140 of active area is 0.06 μ m.

Silicon nitride layer 810 is to be deposited on polysilicon layer 140 as Low Pressure Chemical Vapor Deposition (LPCVE), to an exemplary thickness 1500

If needed, a pad oxide (no icon) can be formed at polysilicon layer 140 before the silicon nitride layer deposition.This pad oxide will provide and select lock one additional protection layer when 170 etchings of control sluice polysilicon layer, and this will cooperate Figure 18 to be illustrated in down.

In some instances, the top end surface of polysilicon layer 140 and silicon nitride layer 810 is a non-flat forms.

Wafer is with photoresist layer (no icon) coating, and the photoresist layer patterning is selected brake cable 140 with definition.See the perspective view of Fig. 2 and Fig. 9, each selects brake cable 140 to extend through whole array with the Y direction, memory array how much is insensitive for the mis-alignment between the shielding of the shielding of selecting brake cable 140 between definition and definition isolation trenches 220T (Fig. 4), except may be on the border of memory array.

Silicon nitride layer 810 is by the opening etching of photoresist layer.Photoresist layer removes, and polysilicon layer 140 is etched, and it exposes to the open air with silicon nitride layer 810, and the result selects brake cable 140 to form (optionally in the example, the photoresist layer of definition silicon nitride layer 810 removes for another) after the etching of polysilicon layer 140.

Shown in Figure 10 (X-X ' section), this structure oxidation is to form silicon dioxide layer 1010 on the sidewall of selecting brake cable 140.Then, under maskless situation on the memory array, one thin similar shape silicon nitride layer 1030 depositions and anisotropy ground etching is to form clearance wall on each sidewall by selection brake cable 140, the silicon nitride layer 810 that is overlying on its top and structure that silicon dioxide layer 1010 is constituted.The formation of silicon nitride gap wall is described in, and for example, on March 12nd, 2002 was checked and approved, and No. the 6th, 355,524, people's such as H.TUAN United States Patent (USP) is dissolved in this and incorporates reference in it.

Code-pattern oxide etch (blanket oxide etch) has been removed the part that silicon dioxide layer 130 exposes to the open air.Silicon dioxide layer 150 (Figure 11, X-X ' section) thermosetting is in semiconductor substrate 120 to one ideal thickness, and for example 90

With floating gate polysilicon layer 160, being deposited on this structure as Low Pressure Chemical Vapor Deposition (LPCVD), and when deposition or the deposition back mix.Polysilicon layer 160 need have the surperficial contour adequate thickness on the top of the top end surface that makes polysilicon layer 160 and silicon nitride layer 810 at least.Especially, the top end surface of polysilicon layer 160 comprises between the regional 160T that selects 140 at lock.Zone 160T needs contour with the top end surface of silicon nitride layer 810 at least.

Polysilicon layer 160 is with chemical mechanical milling method (CMP) or other method planarization, and terminates in silicon nitride layer 810.See Figure 12 (X-X ' section), it is the same smooth with the top end surface of silicon nitride layer 810 that the top end surface of polysilicon layer 160 becomes.Many chemical mechanical milling methods that oneself knows (CMP) and lapping liquid can be avoided causing sagging (dishing) at the top end surface of polysilicon layer.

Polysilicon layer 160 etching under unshielded situation on storage array.See Figure 13 A (X-X ' section) and Figure 13 B (Y2-Y2 ' section).When this etching terminates in ditch oxidation layer 220 and exposes to the open air.Carry out suitable over etching so that polysilicon layer 160 fully the top end surface of autoxidation layer 220 remove.In certain embodiments, the final thickness of polysilicon layer 160 is 1200

Selectively, carry out the timing etching (timed etch) of an oxide layer 220,, see Figure 14 (Y2-Y2 ' section) with the top end surface of the oxide layer 220 of excavating polysilicon layer 160 lower face.The capacitive coupling between between floating gate and control is promoted in this etching meeting, sees before and states United States Patent (USP) the 6th, 355, No. 524.In the embodiment of Figure 14, oxide layer 220 protrudes on the top end surface of semiconductor substrate 120 continuously, and this represents that with 220P projection has 0.10 μ m at least.In other example, oxide layer 220 there is no and is projected on the substrate after etching.

ONO layer 1510 (Figure 15 A, X-X ' section) is formed on the structure.For example, but a silicon dioxide layer thermosetting or is 50 with high-temperature oxydation (HTO) process deposits to thickness in polysilicon layer 160

(high-temperature oxydation (HTO) is described in No. the 2002/0197888th, laid-open U.S. Patents publication number on December 26th, 2002, be dissolved in it this incorporate into reference to).Can Low Pressure Chemical Vapor Deposition to be deposited into thickness be 80 to a silicon nitride layer then

Then, can low temperature oxidation technology to be deposited into thickness be 50 to another silicon dioxide layer

Above-mentioned technology and one-tenth-value thickness 1/10 are exemplary, but do not limit the present invention.

(Figure 15 B) removes from internal memory neighboring area 1512 with silicon dioxide layer 150 for ONO layer 1510, polysilicon layer 160.Suitable brake-pole dielectric layer 1520 is formed at the periphery of semiconductor substrate 120 with traditional method.In the embodiment shown in Figure 15 B, this neighboring area comprises high voltage transistor zone 1512H and low-voltag transistor zone 1512L.The formation of brake-pole dielectric layer 1520 is as follows: silicon dioxide layer with the high temperature oxidation process thermosetting or be deposited on high voltage transistor zone 1512H and low-voltag transistor zone 1512L to thickness 140

This oxide layer is with the shielding etching, and 1512L removes from the low-voltag transistor zone.Thereafter another silicon dioxide layer with thermal oxidation be formed at low-voltag transistor zone 1512L, high voltage transistor zone 1512H to thickness be 60

As a result, the oxidated layer thickness of high voltage transistor zone 1512H is by 140

Increase to 200

The oxide layer on ONO layer 1510 (Figure 15 A) top can be in above-mentioned step, is made significantly thicker and finer and close.Selectively, the whole top oxide layer of ONO layer 1510 sandwich interlayer can be formed at periphery when forming oxidation dielectric layer 1520.

Figure 15 B also NMOS of display memory neighboring area 1512 and the wellblock 1522 of PMOS is formed at semiconductor substrate 120.The technology that can utilize oneself to know forms the wellblock before the manufacturing of oxide layer 1520, and critical voltage cloth can be injected the wellblock.

Control sluice polysilicon layer 170 (Figure 16 A, X-X ' section and Figure 16 B neighboring area) is deposited on ONO layer 1510 and dielectric layer 1520.Polysilicon layer 170 is doping (" extrinsic semiconductor (intrinsic) " is shown in Figure 16 B with " INTR ") at first.Then, with neighboring area 1512 shieldings, and polysilicon layer 170 doping N+ are in the memory array district.

The top end surface of polysilicon layer 170 and non-flat forms, polysilicon layer 170 has a protuberance 170.1 and selects brake cable 140 in each.This protuberance 170.1 will be used to define control sluice and floating gate, not have the additional lithography alignment that depends on.

Shown in Figure 16 A, pothole 170C is formed at polysilicon layer 170, between protuberance 170.1.Shown in Figure 17 A (X-X ' section), these potholes 170C fills up with some material 1710.In one embodiment, material 1710 is a silicon nitride, and it is deposited on polysilicon layer 170, and utilizes chemical mechanical milling method or other method (for example: eat-back) planarization.This memory array zone has a smooth top end surface, exposes to the open air with polysilicon layer 170.Nitration case 1710 is deposited on neighboring area (Figure 17 B) simultaneously, but in certain embodiments, polysilicon layer 170 is not exposed to periphery by the process of nitrogenize planarization.This is for having removed in periphery owing to floating gate polysilicon layer 160, and therefore, before nitration case 1710 planarizations, nitration case 1710 is low in array region in the top of periphery level height.This nitrogenize planarization process perhaps can, perhaps cannot stay nitration case 1710 in periphery.In the embodiment of Figure 17 B, nitration case 1710 there is no in the process of planarization, removes fully from periphery.

Figure 18 (X-X ' section) is seen in polysilicon layer 170 etching do not have using under the shielding nitration case 1710 tool selectivity.Polysilicon layer part 170.1 is invaded in this etching, and from each selects to remove polysilicon layer 170 to expose ONO layer 1510 to the open air on the brake cable 140 to small part.In the embodiment of Figure 18, this is etched in to expose to the open air and continues to carry out after the ONO layer, and excavating the top end surface of the polysilicon layer 170 that is positioned at ONO layer 1510 top end surface below, yet this is inessential.The polysilicon etching can stop when ONO layer one exposes to the open air.Adjoining will be in order to the width of definition control sluice and floating gate in alignment methods voluntarily in the width W 1 of the exposed portion of the polysilicon layer 170 of selecting lock 140, and this will be described in down.

In certain embodiments, the minimum thickness of polysilicon layer 170 (adjoin in select lock 140) is 0.18 μ m, and width W 1 is lower than 0.18 μ m slightly, for example: 0.155 μ m.In Figure 18, the top end surface of the exposed portion of polysilicon layer 170 is excavated.In another embodiment, polysilicon layer 170 has a smooth top end surface and spreads all over this memory array zone.

In the neighboring area (Figure 17 B), polysilicon layer 170 is by nitration case 1710 protections, so the neighboring area does not change because of the etching of polysilicon layer.If nitration case 1710 in the process of nitrogenize planarization (and Figure 17 A is illustrated in) removes in periphery, then polysilicon layer 170 can be when the polysilicon layer etching, and is protected in periphery by an additional mask (no icon).

One protective layer 1910 (seeing Figure 19 X-X ' section) is formed on the exposed portion of this polysilicon layer 170.In one embodiment, layer 1910 is by the formed silicon dioxide layer of the thermal oxidation of layer 170.One exemplary thickness of oxide layer 1910 is 500

Layer 1910 also can be a conductive metal silicide layer, and it is formed on the polysilicon layer 170 to choice of technology by silication (aiming at silication voluntarily).

As above annotate (Figure 18), adjoin in the top end surface of the polysilicon layer 170 of selecting lock 140 and hollowed out, and oxide layer 1910 is formed on this vertical sidewall that hollows out the polysilicon layer part, thereby obtain L type oxidation characteristic.This sidewall oxidation process consumes some polysilicon layer 170 under nitration case 1710.The overall width W2 (Figure 19) of the polysilicon layer part that oxidated layer 1910 covers will define the width of floating gate and control sluice, as explained below.In certain embodiments, W2 is 0.18 μ m.

As above annotate, the top end surface of polysilicon layer 170 can become smooth after the etching of Figure 18 and before oxide layer 1910 formation.In this type of embodiment, W2 approximately is equal to W1, because 1710 times less polysilicon oxidation is arranged at nitration case.

Periphery is by nitration case 1710 protections and change during this step.

One reflection coating layer (ARC) 2010 shown in Figure 20 A, flows on the wafer and through baking-curing (cured).After this step, this structure has a smooth top end surface.

Wafer covers with a photoresist layer 2020.This photoresist layer patterning is positioned at the part that each selects the oxide layer 1910 of brake cable 140 1 sides with protection.Figure 20 B (vertical view) illustrates that photoresistance shields 2020 positions, and is relevant with the pattern that is shown in Fig. 2.Photoresist layer 2020 is covered on control brake cable 170 prepositions, and exposes between the zone of 140 of the selection brake cables that adjoins, and wherein control sluice polysilicon layer 170 will be removed.The longitudinal edge of photoresistance shielding 2020 can be positioned at any position of selecting brake cable 140, and therefore accurate shielding aims at is not to be conclusive (critical) in this array region.

Photoresist layer 2020 does not hide neighboring area 1512.

Reflection coating layer (ARC) 2010 and the oxide layer 1910 that is exposed to the open air by photoresist layer 2020 removed in etching, and then removing the remainder of photoresist layer 2020 and reflection coating layer (ARC) 2010, the memory array structure of gained is shown in Figure 21 (X-X ' section).

The neighboring area is subjected to nitration case 1710 protections, and keeps shown in Figure 17 B.

Oxide layer 1910 tools are optionally removed nitration case 1710 (for example passing through wet etching), and its resulting structures is shown in Figure 22 A (X-X ' section) and Figure 22 B (neighboring area).

Then, this wafer is coated with (no icon) with a photoresist layer, and the photoresist layer patterning is to cover the neighboring area.Photoresist layer there is no the covering memory array.Polysilicon layer 170 with silicon nitride layer 1910 as shielding, in the array region etching.This etching is to silicon dioxide tool selectivity, so this etching terminates in ONO layer 1510, and its resulting structures is (X-X ' section) as shown in figure 23.

ONO layer 1510 and polysilicon layer 160 serve as that etching is carried out in shielding in array region with oxide layer 1910.ONO layer 1510, polysilicon layer 160 remove fully from the place that not oxidized layer 1910 covers, and see Figure 24 (X-X ' section).Oxide layer 1910 and

nitration case

810,1030 can partly remove when 1510 etching of ONO layer.Floating gate 160 and control brake cable 170 fully define when the end of this step, and as Fig. 2 and shown in Figure 3.The width of the top end surface of control brake cable 170 is W2, definition as above-mentioned, and relevant Reference numeral is asked for an interview Figure 19.

The internal memory of Figure 24 has a reliable lateral wall insulation, and it is on the one hand between selecting 140 at lock, on the other hand between 170 of floating gate 160 and control sluice.This insulation provides by silicon dioxide layer 1010 and silicon nitride layer 1030.With regard to this point, the internal memory in the article that the structure of Figure 24 and aforementioned Naruke etc. are shown relatively is more favourable.In the internal memory of Naruke etc., the initial stacked structure that forms of floating gate and control sluice.Then, select lock to form with as a side wall spacer.Forming a good lateral wall insulation is problematic on the stacked structure of floating gate and control sluice, because floating gate and control sluice layer have shoulder (shoulders), protrudes in outside the stacked structure.This lateral wall insulation can attenuation on shoulder.Good lateral wall insulation is formed at can be more easy on selection lock 140 sidewalls of Figure 24, and this is because select lock not to be stacked with other conductive layer.Yet the present invention is not limited to the embodiment of Figure 24, or is limited to this embodiment, wherein selects lock to there is no with other conductive layer and piles up.

Before floating gate and control sluice that formation is piled up, form earlier and select other advantage of lock to be described in down: if floating gate and control sluice pile up first formation, the active area of the etching meeting of floating gate and control sluice layer damage semiconductor substrate 120 (for example, supposing under the situation that floating gate and control sluice make with polysilicon).The damage of this active area may hinder the formation of selecting gate dielectric layer 130.

Simultaneously, in certain embodiments, selecting gate dielectric layer 130 is the silicon dioxide layer of a thermosetting, if floating gate forms earlier with control sluice, then forms the process meeting oxidation floating gate of thermal oxidation of silicon dioxide layer 130 and the edge of control sluice, and this is unwished-for.Further, in certain embodiments, silicon dioxide layer 130 can be thick than the dielectric layer 150 of floating gate, and therefore, it is preferable early forming silicon dioxide layer 130 in technology.

After the etching of polysilicon layer 160, the photoresist layer of protection neighboring area also has been removed, and the neighboring area of reservation is shown in Figure 22 B.Polysilicon layer 170 exposes to the open air and can mix in periphery.When following source/drain injects, but nmos pass transistor gate doped N-type, the PMOS transistor gate P type that can mix.

Wafer is with photoresist layer 2502 coatings (Figure 25), and this photoresist layer patterning is with definition peripheral transistor gate.Photoresist layer 2502 covering memory arrays, the polysilicon layer 170 that exposes to the open air etches away, and photoresist layer 2502 removes.

Wafer is with photoresist layer 2620 coatings, and this photoresist layer patterning is to expose source electrode line 178 (Figure 26 A, X-X ' section to the open air; And Figure 26 B, the vertical view of the array of no dielectric layer).Each source electrode line 178 passes through the memory array between 170 of two control brake cables that adjoin, and provides the source territory to give each storage cell at two row in conjunction with two control brake cables.

The aligning of photoresist layer shielding 2620 is not to be conclusive, and this is because a left side and the right hand edge of this shielding opening can be located in each selection brake cable 140 or control brake cable 170 Anywhere.

Photoresist layer 2620 covers the neighboring area.

Silicon dioxide layer 220 is by shielding 2620 zones of exposing to the open air, i.e. the zone of source electrode line 178, and etching outside isolation trenches 220T, this etching has removed oxide layer 1910, also removes the silicon dioxide layer 150 of the active area of source electrode line top.Then, the injection of source electrode line 178 (N+) utilizes identical shielding to finish.In certain embodiments, this is that high-energy, high dose inject, and it may be better than utilizing the injection (for example, this angle can be 10 ° to 30 °) of low-yield, low dosage, wide-angle, to reach the source electrode line diffusion depth of 0.1 μ m～0.2 μ m.

In an alternate embodiments, photoresistance shielding 2620 forms, and a high-octane N+ injects then, finishes before etching away silicon dioxide layer 220.Then, silicon dioxide layer 220 utilizes the identical etching outside the irrigation canals and ditches that is shielded from.Then, another low-yield N type injects and utilizes identical shielding to finish.(high-energy) is infused in irrigation canals and ditches for the first time needs to be blocked by silicon dioxide layer 220 parts at least, to avoid source electrode line 178 and N type area of isolation 604 short circuits (Fig. 6), sees above-mentioned United States Patent (USP) the 6th, 355, No. 524.

Photoresist layer 2620 removes, and wafer is with photoresist layer 2720 coating (Figure 27), and this photoresist layer patterning to be exposing whole array region to the open air, and exposes the nmos transistor region of periphery simultaneously to the open air.Figure 27 shows that one has the nmos transistor region 1512N of a p type wells district 1522P periphery, with a PMOS transistor area 1512P with a N type wellblock 1522N periphery.Wellblock 1522N, 1522P are two wellblocks of wellblock 1522, generally are shown in Figure 15.Many regional 1512N can be arranged on integrated circuit, 1512P, photoresist layer 2720 covers PMOS transistor area 1512P, carries out a N type and injects (N-), thinks that nmos pass transistor source/drain region 2730N forms the prolongation of lightly doped drain (LDD).This injects the nmos pass transistor of the periphery that mixes simultaneously.Photoresist layer 2720 can, also covering memory array not.If photoresist layer 2720 does not have the array of covering, this injection provides additional doping to give source electrode line 178, and the bit line zone 174 of also having mixed (as Figure 29 A).

Photoresist layer 2720 removes, and another photoresist layer 2820 (Figure 28) is formed at wafer.Photoresist layer 2820 patternings are to cover the transistor area 1512N and the array region of NMOS periphery.Carry out a P type and inject (P-), think PMOS source/drain region 2730P, form the prolongation of lightly doped drain, and the transistorized gate of PMOS of the periphery that mixes.

Photoresist layer 2820 removes, a thin silicon dioxide layer 2904 (Figure 29 A, X-X ' section; And Figure 29 B, the neighboring area) utilize any suitable technique to be deposited on this structure (for example, Ethoxysilane is handled (TEOS), high temperature oxidation process (HTO), rapid thermal oxidation is handled (RTO)).The exemplary thickness of one silicon dioxide layer 2904 is 200 in the silicon face of semiconductor substrate 120 and polysilicon layer 170

～300

If (for example handle with rapid thermal oxidation, RTO), then the silicon dioxide layer in the silicon nitride layer surface will become thinner to silicon dioxide layer 2904 heat deposition.

One thin layer of sin, 2910 depositions, and do not have the shielding of use and carry out anisotropic etching, on the gate of peripheral transistor, to form side wall spacer.Clearance wall 2910 is formed at storage array simultaneously.Silicon dioxide layer 2904 is as an etch stop layer, and it act as the top end surface of protection semiconductor substrate 120 and peripheral polycrystalline silicon gate pole 170.This wafer is coated with a photoresist layer 2920 (Figure 29 B).This photoresist layer patterning covering the neighboring area 1512P of PMOS, but exposes neighboring area 1512N and the memory array of NMOS.Carry out a N+ and inject, think the nmos pass transistor of periphery, create the low-doped drain structure, improve in the nmos pass transistor gate of periphery and the doping content in source electrode line zone 178, and doped bit line zone 174.Figure 29 C is the vertical view of gained memory array structure.Floating gate, control sluice and selection lock shield this injection, the therefore shielding that need not add in this array region with the silicon nitride layer that covers thereon.

Photoresist layer 2920 removes, and this wafer is with a photoresist layer 3020 coating (Figure 30), and this photoresist layer patterning to be covering NMOS neighboring area 1512N and memory array, but exposes PMOS neighboring area 1512P.Carry out a P+ and inject, think that the PMOS transistor forms low-doped structure, and increase the concentration of mixing in PMOS transistor gate.

The manufacturing of this internal memory can utilize known technology to finish.In the embodiment of Figure 31, a code-pattern SiO 2 etch (blanket silicon dioxide etch) does not remove oxide layer 2904,150 on the transistor gate of control sluice line 170, source electrode line 178, bit line zone 174 and periphery and source/drain region (being shown in Figure 31).One conductive metal silicide layer 2930 is formed on the silicide regions that exposes to the open air by aiming at silicidation technique voluntarily.Interlayer dielectric layer 3104 is deposited on this wafer.Contact window is etched in dielectric layer 3104 and exposes (only having the opening in a pairs of bit line zone 174 to be shown in Figure 31) to the open air so that be arranged in the gate and the silicide on source/drain region 2930 of control brake cable 170, source electrode line 178, bit line zone 174 and periphery.Deposition and patterning one conductive layer 3110 are to form bit line and other feature, this bit line contact bit line zone 174.If dielectric layer 3104 is a silica, then the aligning of the shielding of the contact window on the definition layer 3014 (not icon) is not for conclusive in the memory array zone, and this is owing to select lock 140 to be lived by nitration case 2910,1030 protections.

Figure 32 is the circuit diagram of an array embodiment, and this is one or non-array (NOR array), is the type of No. the 6th, 355,524, above-mentioned United States Patent (USP).Each bit line 3110 is shared by the memory cell 3210 on two hurdles.One memory cell 3210 can be utilized the hot electron injection method, comes setting program from the channel region of the memory cell p type island region territory of the semiconductor substrate 120 of selecting the lock below (floating gate of memory cell with) to floating gate 160.This memory cell can be utilized Fu Ernuohan electrons tunnel (Fowler-Nordheim tunneling ofelectrons), is erased by floating gate 160 to source electrode line zone 178 or channel region.

The present invention is not restricted to this and erases or program technic, or is somebody's turn to do or non-storage array (NOR array).The present invention is not restricted to above-mentioned array construction.For example, source electrode line can form from one deck, and this layer is covered in semiconductor substrate 120, and contact source electrode line substrate regions 178; Source electrode line need not pass through isolation trenches.Simultaneously, whole array need not crossed in substrate isolates zone 220 yet.As Figure 33, the substrate isolates zone is blocked at source electrode line 178, and dielectric layer 220 does not need to carry out etching outside irrigation canals and ditches before source electrode line mixes.The shallow trench isolation method can other technology form and can location oxidation of silicon process (LOCOS) or other partition method replace, the method can be that oneself knows maybe will invent.With reference to the 6th, 355, No. 524 United States Patent (USP)s that equal as Tuan to check and approve on March 12nd, 2002; Yi Ding is in the 10/262nd, No. 785 U.S. patent application case of application on October 1st, 2002; C.Hsiao is in the 10/266th, No. 378 U.S. patent application case of application on October 7th, 2002, and it all incorporates reference at this.The present invention can be applicable to multilayer (multi-level) element memory (unit in internal memory can store the multi-layer information position).Other special point that the present invention is not restricted to any special processing step, material or is described in.The present invention is not restricted to lightly doped drain or other peripheral structure.

The present invention must be thought by the personage Ren Shi craftsman who is familiar with this skill, however the protection range of neither disengaging claims.

Claims

1. method of making an integrated circuit, this integrated circuit comprises a non-volatile memory cell, and it comprises one first conduction lock, one second conduction lock and a conduction floating gate of insulation each other, and the method comprising the steps of:

(a) form this first conduction lock on the semiconductor substrate, and form a dielectric medium on a sidewall of this first conduction lock, so that this first conduction lock and the insulation of this floating gate;

(b) form a FG layer on this first conduction lock, wherein this floating gate comprises the part of this FG layer;

(c) remove this FG layer at least a portion of this first conduction lock certainly;

(d) form one second conduction lock layer on this FG layer, so that at least a portion of this second conduction lock to be provided, this second conduction lock has a part of P1 that protrudes on this first conduction lock;

(e) form a nitration case on this second conduction lock layer, this ledge P1 is exposed to the open air and do not covered fully by this nitration case;

(f) this nitration case tool is optionally removed the second conduction lock layer that is positioned at this part P1, remove this second conduction lock layer at least a portion with this first conduction lock certainly;

(g) form a protective layer on the vertical sidewall of this second conduction lock layer that adjoins this first conduction lock; And

(h) this protective layer tool is optionally removed to this nitration case of small part, this second conduction lock layer and this FG layer.

2. the method for claim 1 is characterized in that, step (g) comprises makes this second conduction lock layer and oxygen reaction to form this protective layer.

3. method as claimed in claim 2 is characterized in that, this reactions steps comprises the oxidation of this second conduction lock layer.

4. method as claimed in claim 2 is characterized in that, this reactions steps comprises the chemical reaction of this second a conduction lock layer and a metal, and follows removing of unreacted metal behind this chemical reaction.

5. the method for claim 1 is characterized in that, also comprises to remove in this first conduction first side of lock but not this nitration case on second side of this first conduction lock, this second conduction lock layer and this FG layer, and this second side is with respect to this first side.

6. method as claimed in claim 5, it is characterized in that, also comprise in this semiconductor substrate of this floating gate of one first regions and source on this second side of adjoining this first conduction lock that forms this internal storage location, and in this semiconductor substrate of this first conduction lock of one second regions and source of this internal storage location of formation on this first side of adjoining this first conduction lock.

7. the method for claim 1 is characterized in that, this internal storage location is the part of memory cell array, and each internal storage location comprises one first conduction lock, the one second conduction lock and a floating gate of insulation each other,

Wherein step (a) comprises the one or more first conduction brake cables of formation, and each brake cable provides at least a portion of each first conduction lock;

Wherein each floating gate comprises at least a portion of this FG layer;

Wherein step (c) removes this FG layer at least a portion of each first conduction lock;

Wherein this second conduction lock layer provides at least a portion of each second conduction lock;

Wherein the result of step (d) comprises a part that protrudes on each first conduction lock for this second conduction lock layer;

Wherein the result of step (e) exposes to the open air on each first conduction lock for this second conduction lock layer;

Wherein step (f) removes this second conduction lock layer from least a portion top of each first conduction lock;

Wherein step (g) forms this protective layer on this second conduction lock layer that adjoins each first conduction lock.