CN100401528C - 具有与应变半导体基片形成肖特基或肖特基类接触的源极和/或漏极的场效应晶体管 - Google Patents

具有与应变半导体基片形成肖特基或肖特基类接触的源极和/或漏极的场效应晶体管 Download PDF

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CN100401528C
CN100401528C CNB038025485A CN03802548A CN100401528C CN 100401528 C CN100401528 C CN 100401528C CN B038025485 A CNB038025485 A CN B038025485A CN 03802548 A CN03802548 A CN 03802548A CN 100401528 C CN100401528 C CN 100401528C
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schottky
strained semiconductor
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CN1620729A (zh
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J·P·斯尼的
J·M·拉森
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Spinnaker Semiconductor Inc
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Abstract

本发明是一种场效应晶体管,它具有应变半导体基片和肖特基势垒源电极和漏电极,以及用于制造晶体管的方法。肖特基势垒场效应晶体管的大量电荷载流子输运特性最小化了载流子表面散射,与常规装置相比,这使得应变基片提供这种装置中改善了的功率和速度性能特性。

Description

具有与应变半导体基片形成肖特基或肖特基类接触的源极和/或漏极的场效应晶体管
相关申请的对照
本申请要求2002年1月23日提交的美国临时专利申请60/351114、2002年1月25日提交的美国临时专利申请60/319098以及2002年5月16日提交的美国临时专利申请60/381320的优先权,在此全文并入以供参考。
发明背景
本发明涉及用于调整电流的装置,并具有对集成电路(IC)环境中这些装置制造的特殊应用。尤其是,它涉及具有肖特基势垒源极和/或漏极的用于调整电流的晶体管。
图1示出了本技术领域中已知的一种场效应晶体管(FET),金属氧化物半导体场效应晶体管(MOSFET)。如图所示,MOSFET装置100通常包括硅基片110、由沟道区140分开的掺杂杂质的源极120和掺杂杂质的漏极130。在沟道区140顶上的是绝缘层150,它通常由氧化硅制成。由导电材料制成的栅电极160设置在绝缘层150上。绝缘层170通常围绕栅电极160。场氧化物(field oxide)180使得装置100相互电绝缘。在将合适的电压Vg施加到栅电极160时,电流经过沟道区140在源极120和漏极130之间流动。该电流被称作驱动电流,或者Id。
电流调整装置的设计中的一种考虑是电荷载流子迁移率或者是电荷载流子(即,电子或空穴)在沟道区140中穿过基片晶格的容易性。由常规MOSFET理论,驱动电流与载流子迁移率线性成比例。具有较高电荷载流子迁移率的沟道区140允许电荷载流子在源极120和漏极130之间以较少的时间行进,并在载流子传输过程中消耗较少能量。一种用于增加沟道区140的电荷载流子迁移率的已知技术是采用应变基片。例如,与非应变硅相比,应变硅中电子和空穴的迁移率可以分别提升约二和十倍。(M.V.Fischetti,S.E.Laux,Journal of Applied Physics(应用物理杂志),vol80no.4,1996年8月15日,pp.2234-52)。结果,期望具有应变硅沟道区140的MOSFET装置表明优于常规非应变硅装置的功率和速度性能特性。
用于制造MOSFET装置的另一种已知基片是绝缘体上外延硅(SOT)基片。这种半导体基片包括埋入的氧化层以降低源极到漏极的泄漏电流和寄生电容。现有技术包括具有应变SOI层的半导体基片上MOSFET装置的制造(B.Metzger,″Silicon Takesthe Strain for RF Applications(硅为了RF应用采用应变),″CompoundSemiconductor(化合物半导体),vol 7,no7,2001年8月;T.Mizuno,“Design forScaled Thin Film Strained-SOI CMOS Devices with Higher Carrier Mobility(用于具有高载流子迁移率的成比例薄膜应变SOI CMOS装置的设计),”IEDMProceedings,2002年12月,p.31。)
但是,具有杂质掺杂的源极和漏极以及应变硅沟道的MOSFET的实验结果示出,这些装置不能完全地从载流子迁移率的改善中得益。例如,在一项研究中,70%的电子迁移率改善仅引起35%的驱动电流改善。(K.Rim,S.Koester,M.Hargrove,J.Chu,P.M.Mooney,J.Ott,T.Kanarsky,P.Ronsheim,M.Ieong,A.Grill,H.-S.P.Wong,Proceedings of the 2001 IEEE VLSI Symposium,Kyoto,Japan(2001).)因为驱动电流与迁移率线性地成比例,驱动电流的35%的净提升表示对于该实例,电子的有效迁移率仅改善了35%。
本技术领域内需要一种FET,它具有应变基片,呈现有效迁移率的改善,以及更接近载流子迁移率改善的驱动电流改善。
发明概述
在一个实施例中,本发明是FET,它具有肖特基势垒源极和/或漏极以及应变半导体基片。在该实施例中,装置包括应变半导体基片。源电极和漏电极与应变基片接触,且至少一个电极与基片形成肖特基或肖特基类接触。源电极和漏电极由沟道分开。绝缘层置于沟道上的应变基片上。栅电极置于绝缘层上。
在另一个实施例中,本发明是一种在应变半导体基片上制造肖特基势垒FET的方法。在该实施例中,该方法包括提供应变半导体基片。它进一步包括提供与应变基片接触的电绝缘层。该方法还包括在绝缘层上提供栅电极,从而暴露邻近栅电极的一个或多个区域上的基片。该方法还包括沉积金属薄膜和使金属与暴露的应变基片反应,从而在基片上形成肖特基或肖特基类源电极和漏电极。
虽然揭示了多个实施例,但通过以下的详细描述,本发明的其它实施例也是本技术领域内熟练技术人员显而易见的,以下描述示出并描述了本发明的说明性实施例。如将被实现的,本发明能在各种明显的方面中修改,而不背离本发明的精神和范围。因此,附图和详细描述被认为是说明性的而非限制性的。
附图概述
图1是现有技术已知的金属氧化物半导体场效应晶体管(MOSFET)的剖视图。
图2是根据本发明实施例的具有应变基片的肖特基势垒场效应晶体管(FET)的剖视图。
图3是示出根据本发明一个实施例的应变肖特基势垒FET制造方法的流程图。
具体实施方式
图2示出肖特基势垒FET装置200。装置200包括半导体基片210,其中形成了由沟道240分开的源极220和漏极225。基片210的应变的。在一个实施例中,基片由应变硅构成。在另一个实施例中,使用了其它应变半导体材料。例如,在一个实施例中,在应变SOI基片上制造该装置。该实施例提供了改善载流子迁移率以及降低源极到漏极泄漏和寄生电容耦合的双重优点。
在一个实施例中,源极220或者漏极225(或者这两者)部分或全部由金属硅化物组成。因为源极220和/或漏极225部分由金属组成,所以它们与基片210形成肖特基接触或者肖特基类区域230、235。“肖特基接触”由金属和半导体之间的接触限定,而“肖特基类区域”是由半导体和金属附近形成的区域。可以通过从金属硅化物形成源极220或漏极225来形成肖特基接触或肖特基类区域230、235。在本发明的一个实施例中,源极220或漏极225(或者这两者)部分或全部由硅化铂、硅化钯、硅化铱或者稀土元素的硅化物组成。
肖特基接触或肖特基类区域230、235位于源极220和漏极225之间形成的沟道区240附近的区域中。在本发明的一个实施例中,用常规非均匀掺杂剖面(profile)将沟道区240杂质掺杂,诸如晕植入(halo implant)。在另一个实施例中,掺杂剖面在垂直方向上显著改变并通常在横向上恒定,如共同转让的美国专利6303479B1(479专利)和美国专利6495882(882专利)所描述的,在此全文并入以供参考。对于本发明,装置中使用的特殊掺杂剖面不是关键性的。
绝缘层250置于沟道区240上。绝缘层250由诸如氧化硅的材料或者任何其它电绝缘材料构成。在本发明的一个实施例中,具有高介电常数(即,高K)的材料被用作绝缘层250。高K材料的实例是那些具有比氧化硅的介电常数更大的介电常数的材料,例如包括诸如TiO2的金属氧化物。结合肖特基势垒装置使用高K栅极绝缘层将引起驱动电流的附加改善,如2001年8月10日提交的共同待批的美国专利申请No.09/928124和09/928163中所说明的,在此全文并入以供参考。另一个实施例是应变SOI基片上制造的肖特基势垒FET并包括高K栅极绝缘层。本发明的另一个实施例包括高K栅极绝缘层和通常恒定的横向掺杂剖面(如479专利中阐述的),结合应变硅,肖特基势垒装置。又一个实施例是应变SOI基片上制造的肖特基势垒装置,该应变SOI基片包括高K栅极绝缘层,以及通常恒定的横向掺杂剖面,如479专利中阐述的。
栅电极260置于绝缘层250上,而薄绝缘层270设置在栅电极260的一个或多个栅极侧壁上。栅电极260可以由多晶硅、金属或者任何导电材料掺杂。场氧化物280使装置相互电绝缘。
本发明的原理可应用于本技术领域内已知的各种应变半导体基片上构建的装置中。但是,通过实例,根据本发明的一个实施例,应变半导体如下构建。诸如硅的第一应变半导体层210沉积在诸如硅锗的第二层205上,从而第一应变半导体层210和第二层205之间的晶格失配引起第一层210中的应变。在一个实施例中,第二层205是薄膜。在另一个实施例中,薄膜205沉积在诸如硅的基片215上。本发明的其它实施例针对其它已知应变硅基片上构建的肖特基势垒装置。
常规FET必须是表面传导装置。如图1所示,载流子165离开源极120并横穿沟道区140,在这段时间内载流子165经受由基片110和栅极绝缘层150之间的接触平面限定的界面155的强吸引。由于界面155的粗糙,载流子165通常经受许多表面散射作用。表面散射现象直接降低沟道区140中载流子的迁移率,这导致了较低的有效载流子迁移率。界面155处电荷载流子165的表面散射造成使用应变硅基片的常规FET性能改善的显著不足。
另一方面,在肖特基势垒FET装置200中,载流子290在与金属源极220的表面垂直的起始方向上被从源极220场致发射。它们主要在块硅中横穿的沟道240,而不沿应变基片210和绝缘氧化物250之间的接触平面所限定的界面255。因此,载流子290经受很少的由界面255处的表面粗糙引起的散射作用,使得对于块硅中观察到的电子和空穴的有效载流子迁移率改善分别更接近于2倍和10倍的改善。源极220和漏极225之间的距离被表示为沟道长度245。有效载流子迁移率的改善随着装置200的沟道长度245的降低而增加。
图3示出根据本发明一个实施例的肖特基势垒FET的制造方法。如图3所示,该方法始于被应变的硅基片(块302)。生长薄屏蔽(screen)氧化物(在一个实施例中,约200埃)以便用作植入掩模(块304)。随后通过屏蔽氧化物将合适的沟道掺杂物种类(例如分别用作P型和N型的砷和硼)离子植入到硅中的预定深度(块306)。
随后,将屏蔽氧化物除去,生长薄栅极氧化物(在一个实施例中,约35埃)(块308)。在栅极氧化物生长后紧接着就地掺杂的硅膜(块310)。该膜由例如用于N型装置的磷和用于P型装置的硼高浓度掺杂。使用平版印刷技术和对氧化物来说高度选择性的硅蚀刻,将栅电极形成图案(块312)。随后,薄氧化物(在一个实施例中,约100埃)被热生长于硅栅电极的顶面和侧壁上(块314)。随后,各向异性蚀刻被用于除去水平面上的氧化物层(因此将硅暴露出),同时将其保留在垂直面上(块316)。在这些步骤之后,形成侧壁氧化物,栅电极中和装置的沟道区中的掺杂物都被电激活。
接着,合适的金属(例如,用于P型装置的铂和用于N型装置的铒)被沉积在所有暴露的表面上用作覆盖层(在一个实施例中,约400埃)(块318)。随后,在特定时间内以特定温度将晶片退火,从而在金属与硅直接接触的的位置处,产生化学反应,将金属转换成金属硅化物(块320)。例如,在一个实施例中,在少于约60分钟的时间内以约400℃和约500℃之间的最大温度形成硅化铂。在另一个实施例中,在少于约1分钟的时间内以约400℃和约600℃之间的最大温度形成硅化铒。与非硅表面直接接触的金属不受影响。随后,湿化学蚀刻(用于铂的王水,用于铒的HNO3)被用于除去未反应的金属,同时使得金属硅化物不受影响(块322)。现在,完成了应变肖特基势垒FET装置并准备电接触到栅极、源极和漏极。
必须通过具有超过800C的温度的处理形成常规FET的源电极和漏电极。本技术领域中已知,高温制造步骤,即采用800℃以上的温度的步骤,会改变和/或劣化用于改善FET装置性能的新材料的属性。新材料的实例包括应变半导体基片和高K栅极绝缘体。例如,以高温处理应变半导体基片会松弛(relax)应变层,从而降低应变半导体基片中电荷载流子迁移率的改善。
另一方面,如2002年5月16日提交的美国临时专利申请60/381320中说明的,在肖特基势垒FET制造过程期间,通过具有比常规杂质掺杂的源极和漏极MOSFET装置制造过程中使用的温度小的温度的硅化物反应过程形成源电极和漏电极。更具体地,用于形成本发明的肖特基或肖特基类源极和漏极区的硅化物反应步骤可以是小于800℃,如以上详细说明的。因此,可以将应变硅基片和高K栅极绝缘体与肖特基势垒FET制造过程结合,而不劣化应变硅和/或高K栅极绝缘体的属性。
该过程仅仅是实现应变、金属源极/漏极肖特基FET装置的一种可能方法。本技术领域内熟练的技术人员将理解,存在很多其它变型和可选方案。例如,所述过程中的各种步骤可以由本技术领域内已知的等效步骤代替。同样,各种步骤中的一个或多个可以从制造过程中省去。在本发明的一个实施例中,制造方法包括应变硅基片的制造。如以上进一步描述的,在一个实例性实施例中,这是通过在具有大晶格结构的材料(诸如硅锗)的层上沉积硅层来实现的。随后,以上述方式处理该应变硅基片。用于制造应变硅基片的许多其它技术是本技术领域内已知的并可以结合本发明的教导使用。例如,在一个实施例中,在氧化物绝缘体上制造应变硅基片,形成应变SOI基片,如化合物半导体(Compound Semiconductor)文章中所描述的。
通过使用本发明的技术,可以充分改善诸如FET的晶体管的功率和速度性能。虽然已参考较佳实施例描述了本发明,但本技术领域内的熟练技术人员将理解,可以在形式和细节上进行改变而不背离本发明的精神和范围。例如,虽然以参考FET装置描述了许多实施例,但其它晶体管型装置也可以采用本发明的技术。
所有上述参考都在此全文并入以供参考。虽然已参考较佳实施例描述了本发明,但本技术领域内熟练的技术人员可以理解,可以在形式和细节上进行改变而不背离本发明的精神和范围。

Claims (35)

1.一种用于调整电流的装置,其特征在于,所述装置包括:
应变半导体基片;
栅极,它位于所述应变半导体基片上;以及
源极和漏极,它们与所述应变半导体基片接触,源极和漏极中的至少一个与应变半导体基片形成肖特基或肖特基类接触,所述源极和漏极由沟道隔开。
2.如权利要求1所述的装置,其特征在于,所述源极和漏极由选自以下的材料构成:硅化铂、硅化钯或硅化铱。
3.如权利要求1所述的装置,其特征在于,所述源极和漏极由选自以下的材料构成:稀土硅化物。
4.如权利要求1所述的装置,其特征在于,所述源极和漏极中的至少一个至少在靠近沟道的区域中与应变半导体基片形成肖特基或肖特基类接触。
5.如权利要求1所述的装置,其特征在于,源极和漏极中的至少一个与应变半导体基片之间的整个界面与应变半导体基片形成肖特基接触或肖特基类区域。
6.如权利要求1所述的装置,其特征在于,所述沟道具有沟道掺杂物。
7.如权利要求6所述的装置,其特征在于,所述沟道掺杂物浓度在垂直方向上显著变化而在横向上是大体恒定的。
8.如权利要求6所述的装置,其特征在于,所述沟道掺杂物选自:砷、磷、锑、硼、铟或镓。
9.如权利要求1或7所述的装置,其特征在于,所述沟道长度小于或等于100nm。
10.如权利要求1所述的装置,其特征在于,所述栅极包括:
栅极绝缘体,它包括置于应变半导体基片上的电绝缘层;以及
所述绝缘层上的导电膜。
11.如权利要求10所述的装置,其特征在于,所述栅极的至少一个侧壁上设置有侧壁绝缘层。
12.如权利要求10所述的装置,其特征在于,所述栅极绝缘体具有大于4.0的介电常数。
13.如权利要求10所述的装置,其特征在于,所述栅极绝缘体由选自以下的材料构成:金属氧化物。
14.如权利要求12所述的装置,其特征在于,所述沟道具有沟道掺杂物。
15.如权利要求14所述的装置,其特征在于,沟道掺杂物浓度在垂直方向上显著改变而在横向上是大体恒定的。
16.如权利要求1或14所述的装置,其特征在于,所述应变半导体基片是应变SOI基片。
17.如权利要求1所述的装置,其特征在于,所述装置是MOSFET。
18.一种用于调整电流的装置的制造方法,其特征在于,所述方法包括:
提供应变半导体基片;
在所述应变半导体基片上提供栅极;以及
提供与应变半导体基片接触的源极和漏极,源极和漏极中的至少一个与应变半导体基片形成肖特基或肖特基类接触,所述源极和漏极由沟道分开。
19.如权利要求18所述的方法,其特征在于,所述源极和漏极由选自以下的材料构成:硅化铂、硅化钯或硅化铱。
20.如权利要求18所述的方法,其特征在于,所述源极和漏极由选自以下的材料构成:稀土硅化物。
21.如权利要求18所述的方法,其特征在于,所述源极和漏极中的至少一个至少在靠近沟道的区域中与应变半导体基片形成肖特基或肖特基类接触。
22.如权利要求18所述的方法,其特征在于,所述源极和漏极中的至少一个与应变半导体基片之间的整个界面与应变半导体基片形成肖特基接触或肖特基类区域。
23.如权利要求18所述的方法,其特征在于,还包括提供沟道掺杂物的步骤。
24.如权利要求23所述的方法,其特征在于,还包括提供沟道掺杂物,从而掺杂物浓度在垂直方向上显著变化而在横向上大体是恒定的。
25.如权利要求23所述的方法,其特征在于,所述沟道掺杂物是选自:砷、磷、锑、硼、铟或镓。
26.如权利要求18或24所述的方法,其特征在于,所述沟道长度小于或等于100nm。
27.如权利要求18所述的方法,其特征在于,通过以下步骤提供栅极:
提供栅极绝缘体,它包括应变半导体基片上的电绝缘层;
在绝缘层上提供导电膜;
将导电膜形成图案并蚀刻,以便形成栅极;以及
通过在栅极的至少一个侧壁上设置至少一个侧壁绝缘层形成栅极侧壁隔离物。
28.如权利要求27所述的方法,其特征在于,所述栅极绝缘体具有大于4.0的介电常数。
29.如权利要求27所述的方法,其特征在于,所述栅极绝缘体选自以下材料:金属氧化物。
30.如权利要求28所述的方法,其特征在于,进一步包括提供沟道掺杂物的步骤。
31.如权利要求30所述的方法,其特征在于,还包括提供沟道掺杂物的步骤,从而掺杂物浓度在垂直方向上显著改变而在横向上大体是恒定的。
32.如权利要求18或30所述的方法,其特征在于,所述应变半导体基片是应变SOI基片。
33.如权利要求18所述的方法,其特征在于,所述装置是MOSFET。
34.如权利要求18或27所述的方法,其特征在于,还包括以下步骤:
将邻近栅极的至少一部分的应变半导体基片暴露;
在应变半导体基片上沉积金属薄膜;以及
使金属与暴露部分反应,从而肖特基或肖特基类源极和漏极形成于应变半导体基片的暴露部分上。
35.如权利要求34所述的方法,其特征在于,采用具有小于800℃的最大温度的退火形成所述源极和漏极。
CNB038025485A 2002-01-23 2003-01-15 具有与应变半导体基片形成肖特基或肖特基类接触的源极和/或漏极的场效应晶体管 Expired - Fee Related CN100401528C (zh)

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