CN100409428C - Non-volatile memory, its production and operation - Google Patents
Non-volatile memory, its production and operation Download PDFInfo
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- CN100409428C CN100409428C CNB2005100679136A CN200510067913A CN100409428C CN 100409428 C CN100409428 C CN 100409428C CN B2005100679136 A CNB2005100679136 A CN B2005100679136A CN 200510067913 A CN200510067913 A CN 200510067913A CN 100409428 C CN100409428 C CN 100409428C
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Abstract
The present invention relates to a nonvolatile memory, and a manufacture method and an operation method thereof. The production method of the nonvolatile memory comprises the steps that a stacking structure is formed on a substrate firstly, and the stacking structure comprises a gate dielectric layer ay lower layer and a control gate above the gate dielectric layer; next, a first dielectric layer, a second dielectric layer and a third dielectric layer are respectively formed on the top and the side wall of the stacking structure and an exposed base; finally, a charge storage layer is covered on the top and the side wall of the stacking structure, and a pair of auxiliary gates are formed on the base at both sides of the charge storage layer, wherein a gap exists between each auxiliary gate and the charge storage layer.
Description
Technical field
The present invention relates to a kind of memory component and manufacture method thereof and method of operation, particularly relate to a kind of nonvolatile memory and manufacture method thereof and method of operation.
Background technology
Nonvolatile memory is owing to have and can repeatedly carry out the actions such as depositing in, read, wipe of data, and the data that deposits in the advantage that also can not disappear after outage.Therefore, become PC and electronic equipment a kind of non-volatile memory device of extensively adopting.
Typical non-volatile memory device is to make floating grid (FloatingGate) and the control grid (Control Gate) that is positioned at the floating grid top with doped polycrystalline silicon.And floating grid and control are to be separated by with gate dielectric layer between the grid, and between floating grid and substrate being that tunneling layer is separated by.In addition, more there are source area and drain region to be configured in the control grid substrate on two sides.
When memory being write the operation of (Write) data, be by applying bias voltage, so that electronics injects floating grid in control grid, source area and drain region.During data in reading memory, be on the control grid, to apply operating voltage, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel) at this moment, and is used as the foundation of interpretation data value for " 0 " or " 1 " by the ON/OFF of this passage.When memory carry out data wipe (Erase) time, it is relative current potential raising with substrate, source area, drain region or control grid, utilizing tunneling effect to make electronics pass tunneling layer and to drain into (being Substrate Erase) in the substrate, or pass gate dielectric layer and drain in the control grid by floating grid.
Summary of the invention
The objective of the invention is to, a kind of manufacture method of nonvolatile memory of new structure is provided, technical problem to be solved is to make it can simplify processing procedure, thereby reduces the cost expenditure, thereby is suitable for practicality more.
Another object of the present invention is to, a kind of manufacture method of new nonvolatile memory is provided, technical problem to be solved is to make it can simplify processing procedure, thereby reduces the cost expenditure, thereby is suitable for practicality more.
A further object of the present invention is, a kind of nonvolatile memory is provided, and technical problem to be solved is to make its integration that element can be provided, thereby is suitable for practicality more.
An also purpose of the present invention is, a kind of method of operation of nonvolatile memory is provided, and technical problem to be solved is to make it can reduce the required voltage of control grid, thereby is suitable for practicality more, and has the value on the industry.
The present invention proposes a kind of manufacture method of nonvolatile memory, and the method is to form stacked structure prior to substrate, and this stacked structure comprises the gate dielectric and the control grid that is positioned at the gate dielectric top of lower floor.Then, in the top of stacked structure, sidewall and exposed substrate, form first dielectric layer, second dielectric layer and the 3rd dielectric layer respectively.Afterwards, in the top of stacked structure and sidewall cover electric charge storage layer, and on the electric charge storage layer substrate on two sides, form auxiliary grid, wherein between each auxiliary grid and the electric charge storage layer at a distance of a gap.
The present invention proposes the manufacture method of another kind of nonvolatile memory, and the method is to form stacked structure prior to substrate, and this stacked structure is gate dielectric, control grid and dielectric stack lamination by substrate in regular turn.Then, in substrate, form first dielectric materials layer and second dielectric materials layer, cover stacked structure and substrate.Afterwards, the sidewall in stacked structure forms a pair of composite dielectric clearance wall.Then, in substrate, form the 3rd dielectric materials layer, cover stacked structure, composite dielectric clearance wall and substrate.Continue it, in the top of stacked structure and sidewall cover electric charge storage layer, and on this electric charge storage layer substrate on two sides, form a pair of auxiliary grid, wherein between each auxiliary grid and the electric charge storage layer at a distance of a gap.
The present invention proposes a kind of nonvolatile memory, and it is made of substrate, stacked structure, electric charge storage layer, first dielectric layer, second dielectric layer, the 3rd dielectric layer, a pair of auxiliary grid and the 4th dielectric layer.Wherein, stacked structure is configured in the substrate, and this stacked structure comprises the gate dielectric and position control grid thereon of lower floor.Electric charge storage layer covers stacked structure top and sidewall.First dielectric layer is configured between stacked structure top and the electric charge storage layer.Second dielectric layer is configured between stacked structure sidewall and the electric charge storage layer.The 3rd dielectric layer is configured between electric charge storage layer and the substrate.Auxiliary grid is configured on the stacked structure substrate on two sides, and with electric charge storage layer at a distance of a gap.The 4th dielectric layer is configured between auxiliary grid and the substrate.
According to the described nonvolatile memory of preferred embodiment of the present invention or its manufacture method, the material of above-mentioned electric charge storage layer for example is polysilicon, silicon nitride or other high dielectric constant materials.
According to the described nonvolatile memory of preferred embodiment of the present invention or its manufacture method, above-mentioned gate dielectric, first dielectric layer or second dielectric layer are the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
Because the present invention is with the usefulness of formed auxiliary grid as bit line, and apply the voltage of appropriateness in auxiliary grid, can make the substrate of its below become the source area or the drain region of counter-rotating, so the size that can effectively dwindle memory component, thereby the element integration improved.
The present invention proposes a kind of method of operation of nonvolatile memory, be suitable for above-mentioned nonvolatile memory, this method of operation comprises carries out one first programming, apply first voltage in the control grid, apply second voltage and make the substrate that is positioned at first auxiliary grid below form the drain electrode reversal zone in first auxiliary grid, apply tertiary voltage in this drain electrode reversal zone, and setting second auxiliary grid becomes it to float, wherein magnitude of voltage by little to being tertiary voltage greatly in regular turn, second voltage and first voltage are entered in the electric charge storage layer of close drain electrode reversal zone by the drain electrode reversal zone so that electronics is worn tunnel by FN.
Method of operation according to the described nonvolatile memory of preferred embodiment of the present invention, perhaps can comprise when carrying out one second programming, apply the 4th voltage in the control grid, apply the 5th voltage in first auxiliary grid and second auxiliary grid, and make the substrate that is positioned at first auxiliary grid and second auxiliary grid below form drain electrode reversal zone and source electrode reversal zone respectively, apply the 6th voltage in this drain electrode reversal zone, apply the 7th voltage in this source electrode reversal zone, wherein magnitude of voltage by little to being the 7th voltage greatly in regular turn, the 6th voltage, the 4th voltage and the 5th voltage are so that electronics is entered in this electric charge storage layer of close drain electrode reversal zone by the source electrode reversal zone by channel hot electron effect (CHE).
Method of operation according to the described nonvolatile memory of preferred embodiment of the present invention, wherein when wiping, apply the 8th voltage in the control grid, apply the 9th voltage and make the substrate that is positioned at second auxiliary grid below form the source electrode reversal zone in second auxiliary grid, apply the tenth voltage in this source electrode reversal zone, and setting first auxiliary grid becomes it to float, wherein magnitude of voltage by little to being the tenth voltage, the 9th voltage and the 8th voltage greatly in regular turn, so that electronics is worn tunnel by entering the source electrode reversal zone in the close electric charge storage layer of source electrode reversal zone by FN.
Method of operation according to the described nonvolatile memory of preferred embodiment of the present invention, wherein when reading, apply the 11 voltage in the control grid, apply the 12 voltage in first auxiliary grid and second auxiliary grid, and make the substrate that is positioned at first auxiliary grid and second auxiliary grid below form drain electrode reversal zone and source electrode reversal zone respectively, apply the 13 voltage in this drain electrode reversal zone, apply the 14 voltage in this source electrode reversal zone, wherein magnitude of voltage by little to being the 14 voltage greatly in regular turn, the 13 voltage, the 11 voltage and the 12 voltage are to read the position that is stored in this electric charge storage layer.
Because the present invention is made in electric charge storage layer on the control grid, therefore can solve when carrying out memory erase, the problem of over-erasure, thus improve the element reliability.And, because therefore the close together between control grid and the substrate is controlled the required voltage of grid and can be reduced.
The present invention compared with prior art has tangible advantage and beneficial effect.Via as can be known above-mentioned, the invention relates to a kind of nonvolatile memory and manufacture method thereof and method of operation.The manufacture method of this nonvolatile memory is to form stacked structure prior to substrate, and this stacked structure comprises the gate dielectric and the control grid that is positioned at the gate dielectric top of lower floor.Then, in the top of stacked structure, sidewall and exposed substrate, form first dielectric layer, second dielectric layer and the 3rd dielectric layer respectively.Afterwards, in the top of stacked structure and sidewall cover electric charge storage layer, and on the electric charge storage layer substrate on two sides, form a pair of auxiliary grid, wherein between each auxiliary grid and the electric charge storage layer at a distance of a gap.
By technique scheme, nonvolatile memory of the present invention and manufacture method thereof and method of operation have following advantage at least:
Since the present invention with the usefulness of formed auxiliary grid as bit line, and apply the voltage of appropriateness in auxiliary grid, can make the substrate of its below become the source area or the drain region of counter-rotating, so the size that can effectively dwindle memory component, thereby the element integration improved.
2. because the present invention is disposed at electric charge storage layer on the control grid, therefore can solve when carrying out memory erase, the problem of over-erasure, thus improve the element reliability.
3. owing to the close together between its control grid of nonvolatile memory of the present invention and the substrate, therefore control the required voltage of grid and also can reduce.
Above-mentioned explanation only is the general introduction of technical solution of the present invention, for can clearer understanding technological means of the present invention, and can be implemented according to the content of specification, and for above-mentioned and other purposes, feature and advantage of the present invention can be become apparent, below especially exemplified by preferred embodiment, and conjunction with figs., be described in detail as follows.
Description of drawings
Figure 1A to Fig. 1 C is the manufacturing process generalized section according to a kind of nonvolatile memory of a preferred embodiment of the present invention.
Fig. 2 A to Fig. 2 C is the manufacturing process generalized section according to a kind of nonvolatile memory of another preferred embodiment of the present invention.
Fig. 3 A to Fig. 3 D is the manufacturing process generalized section according to a kind of nonvolatile memory of the another preferred embodiment of the present invention.
Fig. 4 is the generalized section according to a kind of nonvolatile memory of a preferred embodiment of the present invention.
Fig. 5 is the generalized section according to a kind of nonvolatile memory of another preferred embodiment of the present invention.
Fig. 6 is the generalized section according to a kind of nonvolatile memory of the another preferred embodiment of the present invention.
Fig. 7 is its schematic diagram of programming of nonvolatile memory of Fig. 4 of the present invention.
Fig. 8 is its schematic diagram in the programming of carrying out another form of nonvolatile memory of Fig. 4 of the present invention.
Fig. 9 is its schematic diagram of wiping of nonvolatile memory of Fig. 4 of the present invention.
Figure 10 is its schematic diagram that is reading of nonvolatile memory of Fig. 4 of the present invention.
100,400: substrate
102,300,402: stacked structure
104,416: gate dielectric
106,418: the control grid
108,200,202,206,310,312,316: dielectric materials layer
110: conductor material layer
112,404: electric charge storage layer
114a, 114b, 412a, 412b: auxiliary grid
116,420: the gap
204,314: the composite dielectric clearance wall
302,500,600: the dielectric stack lamination
304,308,502,506,602,606: silicon oxide layer
306,504,604: silicon nitride layer
406,408,410,414: dielectric layer
700a: drain electrode reversal zone
700b: source electrode reversal zone
Embodiment
Reach technological means and the effect that predetermined goal of the invention is taked for further setting forth the present invention, below in conjunction with accompanying drawing and preferred embodiment, to nonvolatile memory and manufacture method and its embodiment of method of operation, structure, method, step, feature and the effect thereof that foundation the present invention proposes, describe in detail as after.
Figure 1A to Fig. 1 C is the manufacturing process generalized section that illustrates according to a kind of nonvolatile memory of a preferred embodiment of the present invention.
Please refer to Figure 1A, form stacked structure 102 in substrate 100, this stacked structure 102 comprises the gate dielectric 104 and the control grid 106 that is positioned at gate dielectric 104 tops of lower floor.In the present embodiment, gate dielectric 104 can be the individual layer dielectric layer, and it for example is a silicon oxide layer.In another embodiment, gate dielectric 104 can be the dielectric stack lamination of multilayer, and it for example is the silicon oxide/silicon nitride/silicon oxide stack layer.In addition, the material of control grid 106 for example is polysilicon, doped polycrystalline silicon or other suitable conductor materials.
Then, please refer to Figure 1B, in substrate 100, form dielectric materials layer 108, cover stacked structure 102 and substrate 100.The material of dielectric materials layer 108 for example is silica or other suitable materials, and its formation method for example is thermal oxidation method, the long-pending method in chemical gaseous phase Shen or other suitable methods.
Then, in substrate 100, form conductor material layer 110.The material of conductor material layer 110 for example is polysilicon, doped polycrystalline silicon or other suitable conductor materials, and its formation method long-pending processing procedure that for example is chemical gaseous phase Shen.
Afterwards, please refer to Fig. 1 C, definition conductor material layer 110, form electric charge storage layer 112 with top and sidewall in stacked structure 102, and on these electric charge storage layer 112 substrate on two sides 100, form a pair of auxiliary grid 114a, 114b, wherein have a gap 116 between auxiliary grid 114a, 114b and the electric charge storage layer 112.
What deserves to be mentioned is that above-mentioned electric charge storage layer 112 its materials are not limited to conductor material, it also can be high dielectric constant materials, and it for example is that silicon nitride or aluminium oxide etc. can be used as charge storage material.When if the material of electric charge storage layer 112 is high dielectric constant materials, then electric charge storage layer 112 needs to carry out in different steps with the making of auxiliary grid 114a, 114b.That is to say that electric charge storage layer 112 needs to define it respectively by different light shield processing procedures with auxiliary grid 114a, 114b.
In addition, it should be noted that, this moment, the dielectric materials layer 108 between stacked structure 102 tops and electric charge storage layer 112 can be used as gate dielectric layer usefulness, be positioned at the usefulness that substrate 100 lip-deep dielectric materials layers 108 can be used as tunneling layer, the dielectric materials layer 108 between stacked structure 102 sidewalls and electric charge storage layer 112 can be used as the usefulness of insulating gap wall.And, being not limited to one deck as its rete number of dielectric materials layer of gate dielectric layer or insulating gap wall, it also can be the dielectric stack lamination of multilayer.Below be to explain for two example two.
In the following embodiments, the dielectric materials layer of insulating gap wall for example is the dielectric stack lamination of multilayer, and its relevant processing procedure is described as follows.Please refer to Fig. 2 A, be to form in the substrate 100 after the stacked structure 102, in substrate 100, form dielectric materials layer 200 and 202, cover stacked structure 102 and substrate 100.Wherein, the material of dielectric materials layer 200 for example is a silica, and the material of dielectric materials layer 202 for example is a silicon nitride.Afterwards, please refer to Fig. 2 B, remove the dielectric materials layer 200 and 202 of part, form a pair of composite dielectric clearance wall 204 with the sidewall in stacked structure 102, this moment can come out in stacked structure 102 tops.Then, please refer to Fig. 2 C, in substrate 100, form dielectric materials layer 206, cover stacked structure 102, composite dielectric clearance wall 204 and substrate 100.Wherein, the material of dielectric materials layer 206 for example is a silica.Then, top and the sidewall in stacked structure 102 forms electric charge storage layer 112 again, and forms a pair of auxiliary grid 114a, 114b on these electric charge storage layer 112 substrate on two sides 100.
In another embodiment, the dielectric materials layer of gate dielectric layer and insulating gap wall for example all is the dielectric stack lamination of multilayer, and its relevant processing procedure explanation is as described below.Please refer to Fig. 3 A, form stacked structure 300 in substrate 100, this stacked structure 300 is gate dielectric 104, control grid 106 and dielectric stack lamination 302 by substrate 100 in regular turn.Wherein dielectric stack lamination 302 for example is silicon oxide layer 304/ silicon nitride layer 306/ silicon oxide layer 308 stack layers.Then, please refer to Fig. 3 B, in substrate 100, form dielectric materials layer 310 and 312, cover stacked structure 300 and substrate 100.Wherein, the material of dielectric materials layer 310 for example is a silica, and the material of dielectric materials layer 312 for example is a silicon nitride.Afterwards, please refer to Fig. 3 C, remove the dielectric materials layer 310 and 312 of part, form a pair of composite dielectric clearance wall 314 with the sidewall in stacked structure 300, can come out in silicon nitride layer 306 tops in the stacked structure 300 at this moment.Then, please refer to Fig. 3 D, in substrate 100, form dielectric materials layer 316, cover stacked structure 300, composite dielectric clearance wall 314 and substrate 100.Wherein, the material of dielectric materials layer 316 for example is a silica.Then, top and the sidewall in stacked structure 300 forms electric charge storage layer 112 again, and forms a pair of auxiliary grid 114a, 114b on these electric charge storage layer 112 substrate on two sides 100.
What deserves to be mentioned is, because the formed auxiliary grid of the present invention can be used as bit line, and on auxiliary grid, apply the voltage of appropriateness, can make the substrate of its below become the source area or the drain region of counter-rotating, so the size that can effectively dwindle memory component, thereby improve the element integration.
It below is the structure of explanation nonvolatile memory of the present invention.
Please refer to Fig. 4, nonvolatile memory of the present invention is made of substrate 400, stacked structure 402, electric charge storage layer 404, dielectric layer 406,408,410,414 and a pair of auxiliary grid 412a, 412b.
Wherein, stacked structure 402 is configured in the substrate 400, and this stacked structure 402 comprises the gate dielectric 416 and the control grid 418 that is positioned at gate dielectric 416 tops of lower floor.In the present embodiment, gate dielectric 416 can be the individual layer dielectric layer, and it for example is a silicon oxide layer.In another embodiment, gate dielectric 416 can be the dielectric stack lamination of multilayer, and it for example is the silicon oxide/silicon nitride/silicon oxide stack layer.In addition, the material of control grid 418 for example is polysilicon, doped polycrystalline silicon or other suitable conductor materials.
In addition, electric charge storage layer 404 covers stacked structure 402 tops and sidewall.Wherein the material of electric charge storage layer 404 comprises polysilicon or high dielectric constant materials, can be used as charge storage material and high dielectric constant materials for example is silicon nitride or aluminium oxide etc.
In addition, dielectric layer 406 is configured between stacked structure 402 tops and the electric charge storage layer 404, and this dielectric layer 406 can be used as the usefulness of gate dielectric layer.The material of dielectric layer 406 for example is silica or other suitable materials.
In addition, dielectric layer 408 is configured between stacked structure 402 sidewalls and the electric charge storage layer 404, and this dielectric layer 408 can be used as the usefulness of insulating gap wall.The material of dielectric layer 408 for example is silica or other suitable materials.
In addition, dielectric layer 410 is configured between electric charge storage layer 404 and the substrate 400, and this dielectric layer 410 can be used as the usefulness of tunneling layer.The material of dielectric layer 410 for example is silica or other suitable materials.
In addition, auxiliary grid 412a, 412b are configured on stacked structure 402 substrate on two sides 400, and with electric charge storage layer 404 at a distance of a gap 420.The material of auxiliary grid 412a, 412b for example is polysilicon or doped polycrystalline silicon.In addition, dielectric layer 414 is configured between auxiliary grid 412a, 412b and the substrate 400.The material of dielectric layer 414 for example is silica or other suitable materials.
What deserves to be mentioned is that above-mentioned dielectric layer 408 is not limited to the dielectric layer of individual layer, it also can be the dielectric stack lamination 500 (as shown in Figure 5) of multilayer.In Fig. 5, dielectric stack lamination 500 for example is that silicon oxide layer 502/ silicon nitride layer 504/ silicon oxide layer 506 constitutes.In addition, can the dielectric stack lamination 500 of configuring multi-layer except stacked structure 402 sidewalls, its top is the dielectric stack lamination 600 (as shown in Figure 6) of configurable multilayer also.That is to say that the dielectric layer 406 in Fig. 4 is replaced by the dielectric stack lamination 600 of the multilayer among Fig. 6, and this dielectric stack lamination 600 for example is that silicon oxide layer 602/ silicon nitride layer 604/ silicon oxide layer 606 constitutes.
Because non-volatile memory configuration of the present invention has auxiliary grid 412a, 412b, and this auxiliary grid 412a, 412b can be used as bit line, and on auxiliary grid 412a, 412b, apply the voltage of appropriateness, can make the substrate 400 of its below become the source area or the drain region of counter-rotating, so the size that can effectively dwindle memory component, thereby improve the element integration.
It below is the method for operation of explanation nonvolatile memory of the present invention.Please refer to Fig. 7, when programming, apply a control voltage (Vg) in control grid 418; Apply a boost voltage (Vag) and make the substrate 400 that is positioned at auxiliary grid 412a below form drain electrode reversal zone 700a in auxiliary grid 412a; Reversal zone 700a applies drain voltage (Vd) in this drain electrode; And setting auxiliary grid 412b becomes it and floats.Wherein, magnitude of voltage by little to being drain voltage, boost voltage and control voltage greatly in regular turn.So can make electronics wear tunnel by FN is entered in the electric charge storage layer 404 of close drain electrode reversal zone 700a by drain electrode reversal zone 700a.In one implemented, control voltage can be 14～20 volts, and it for example is 14 volts, and boost voltage can be 5～10 volts, and it for example is 8 volts, and drain voltage for example is 0 volt.
Please refer to Fig. 8, in another embodiment, the method for the nonvolatile memory of the present invention of programming can be to apply control voltage (Vg) in control grid 418; Apply boost voltage (Vag) in auxiliary grid 412a and 412b, and make the substrate 400 that is positioned at auxiliary grid 412a and 412b below form drain electrode reversal zone 700a and source electrode reversal zone 700b respectively; Reversal zone 700a applies drain voltage (Vd) in this drain electrode; 700b applies source voltage (Vs) in this source electrode reversal zone.Wherein, magnitude of voltage by little to being source voltage, drain voltage, control voltage and boost voltage greatly in regular turn.So can make electronics by channel hot electron effect (CHE) by source electrode reversal zone 700b, by the substrate 400 (channel region) of control grid 418 belows, and enter in the electric charge storage layer 404 near drain electrode reversal zone 700a.In one embodiment, control voltage can be 5～10 volts, and it for example is 5 volts, and boost voltage can be 5～10 volts, and it for example is 8 volts, and drain voltage can be 4～6 volts, and it for example is 4 volts, and source voltage for example is 0 volt.
In addition, please refer to Fig. 9, the method for deleting of nonvolatile memory of the present invention can be to apply control voltage (Vg) in control grid 418; Apply boost voltage (Vag) and make the substrate 400 that is positioned at auxiliary grid 412b below form source electrode reversal zone 700b in auxiliary grid 412b; 700b applies source voltage (Vs) in this source electrode reversal zone; And setting auxiliary grid 412a becomes it and floats.Wherein, magnitude of voltage by little to being source voltage, boost voltage and control voltage greatly in regular turn.So can make electronics wear tunnel by entering source electrode reversal zone 700b near in the electric charge storage layer 404 of source electrode reversal zone 700b by-FN.In one embodiment, control voltage can be-8～-12 volts, and it for example is-9 volts, and boost voltage can be 5～10 volts, and it for example is 8 volts, and source voltage can be 4～6 volts, and it for example is 5 volts.
Particularly,, therefore can solve when carrying out memory erase because the present invention is disposed at electric charge storage layer 404 on the control grid 418, the problem of over-erasure, thus improve the element reliability.
In addition, please refer to Figure 10, the read method of nonvolatile memory of the present invention can be to apply control voltage (Vg) in control grid 418; Apply boost voltage (Vag) in auxiliary grid 412a and 412b, and make the substrate 400 that is positioned at auxiliary grid 412a and 412b below form drain electrode reversal zone 700a and source electrode reversal zone 700b respectively; Reversal zone 700a applies drain voltage (Vd) in this drain electrode; Apply source voltage (Vs) in source electrode reversal zone 700b.Wherein, magnitude of voltage by little to being source voltage, drain voltage, control voltage and boost voltage greatly in regular turn.So can read the position that is stored in the electric charge storage layer 404.In one embodiment, control voltage can be 3～5 volts, and it for example is 3 volts, and boost voltage can be 5～10 volts, and it for example is 8 volts, and drain voltage can be 1～2 volt, and it for example is 1 volt, and source voltage for example is 0 volt.
What deserves to be mentioned is, in above-mentioned operation, be with one storage, wipe and read and explain, right non-in order to limit the present invention.If the material of its electric charge storage layer of nonvolatile memory of the present invention is a high dielectric constant materials, then can deposit one respectively in this electric charge storage layer left and right sides, use and make memory of the present invention can be used as multistage memory.
The above, it only is preferred embodiment of the present invention, be not that the present invention is done any pro forma restriction, though the present invention discloses as above with preferred embodiment, yet be not in order to limit the present invention, any those skilled in the art, in not breaking away from the technical solution of the present invention scope, when the method that can utilize above-mentioned announcement and technology contents are made a little change or be modified to the equivalent embodiment of equivalent variations, but every content that does not break away from technical solution of the present invention, according to technical spirit of the present invention to any simple modification that above embodiment did, equivalent variations and modification all still belong in the scope of technical solution of the present invention.
Claims (20)
1. the manufacture method of a nonvolatile memory is characterized in that it may further comprise the steps:
Form a stacked structure in a substrate, this stacked structure comprises a gate dielectric and a control grid that is positioned at this gate dielectric top of lower floor;
In the top of this stacked structure, sidewall and exposed this substrate, form one first dielectric layer, one second dielectric layer and one the 3rd dielectric layer respectively; And
Top and sidewall in this stacked structure cover an electric charge storage layer, and form a pair of auxiliary grid in this substrate of these electric charge storage layer both sides, and a gap apart between described auxiliary grid and this electric charge storage layer.
2. the manufacture method of nonvolatile memory according to claim 1 is characterized in that the material of wherein said electric charge storage layer comprises polysilicon, silicon nitride or other high dielectric constant materials.
3. the manufacture method of nonvolatile memory according to claim 1 is characterized in that wherein said gate dielectric is the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
4. the manufacture method of nonvolatile memory according to claim 1 is characterized in that wherein said first dielectric layer or this second dielectric layer are the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
5. the manufacture method of nonvolatile memory according to claim 4, it is characterized in that wherein the method that forms this first dielectric layer, this second dielectric layer and the 3rd dielectric layer in top, sidewall in this stacked structure and exposed this substrate respectively is included in formation one dielectric materials layer in this substrate, covers this stacked structure and this substrate.
6. the manufacture method of nonvolatile memory according to claim 4 is characterized in that wherein the method that forms this first dielectric layer, this second dielectric layer and the 3rd dielectric layer in top, sidewall in this stacked structure and exposed this substrate respectively comprises:
In this substrate, form one first dielectric materials layer and one second dielectric materials layer, cover this stacked structure and this substrate;
Remove this first dielectric materials layer of part and this second dielectric materials layer, form a pair of composite dielectric clearance wall with sidewall in this stacked structure; And
In this substrate, form one the 3rd dielectric materials layer, cover this stacked structure, this is to composite dielectric clearance wall and this substrate.
7. the manufacture method of a nonvolatile memory is characterized in that it may further comprise the steps:
Form a stacked structure in a substrate, this stacked structure is a gate dielectric, a control grid and a dielectric stack lamination by this substrate in regular turn;
In this substrate, form one first dielectric materials layer and one second dielectric materials layer, cover this stacked structure and this substrate;
Sidewall in this stacked structure forms a pair of composite dielectric clearance wall;
In this substrate, form one the 3rd dielectric materials layer, cover this stacked structure, this is to composite dielectric clearance wall and this substrate; And
Top and sidewall in this stacked structure cover an electric charge storage layer, and form a pair of auxiliary grid in this substrate of these electric charge storage layer both sides, wherein a gap apart between this auxiliary grid and this electric charge storage layer respectively.
8. the manufacture method of nonvolatile memory according to claim 7 is characterized in that the material of wherein said electric charge storage layer comprises polysilicon, silicon nitride or other high dielectric constant materials.
9. the manufacture method of nonvolatile memory according to claim 7 is characterized in that wherein said gate dielectric is the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
10. nonvolatile memory is characterized in that it comprises:
One substrate;
One stacked structure is configured in this substrate, and this stacked structure comprises a gate dielectric and a position control grid thereon of lower floor;
One electric charge storage layer covers this stacked structure top and sidewall;
One first dielectric layer is configured between this stacked structure top and this electric charge storage layer;
One second dielectric layer is configured between this stacked structure sidewall and this electric charge storage layer;
One the 3rd dielectric layer is configured between this electric charge storage layer and this substrate;
A pair of auxiliary grid is configured in this substrate of these stacked structure both sides, and with this electric charge storage layer at a distance of a gap; And
One the 4th dielectric layer is configured in respectively between this auxiliary grid and this substrate.
11. nonvolatile memory according to claim 10 is characterized in that the material of wherein said electric charge storage layer comprises polysilicon, silicon nitride or other high dielectric constant materials.
12. nonvolatile memory according to claim 10 is characterized in that wherein said gate dielectric, this first dielectric layer or this second dielectric layer are the dielectric stack lamination of an individual layer dielectric layer or a multilayer.
13. the method for operation of a nonvolatile memory, be suitable for a nonvolatile memory, this nonvolatile memory comprises that at least being positioned at one suprabasil one controls grid, cover an electric charge storage layer of this control top portions of gates and sidewall, be positioned at these control grid both sides and with this electric charge storage layer at a distance of one first auxiliary grid and one second auxiliary grid in a gap, it is characterized in that this method of operation comprises that carrying out one first programmes:
Apply one first voltage in this control grid, apply one second voltage and make this substrate that is positioned at this first auxiliary grid below form a drain electrode reversal zone in this first auxiliary grid, apply a tertiary voltage in this drain electrode reversal zone, and setting this second auxiliary grid becomes it to float, wherein magnitude of voltage, is entered near in this electric charge storage layer of this drain electrode reversal zone by this drain electrode reversal zone so that electronics is worn tunnel by FN to being this tertiary voltage, this second voltage and this first voltage greatly in regular turn by little.
14. the method for operation of nonvolatile memory according to claim 13 is characterized in that wherein said first voltage is 14～20 volts, this second voltage is 5～10 volts, and this tertiary voltage is 0 volt.
15. the method for operation of nonvolatile memory according to claim 13, it is characterized in that or comprise carry out one second the programming:
Apply one the 4th voltage in this control grid, apply one the 5th voltage in this first auxiliary grid and this second auxiliary grid, and make this substrate that is positioned at this first auxiliary grid and this second auxiliary grid below form a drain electrode reversal zone and an one source pole reversal zone respectively, apply one the 6th voltage in this drain electrode reversal zone, apply one the 7th voltage in this source electrode reversal zone, wherein magnitude of voltage by little to being the 7th voltage greatly in regular turn, the 6th voltage, the 4th voltage and the 5th voltage are so that electronics is entered near in this electric charge storage layer of this drain electrode reversal zone by this source electrode reversal zone by channel hot electron effect (CHE).
16. the method for operation of nonvolatile memory according to claim 15 is characterized in that wherein said the 4th voltage is 5～10 volts, the 5th voltage is 5～10 volts, and the 6th voltage is 4～6 volts, and the 7th voltage is 0 volt.
17. the method for operation of nonvolatile memory according to claim 13, it is characterized in that wherein when wiping, apply one the 8th voltage in this control grid, apply one the 9th voltage and make this substrate that is positioned at this second auxiliary grid below form the one source pole reversal zone in this second auxiliary grid, apply 1 the tenth voltage in this source electrode reversal zone, and setting this first auxiliary grid becomes it to float, wherein this magnitude of voltage by little to being the tenth voltage greatly in regular turn, the 9th voltage and the 8th voltage are so that electronics is worn tunnel by entering this source electrode reversal zone near in this electric charge storage layer of this source electrode reversal zone by FN.
18. the method for operation of nonvolatile memory according to claim 17 is characterized in that wherein said the 8th voltage is-8～-12 volts, the 9th voltage is 5～10 volts, and the tenth voltage is 4～6 volts.
19. the method for operation of nonvolatile memory according to claim 13, it is characterized in that wherein when reading, apply 1 the 11 voltage in this control grid, apply 1 the 12 voltage in this first auxiliary grid and this second auxiliary grid, and make this substrate that is positioned at this first auxiliary grid and this second auxiliary grid below form a drain electrode reversal zone and an one source pole reversal zone respectively, apply 1 the 13 voltage in this drain electrode reversal zone, apply 1 the 14 voltage in this source electrode reversal zone, wherein magnitude of voltage by little to being the 14 voltage greatly in regular turn, the 13 voltage, the 11 voltage and the 12 voltage are to read the position that is stored in this electric charge storage layer.
20. the method for operation of nonvolatile memory according to claim 19 is characterized in that wherein said the 11 voltage is 3～5 volts, the 12 voltage is 5～10 volts, and the 13 voltage is 1～2 volt, and the 14 voltage is 0 volt.
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| CN1216862A (en) * | 1997-11-04 | 1999-05-19 | 株式会社日立制作所 | Semiconductor memory device and method of fabricating the same |
| US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
| CN1433064A (en) * | 2002-01-14 | 2003-07-30 | 联华电子股份有限公司 | Operation process of non-volatile memory element |
| US20040130947A1 (en) * | 2003-01-02 | 2004-07-08 | Der-Tsyr Fan | Flash memory with trench select gate and fabrication process |
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| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN1216862A (en) * | 1997-11-04 | 1999-05-19 | 株式会社日立制作所 | Semiconductor memory device and method of fabricating the same |
| US6255166B1 (en) * | 1999-08-05 | 2001-07-03 | Aalo Lsi Design & Device Technology, Inc. | Nonvolatile memory cell, method of programming the same and nonvolatile memory array |
| CN1433064A (en) * | 2002-01-14 | 2003-07-30 | 联华电子股份有限公司 | Operation process of non-volatile memory element |
| US20040130947A1 (en) * | 2003-01-02 | 2004-07-08 | Der-Tsyr Fan | Flash memory with trench select gate and fabrication process |
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