CN100411306C - A/D converter in billion Ethernet transmission circuit - Google Patents

Abstract

The present invention relates to a digital-to-analog converter in a transmitting circuit of a kilomega Ethernet, which is composed of a temperature decoding module, a switch latch array module, a current unit array module and a phase-locked loop circuit module. 5-bit digital signals of a system are transmitted to the temperature decoding circuit, and 16-bit digital signals are output after the 5-bit digital signals are encoded; the 16-bit digital signals are respectively transmitted to the switch latch module for processing, and 128 paths of digital switch signals are obtained; the digital switch signals are used as the input of a current unit array and can control the current unit to be opened or closed; the phase-locked loop circuit can provide a sampling clock and a series of clocks needed by 4 ns sequence control for the digital-to-analog converter. The present invention can control the conversion time of outputting a simulating electrical level between 3 ns and 5 ns.

Description

Digital to analog converter in the gigabit Ethernet transtation mission circuit

Technical field

The invention belongs to technical field of integrated circuits, be specifically related to a kind of can be at protocol requirement to the structural design of digital to analog converter (DAC) in the gigabit Ethernet transtation mission circuit of controlling output waveform rise time and fall time.

Background technology

21st century is the century of rapid development of information technology, and network system is the technology guide and the material base of quick propagation of realization information and resource-sharing.Network hardware system mainly adopts Local Area Network systems technologies such as Ethernet, FDDI net and ATM net to design, and wherein ATM net and gigabit Ethernet are the main trend of Future Development.Shared Ethernet (common Ethernet has successively been experienced in the development of Ethernet, transmission data rate 10Mbps), crossover Ethernet, 100 m ethernet (Fast Ethernet, send data rate 100Mbps), and the gigabit Ethernet that is developing (Fast Ethernet sends data rate 1000Mbps).Rose in 1998 in network application, successfully to have developed and go up the coded system and the algorithm of transmitted in both directions simultaneously, the 1000Base-T in Here it is the IEEE gigabit Ethernet at 4 pairs five class unshielded twisted pairs (Cat.5 UTP).Gigabit Ethernet is the network application that the LAN system is exerted far reaching influence, and it has almost used the limit with the theoretic transmission bandwidth of five class unshielded twisted pairs.Compare with Ethernet before, Gigabit Ethernet has following a plurality of advantage: fast 100 times than common Ethernet of its speed, fast 10 times than Fast Ethernet; Because adopt and the Fast Ethernet similar techniques, network compatibility heightens, the deployment ability is more extensive; Have the full duplex ability, allow to receive simultaneously and send data, be equivalent to effective bandwidth double like this.Therefore, the current whole world sharply strengthens the interest of gigabit Ethernet.Along with exploitation, use and the popularization of dried mbit ethernet, gigabit Ethernet becomes network technology developing direction from now on.

Gigabit Ethernet 1000Base-T adopts 5 class unshielded twisted pairs by the ANSI/TIA/EIA-568-A definition, and the transmission rate of the 1000Mb/s of half-duplex (CSMA/CD) and full duplex is provided.It comes high-speed parallel ground transmission data by four couples 5 class unshielded twisted pair UTP-5, and the transmission rate of every pair of twisted-pair feeder is 125MHz.In each tranmitting data register cycle, supplied with digital signal TX[7:0] the 8bit data through forming four analog waveforms after PCS sublayer and the PMA sub-layer processes, speed with 125MHz is delivered to respectively on four pairs of parallel twisted-pair feeders by transformer, therefore when four pairs of twisted-pair feeders transmitted simultaneously, total digital information transmission speed was 1000Mb/s just.The design of transtation mission circuit is a pith in the design of gigabit Ethernet (Gigabit Ethernet) physical chip, and it has determined gigabit ethernet card to send the waveform characteristic and the data conversion feature of signal.

1000Base-T physical chip transtation mission circuit mainly comprises two parts, and a part is digital to analog converter (DAC), converts digital signal to suitable analog signal; Another part is a cable drive, and being used for provides necessary drive current to transmission cable.Early stage DAC has multiple structure, for example resistance gradient structure, charge distributing type structure, electric current distribution type structure and current drive-type structure.Current drive-type DAC is the main flow structure of present high-speed DAC.In the middle of the design of DAC, when supplied with digital signal is N bit, then Shu Chu distinguishable maximum analog level number is 2 ^NIndividual.In general, when the output analog level when certain one-level is transformed into another grade, The faster the better to require the switching rate of signal, promptly exports the change of analog signal along with supplied with digital signal, The faster the better for the speed of its response.But the transformation rate at the gigabit Ethernet output waveform in the middle of IEEE 802.3 standard agreements has special regulation, the output that requires DAC is when some level jump to the another one level, bound-time (being the rise time or the fall time of level) must be controlled in 4ns ± 25%, transit time when being DAC output signal generation saltus step is between 3ns～5ns, can not be too fast, can not be too slow.Therefore this is different with DAC design in the past, is a challenge to the design of the whole transtation mission circuit of gigabit Ethernet.In the middle of some present designs, for example in the design of the transtation mission circuit of 100 m ethernet, similar regulation is arranged also.At the design of level conversion time in the 100 m ethernet transtation mission circuit, arranged, the transit time that has proposed to control with the length of impulse electricity time of electric capacity this 4ns in the middle of some lists of references as J.Everitt, J.Parker, P.Hurst, D.Nack, K.Konda, " A CMOS Transceiver for 10-Mb/s; and100M-b/s Ethernet, " IEEE J.Solid-State Circuits, Vol.33, No.12, December 1998.But, in the CMOS in modern times integrated circuit technology the inside, obtain the high slightly electric capacity of precision, need realize electric capacity with the MIM layer.But its precision is still lower, and chip occupying area is big simultaneously, and the impulse electricity time is difficult to accurately control.Therefore this method itself exists the defective that is difficult to overcome.Add and also have other a lot of parasitic parameters in the side circuit, dead resistance for example, parasitic capacitance, the result who obtains at last can differ greatly with desired value.

Summary of the invention

The objective of the invention is to propose digital to analog converter (DAC) structure in a kind of improved gigabit Ethernet transtation mission circuit, can be effectively controlled between 3ns～5ns change-over time of its output analog level.

Digital to analog converter in the gigabit Ethernet transtation mission circuit that the present invention proposes, connect and compose through circuit by thermometer decoding module 1, switch lock storage array module 2, current unit array module 3 and phase-locked loop circuit module 4, wherein, thermometer decoding module 1, switch lock storage array module 2, current unit array module 3 connect successively, phase-locked loop circuit module 4 is connected with switch lock storage array module 2, and its structure is seen shown in Figure 1.The DAC resolution that the present invention will design is 5bit, and this digital signal offers thermometer decoding circuit 1, by exporting the 16bit digital signal after the coding, sends into respectively in the switch lock storage module 2 and handles.Obtain 128 way word switch signals,, come opening or closing of Control current unit as the input of current unit array module 3.Phase-locked loop circuit module 4 provides sampling clock for digital to analog converter and is used for the required a series of clocks of 4ns sequencing control.

Among the present invention, be improved, can accurately produce the 4ns conversion time that satisfies 802.3 consensus standards by the circuit of the current unit switch arrays 3 of latch arrays 2 control.The specific descriptions of this part-structure module as shown in Figure 2.The basic principle of this structure DAC is, will import the 5bit encoding digital signals by the thermometer decoding device, obtains 16 pairs of output digital differential signals, Dout[0:15 promptly shown in Figure 2].Switch lock storage array module 2 is to be made up of 16 identical switch lock storages and 8 little current unit array 5-20 corresponding with it with current unit array module 3, and the difference output of its current unit all is connected in parallel.This 16 couple output digital differential signal is admitted to 16 switch lock storages and current unit array module 5-20 respectively, controls opening or closing of 16 current units.Last exportable 16 grades of difference currents that vary in size by certain ohmic load, just can produce 16 grades of analog levels with this electric current.The present invention is used in the transtation mission circuit of gigabit Ethernet, and gigabit Ethernet is with four pairs of twisted-pair feeder parallel convey signals, and every road tranmitting data register is 125MHz, thus in the transtation mission circuit sampling clock cycle of each DAC be 8ns.When input 5bit digital signal changed, the difference output current will change thereupon.For the transformation period with electric current is controlled at 4ns, adopt structure as shown in Figure 2.When be 4ns the change-over time of output difference current, be 4ns its stabilization time.Therefore, the present invention will adopt gradually the staircase waveform that increases progressively (or successively decreasing) to come the 4ns transit time of match analog output signal.Among the present invention, phase-locked loop module 4 requires can produce 16 phase clock signal CLK[0:15 for fundamental clock is 125MHz], CLK[0:15 then] in differing of every adjacent two phase clock be 0.5ns.If CLK[0:7] be 8 continuous phase clocks, as shown in Figure 3.Because every adjacent two phase clock differs and is 0.5ns, then from CLK[0] to CLK[7] to differ just in time be 4ns.Therefore can go the control switch latch arrays with this 8 phase clock.Basic skills is exactly each current unit in 16 current units to be divided into 8 little current sources again, by CLK[0:7] go to control successively opening or closing of 8 little current sources by the switch lock storage.When 8 little current sources were all opened or closed, the required time just in time was 4ns.

The present invention is directed among Fig. 2 the sequencing control of latch arrays and current source array module 5-20 and improve, these 16 array module structures are identical, and the difference output of its current unit all is connected in parallel, and has just constituted final DAC output difference current.Be that example provides description more specifically with switch lock storage among Fig. 2 and 8 little current source array modules 5 below.The circuit structure that adopts as shown in Figure 4.Latch module (Latch) 1 is identical to latch 8 modules, and current source 1 is also identical to current source 8.Wherein latch 1-8 adopts the mode of cascade, and the digital input signals of each grade Latch all is by the numeral output decision of upper level Latch, adopts 8 phase clock signal CLK[0 successively]～CLK[7].8 identical current sources adopt mode in parallel.Wherein Vbias1 and Vbias2 are bias voltage, are produced by mirror image by special reference current source, are used to provide constant current source.When control 8 current supply switchs 8 latchs by clock signal clk [0]～CLK[7] open successively after, the difference output current is stepped to be increased progressively.Otherwise when it was closed successively, output was successively decreased with regard to stepped.To increase progressively is example, and Fig. 5 has shown the course of work of circuit.

As shown in Figure 5, (establish and to open n current unit switch when DAC simulation output jumps to another value VB from a value VA (establish and need open m current unit switch), and during m＜n), on m current unit basis of having opened, also need to open (n-m) individual current unit, suppose that it is I that each current unit flows through electric current _r, and each current unit is divided into 8 little current units, then each little current unit size of current is

At 8 phase clock CLK[7:0] control under, just rise every the 0.5ns output analogue value

Individual unit, output is stablized behind 4ns, reaches VB, shown in Fig. 4-3.Otherwise if m＞n, then 8 little current sources are closed under the control of 8 phase clocks successively, promptly just descend every the 0.5ns output analogue value Individual unit, output is stable behind 4ns.For avoiding the high-frequency loss in signals transmission, also need the staircase waveform that a low pass filter (LPF) will last figure level and smooth.In the middle of the realization of reality, because circuit itself exists bigger dead resistance and parasitic capacitance, be equivalent to a low pass filter, so specialized designs low pass filter again.In sum, the DAC among the present invention forms array by 16 * 8 little current sources altogether, and current source is produced by special biasing mirror image circuit, the final conversion time of realizing the output analog signal of 4ns under the sequencing control of 8 phase clocks.

Description of drawings

Fig. 1 is the schematic diagram of digital to analog converter construction system.

Fig. 2 is the schematic diagram of digital to analog converter main part among the present invention.

Fig. 3 is the sequential relationship schematic diagram of the required clock of transmitting system.

Fig. 4 is the difference current generation circuit block diagram that satisfies the 4ns conversion timing sequence

Fig. 5 is for producing the transtation mission circuit fundamental diagram of staircase waveform

Fig. 6 is difference output and the difference output comparison diagram that does not pass through latch by latch

Fig. 7 is the physical circuit figure of latch unit.

Number in the figure: 1 is the thermometer decoding module, 2 is switch lock storage array module, 3 is the current unit array module, 4 is the phase-locked loop circuit module, 5-20 is switch lock storage and 8 little current source array, 21-28 is a current source module, and 29-36 is the latch module, and 37 is transport module, 38 are the positive feedback module, 39 is the latch units module, and 40 and 41 is inverter modules, and 42 and 43 is the nMOS transistor, 44 and 45 is the pMOS transistor, 46-49 is the pMOS transistor, Dout[0:15] be 16 pairs of output digital differential signals, CLK[0:15] be 16 phase clock signals.

Embodiment

Further describe the present invention below in conjunction with accompanying drawing.

Digital to analog converter is by being made of thermometer decoding device module 1, switch lock storage array module 2 and current unit array module 3, and its structure is seen shown in the accompanying drawing 1.Phase-locked loop module 4 provides all required clock signals for the operate as normal of digital to analog converter.According in 802.3 consensus standards to the requirement of gigabit Ethernet cable output signal, the concrete function that the present invention will realize is will import the 5bit digital signal according to certain coding rule to convert 16 grades of analog output signals to, when analog signals at different levels were changed each other, conversion time was 4ns.Add the various errors that exist in circuit design, the actual converted time range is between 3ns～5ns.As shown in Figure 1, the 5bit digital input signals is input temp decoding module 1 at first, obtains the 16bit digital signal according to the temperature coding rule.Add the reverse signal of exporting each digital signal simultaneously, the actual digital signal of exporting 32bit altogether.These 16 pairs of differential digital signal will be sent into respectively in switch latch arrays and the current source array.The most basic effect of latch is in order to reduce the glitch of wave form varies in short-term of DAC.The digital signal of temperature coding output is undertaken being re-used as switching signal after the Synchronous Processing by latch and is gone to control opening or closing of 16 current units respectively.In the present invention, the function of latch moreover, the 8 phase clock signal CLK[0:7 of its also collaborative phase-locked loop pll output], as time-sequence control module, come the course of work of Control current unit, realize the analog output signal rise or fall time conversion requirement of agreement regulation.The difference input switch of the positive and negative two-phase Digital Signals current unit of latch arrays output is exported difference current at last.

As shown in Figure 2, pass through 16 identical switch lock storages and 8 current source array module 5-20 respectively from the signal demand of thermometer decoding module output, with module 5 is example, and this module is made of the identical latch module 29-36 of 8 cascades and the identical current source module 21-28 of 8 parallel connections.The supplied with digital signal Din of latch module 29 and Din_Bar are some bit of thermometer decoding output, and the non-signal of this bit.The supplied with digital signal of latch 30-36 is the output Do1 and the Do1_Bar of its upper level latch module.Latch comprises two-part output, and a part is hanged down a pair of differential digital signal Do2 and the Do2_Bar that produces after Glitch handles for some bit and the non-signal thereof with thermometer decoding output, as the input of corresponding certain current source; Another to digital differential output signal Do1 and Do1_Bar by after the sequential adjustment of clock as the input signal of next stage latch, by that analogy.The adjacent eight phase clock signal CLK[0 that differ to 0.5ns by the phase-locked loop generation]～CLK[7], as shown in Figure 3, also as the input of these 8 latch module 29-36 clock end CLK, the control entire circuit is to the requirement of sequential successively.Current source except by a pair of output digital signal of latch as the switching signal, also have two input signal Vbias1 and Vbias2 mirror image offset signal as current source, purpose is in order to produce a certain size electric current.What list in the accompanying drawing 4 is the major part of DAC, and such as just not providing in the generation circuit diagram of bias voltage Vbias1 and Vbias2, but this does not influence the course of work that helps to understand the DAC circuit by this figure.The difference current of 8 current sources output IA and IB are connected in parallel, and then as shown in Figure 4, with all difference output-parallels of 16 current units together, have just constituted the final analog output signal of DAC again.Latch module 29 with accompanying drawing 4 is an example, specifically describes its circuit structure, as shown in Figure 7.Latch module 29 mainly comprises transport module 37, positive feedback module 38, latch units module 39 and two inverter modules 40 and 41.Transport module 37 is made of two identical n channel mosfets (nMOS) transistor 42 and 43.The source end of nMOS pipe 42 and 43 meets the reverse signal Din_Bar of input signal Din and Din respectively, and the grid of nMOS pipe 42 and 43 all meets clock CLK[0] as the switch of transmission unit.As clock CLK[0] when being high level, transmission unit 42 and 43 is opened, and input signal Din and Din_Bar are sent to the drain terminal DI and the DI_Bar of nMOS pipe 42 and 43 respectively.Positive feedback module 38 is to be made of two identical p channel mosfets (pMOS) transistor 44 and 45.The source end of pMOS pipe 44 and 45 all meets power vd D, a grid of 44 and 45 and a leakage level cross-couplings, and promptly the grid of pMOS pipe 44 connects the drain electrode of pMOS pipe 45, and 45 grid connects 44 drain electrode.Simultaneously, the drain terminal of pMOS pipe 44 also meets the drain terminal DI of nMOS pipe 42, and the drain terminal of pMOS pipe 45 also meets the drain terminal DI_Bar of nMOS pipe 43.When DI changed from the low level to the high level, 45 pipes ended gradually from conducting, and to low transition, this has caused 44 pipes from by conducting gradually again to acceleration DI_Bar, has further quickened Din and has become high level from low transition from high level.To when changing to low level, high level also have effect same by this circuit as DI_Bar conversely, the operation principle of Here it is positive feedback unit.DI and DI_Bar respectively through two identical inverter modules 40 and 41, establish inverter modules 40 and are output as Do1_Bar again, and inverter modules 41 is output as Do1.Differential signal is to Do1 and Do1_Bar input signal Din and the Din_Bar as next stage latch module 30.

In general because the input difference digital signal of current source cell has certain time-delay each other, can cause certain the time differential signal simultaneously for high or simultaneously for low.To the current source cell that is made of the pMOS differential pair tube, when differential signal when being high simultaneously, current source cell ends; To the current source cell that constitutes by the nMOS differential pair tube, when differential signal simultaneously when low, current source cell ends.Current source cell is from when the conducting once more, need the regular hour to carry out impulse electricity owing to produce the bias transistor of electric current, therefore current source flows out stable difference current needs certain delay, produce certain overshoot simultaneously, the so-called wave form varies of just above mentioning in short-term, i.e. Glitch.Glitch has had a strong impact on the dynamic characteristic of current source, must suppress Glitch by designing suitable latch unit Latch.In the design of Latch, to the current source that is made of the pMOS pipe, the difference supplied with digital signal is low at jumping moment as much as possible simultaneously; To the current source that constitutes by the nMOS pipe, then be high as much as possible simultaneously.Purpose is in order to reduce DAC by a Glitch who produces when exporting analog signal conversion to another analog signal.What use among the present invention is the current source that is made of the nMOS differential pair tube, therefore the function of Latch be make the Control current source the difference supplied with digital signal when from the high level to the low level or from the low level to the high level, changing, the part of its intersection be height as much as possible simultaneously.As shown in Figure 6.Therefore, Latch module 39 is made of 4 pMOS pipe 46-49 in accompanying drawing 7.The source end of pipe 46 and pipe 48 all meets power vd D, and the drain terminal of pipe 47 and pipe 49 is ground connection GND all.The drain terminal of pipe 46 is taken over 47 source end, and the drain terminal of 48 pipes is taken over 49 source end.The grid cross-couplings of PMOS pipe 46-49 is promptly managed 46 grid and is taken over 49 grid, and the grid of pipe 47 is taken over 48 grid.The public grid of the output Do1_Bar of inverter 40 adapter simultaneously 47 and pipe 48, the output Do1 adapter 46 of inverter 41 and the public grid of pipe 49, promptly the differential signals of inverter 40 and 41 outputs are right as the input differential signal of Latch unit to Do1 and Do1_Bar.Pipe 46 and pipe 48 drain terminal Do2 and Do2_Bar are the output signals of Latch unit, and as shown in Figure 4, these two output signals will be right as the differential input signal of next stage current source module 22, the opening or closing of Control current source.Effectively reduce glitch like this to the DAC Effect on Performance.The structure of current source module 21-28 also is identical, adopt more traditional structure, particular circuit configurations can be with reference to S.Huss, M.Mullen, C.Gray, R.Smith, M.Summers, J.Shafer, P.Heron, T.Sawinska, and J.Medero, " A DSP Based 10BaseT/100BaseTX Ethernet Transceiver in a 1.8V; 0.18um CMOS Technology; " IEEE Custom Integrated Circuits Conference, pp.135-138,2001.

This 8 phase clock signal CLK[0:7 that utilize] control the circuit of the latch units transmitting switch structure of 8 cascades successively, generation is every ladder of 0.5ns staircase waveform of totally 8 ladders, then final difference current output is undertaken smoothly obtaining the analog signal transit time of 4ns by low pass filter.This structure is easy to realize on technology, and can obtains more accurate 4ns conversion time.Therefore adopted by the designing institute of gigabit Ethernet transtation mission circuit.

Claims (5)

1. the digital to analog converter in the gigabit Ethernet transtation mission circuit, it is characterized in that connecting and composing through circuit by thermometer decoding module (1), switch lock storage array module (2), current unit array module (3) and phase-locked loop circuit module (4), wherein, thermometer decoding module (1) is connected with switch lock storage array module (2), switch lock storage array module (2) is connected with current unit array module (3), and phase-locked loop circuit module (4) is connected with switch lock storage array module (2); 5 bit digital signal of system offer thermometer decoding circuit (1), by exporting 16 bit digital signal after the coding, send into respectively in the switch lock storage module (2) and handle, obtain 128 way word switch signals and come opening or closing of Control current unit as the input of current unit array module (3); Phase-locked loop circuit module (4) provides sampling clock for digital to analog converter and is used for 4 nanoseconds of a series of clocks that sequencing control is required.

2. digital to analog converter according to claim 1, it is characterized in that described switch lock storage array module (2) reaches 8 the little current unit array modules (5-20) corresponding with it with current unit array module (3) by 16 identical switch lock storages and forms, the difference output of its current unit all is connected in parallel; 16 pairs of output digital differential signals are sent into 16 identical switch lock storages and 8 the little current unit array modules (5-20) corresponding with it respectively, and 16 grades of difference currents that vary in size are exported in opening or closing of 16 current units of control at last.

3. digital to analog converter according to claim 2 is characterized in that fundamental clock is 125MHz in the said phase-locked loop circuit module (4), has 16 phase clock signals (CLK[0:15]), and differing of every adjacent two phase clock is 0.5 nanosecond; 8 wherein continuous phase clock signals (CLK[0:7]), the control switch latch arrays.

4. digital to analog converter according to claim 3, it is characterized in that described 16 identical switch lock storages and 8 the little current unit array modules (5-20) corresponding with it, wherein, each module is made of with 8 identical current source module (21-28) of parallel connection 8 identical latch modules (29-36) of cascade; Wherein, described latch module mainly comprises transport module (37), positive feedback module (38), latch units module (39) and two inverter modules (40,41); Transport module (37) is made of the nMOS pipe (42) and the 2nd nMOS pipe (43) of two identical n channel mosfets; The source end of the one nMOS pipe (42) and the 2nd nMOS pipe (43) connects the reverse signal (Din_Bar) of input signal (Din) and this input signal respectively, and a nMOS manages grid that (42) and the 2nd nMOS manage (43) and connects the switch of clock (CLK[0]) as transmission unit; Positive feedback module (38) is to be made of the pMOS pipe (44) of two identical p channel mosfets and the 2nd pMOS pipe (45); The source end of the one pMOS pipe (44) and the 2nd pMOS pipe (45) all connects power supply (VDD), and pMOS pipe (44) and the 2nd pMOS manage the grid of (45) and leak the level cross-couplings; Simultaneously, the drain terminal of pMOS pipe (44) also meets the drain terminal DI of nMOS pipe (42), and the drain terminal of the 2nd pMOS pipe (45) also connects the drain terminal (DI_Bar) of the 2nd nMOS pipe (43).

5. digital to analog converter according to claim 4, it is characterized in that the latch units module manages (46,47,48,49) by 4 pMOS and constitute, the source end of the 3rd pMOS pipe (46) and the 5th pMOS pipe (48) all connects power supply (VDD), and the drain terminal of the 4th pMOS pipe (47) and the 6th pMOS pipe (49) is ground connection (GND) all; The drain terminal of the 3rd pMOS pipe (46) connects the source end of the 4th pMOS pipe (47), and the drain terminal of the 5th pMOS pipe (48) connects the source end of the 6th pMOS pipe (49); The grid cross-couplings of PMOS pipe (46,47,48,49); The output (Do1_Bar) of first inverter modules (40) simultaneously connects the public grid of the 4th pMOS pipe (47) and the 5th pMOS pipe (48), and the output (Do1) of second inverter modules (41) connects the public grid of the 3rd pMOS pipe (46) and the 6th pMOS pipe (49).

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