CN100424827C - Method for fabricating openings of self aligned contact window, and semiconductor component - Google Patents
Method for fabricating openings of self aligned contact window, and semiconductor component Download PDFInfo
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- CN100424827C CN100424827C CNB2005100920461A CN200510092046A CN100424827C CN 100424827 C CN100424827 C CN 100424827C CN B2005100920461 A CNB2005100920461 A CN B2005100920461A CN 200510092046 A CN200510092046 A CN 200510092046A CN 100424827 C CN100424827 C CN 100424827C
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- Prior art keywords
- conductor
- substrate
- clearance wall
- contact window
- layer
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- Expired - Fee Related
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- 238000000034 method Methods 0.000 title claims abstract description 59
- 239000004065 semiconductor Substances 0.000 title claims description 29
- 239000004020 conductor Substances 0.000 claims abstract description 100
- 239000000758 substrate Substances 0.000 claims abstract description 51
- 238000004519 manufacturing process Methods 0.000 claims description 27
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 26
- 239000000463 material Substances 0.000 claims description 23
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 15
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 15
- 229910052751 metal Inorganic materials 0.000 claims description 13
- 239000002184 metal Substances 0.000 claims description 13
- 229910021332 silicide Inorganic materials 0.000 claims description 12
- FVBUAEGBCNSCDD-UHFFFAOYSA-N silicide(4-) Chemical compound [Si-4] FVBUAEGBCNSCDD-UHFFFAOYSA-N 0.000 claims description 12
- 229910052814 silicon oxide Inorganic materials 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims description 8
- 238000005530 etching Methods 0.000 claims description 8
- 239000000377 silicon dioxide Substances 0.000 claims description 7
- 230000015572 biosynthetic process Effects 0.000 claims description 6
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 6
- 229920005591 polysilicon Polymers 0.000 claims description 6
- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 claims description 6
- 229910021342 tungsten silicide Inorganic materials 0.000 claims description 6
- 239000010410 layer Substances 0.000 description 81
- 238000005516 engineering process Methods 0.000 description 14
- 229920002120 photoresistant polymer Polymers 0.000 description 5
- 238000000059 patterning Methods 0.000 description 3
- 150000002500 ions Chemical class 0.000 description 2
- 125000006850 spacer group Chemical group 0.000 description 2
- 230000005641 tunneling Effects 0.000 description 2
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000000151 deposition Methods 0.000 description 1
- 230000008021 deposition Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000002372 labelling Methods 0.000 description 1
- 239000011241 protective layer Substances 0.000 description 1
Images
Abstract
The method includes steps: multiple component structures are formed on substrate provided in advance, and top parts of these structures are higher than surface of substrate; forming first dielectric layer and conductor layer on surface of substrate and surface of surfaces of these component structures in sequence; then, removing partial conductor layer on top parts of these structures and on sidewalls, and forming multiple first gap walls on uncovered sidewalls of component structures; removing uncovered conductor layer and first dielectric layer by using first gap walls as masks so as to expose substrate, and form multiple conductor gap walls; forming multiple second gap walls on sidewalls of conductor gap walls.
Description
Technical field
The present invention relates to a kind of semiconductor element and related process thereof, particularly relate to a kind of semiconductor element and the manufacture method of aiming at contact window voluntarily.
Background technology
Along with the progress of semiconductor technology, size of component is also constantly dwindled and is entered in the field of deep-sub-micrometer.Great scale integrated circuit (ULSI) technology has developed into below 0.18 micron at present, and along with the increase of integrated circuit integration, metal and semi-conductive contact hole are also more and more little.In order to overcome more and more little live width and to prevent contact hole generation aligning mistake (misalignment), contact hole (self-aligned contact, design SAC) are aimed in general employing voluntarily.
Figure 1A to Fig. 1 C is the existing flow process profile of aiming at the manufacture method of contact window voluntarily.Please refer to Figure 1A, at first, provide a substrate 100, a plurality of doped regions 106 that have been formed with a plurality of component structures 102 in the substrate 100 and have been positioned at its below.Then, on the surface of substrate 100 and component structure 102, form dielectric layer 104, conductor layer 108 and silicon nitride layer 110 in regular turn.Then, please refer to Figure 1B, carry out etch process, to form clearance wall 110a in conductor layer 108 sidewalls.Then, be mask with clearance wall 110a, carry out etch process and form conductor clearance wall 108a, this conductor clearance wall 108a exposes a upper surface and a sidewall.Next, form another clearance wall 112 as protection in the sidewall of conductor clearance wall 108a, when forming clearance wall 112, the material of clearance wall 112 also is covered in the exposed upper surface of conductor clearance wall 108a as protection.Afterwards, please refer to Fig. 1 C, in substrate 100, form dielectric layer 114.Afterwards, carry out etch process,, and expose substrate 100 with formation contact window 116 in dielectric layer 114.
Though it should be noted that etched in alignment technology can be avoided the problem of contact window aligning mistake on the general photoengraving carving technology voluntarily, and, make technology comparatively simple, and can reduce cost because reduce the use of one photomask.Yet, because cover its thinner thickness of spacer material at conductor clearance wall 108a top, therefore when carrying out voluntarily etched in alignment technology when forming contact window, the spacer material that is positioned at conductor clearance wall 108a top can corrode and make conductor clearance wall 108a top expose out because of continuous etched dose.In addition, the knot place 101 of clearance wall 110a and clearance wall 112 also may corrode conductor clearance wall 108a is come out because of continuous etched dose.Produce the phenomenon of short circuit after so can causing between formed contact hole connector and the conductor clearance wall 108a, and influence the usefulness of element.
Summary of the invention
Purpose of the present invention is exactly that a kind of manufacture method of aiming at contact window voluntarily is being provided, and can form the thicker clearance wall of thickness in making step, avoids the conductor clearance wall of element to expose when forming contact window, causes the phenomenon of short circuit.
Another object of the present invention provides a kind of semiconductor element, and it has the bigger clearance wall of thickness, can be when carrying out contact window technology, and the conductor clearance wall under the protection clearance wall has increased the feasibility of dwindling component size.
The present invention proposes a kind of manufacture method of aiming at contact window voluntarily, and a substrate is provided earlier, be formed with a plurality of component structures in this substrate, and the top of these component structures is higher than the surface of substrate.Then, on the surface of substrate and component structure, form first dielectric layer and conductor layer in regular turn.Then, the segment conductor layer on removal component structure top and the sidewall.Next, on the exposed sidewall of component structure, form a plurality of first clearance walls.Continuing it, is mask with these first clearance walls, removes the exposed conductor layer and first dielectric layer, and exposes substrate, and make the conductor layer that remains form a plurality of conductor clearance walls.Afterwards, on the sidewall of these conductor clearance walls, form a plurality of second clearance walls.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, above-mentioned is that mask is removed the step of the segment conductor layer on component structure top and the sidewall for example for carrying out anisotropic etching process with first clearance wall.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, the method for the above-mentioned removal bare exposed conductor layer and first dielectric layer is for example for carrying out anisotropic etching process.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, above-mentioned conductor layer for example is the composite conductor layer, and it for example is polysilicon layer and position metal silicide layer thereon.Wherein, the material of metal silicide layer for example is a tungsten silicide.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, above-mentioned a plurality of component structures for example are the plough groove type element.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, the material of the first above-mentioned clearance wall for example is a silicon nitride.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, the material of the first above-mentioned dielectric layer for example is silica or silicon oxide/silicon nitride/silicon oxide.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, can also after forming second clearance wall, in substrate, form second dielectric layer.
According to the described manufacture method of aiming at contact window voluntarily of embodiments of the invention, can also be after forming second dielectric layer, carry out etch process, in second dielectric layer, to form a plurality of contact windows, wherein these contact windows are between two adjacent elements structures, and expose substrate, first clearance wall and second clearance wall.
The present invention proposes a kind of semiconductor element in addition, comprises a substrate, an element structure, a dielectric layer, a doped region, a conductor clearance wall and first clearance wall.Wherein, above-mentioned substrate has a groove.Component structure is disposed in the groove, and the top of component structure is higher than the surface of substrate.Doped region is disposed in the substrate of component structure bottom.The conductor clearance wall is disposed on the sidewall of component structure Lower Half.First clearance wall is disposed at the sidewall of the component structure first half, and covers on the conductor clearance wall.Dielectric layer is disposed between conductor clearance wall and the component structure, and is disposed between conductor clearance wall and the substrate.
According to the described semiconductor element of embodiments of the invention, one second clearance wall can also be arranged, be disposed on the sidewall of conductor clearance wall.
According to the described semiconductor element of embodiments of the invention, above-mentioned component structure for example is grid structure conductor structure or plough groove type element.
According to the described semiconductor element of embodiments of the invention, the material of the first above-mentioned clearance wall for example is a silicon nitride.
According to the described semiconductor element of embodiments of the invention, the material of above-mentioned dielectric layer for example is silica or silicon oxide/silicon nitride/silicon oxide.
According to the described semiconductor element of embodiments of the invention, above-mentioned doped region for example is a source electrode.
According to the described semiconductor element of embodiments of the invention, above-mentioned conductor clearance wall for example is the composite conductor layer, and it for example is polysilicon layer and position metal silicide layer thereon.Wherein, the material of metal silicide layer for example is a tungsten silicide.
The present invention before forming first clearance wall, removes the segment conductor layer on top and the sidewall because of in aiming at the contact window processing step voluntarily earlier, to reserve bigger space on the sidewall of component structure.Formed first clearance wall can have bigger thickness after so can making, avoid in the technology of aiming at contact window voluntarily, make the conductor clearance wall expose because of first clearance wall is removed, and then cause follow-up conductor clearance wall to contact and cause problem of short-circuit with conducting elements such as contact holes.In addition, the present invention has also increased the feasibility of dwindling component size.
For above and other objects of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A to Fig. 1 C is the existing flow process profile of aiming at the manufacture method of contact window voluntarily.
Fig. 2 A to Fig. 2 E is the flow process profile according to the manufacture method of aiming at contact window voluntarily that embodiments of the invention illustrated.
Fig. 3 is the generalized section according to the semiconductor element that embodiments of the invention illustrated.
Fig. 4 illustrates the generalized section into a kind of plough groove type element.
The simple symbol explanation
30: semiconductor element
100,200,300,400: substrate
101: region labeling
102,202,302: component structure
104,114,204,204a, 214,304: dielectric layer
106,201,306: doped region
108,206,206a: conductor layer
108a, 206b, 308: conductor clearance wall
110: silicon nitride layer
110a, 112,210,212,310,312: clearance wall
116,216: contact window
208,208a: the photoresist layer of patterning
301,402: groove
404: the control grid
406: floating grid
408: tunneling oxide layer
410: dielectric layer between grid
412: source/drain regions
Embodiment
Fig. 2 A to Fig. 2 E is the flow process profile according to the manufacture method of aiming at contact window voluntarily that embodiments of the invention illustrated.Please refer to Fig. 2 A, at first, provide a substrate 200, the doped region 201 that has been formed with a plurality of component structures 202 in the substrate 200 and has been positioned at its below, and the top of component structure 202 is higher than the surface of substrate 200.Wherein, substrate 200 for example is the substrate of P type, and doped region 201 for example is the doped region with N type ion, and can be used as the usefulness of source electrode.In addition, component structure 202 can be grid structure, conductor structure or plough groove type element.Furtherly, grid structure is made of a dielectric layer and a grid layer at least, and conductor structure is made of a conductor layer at least.In addition, plough groove type element (as shown in Figure 4) is arranged in groove 402, and groove 402 is arranged in substrate 400.This plough groove type element comprises dielectric layer 410 and source/drain regions 412 between control grid 404, a pair of floating grid 406, tunneling oxide layer 408, grid.Then, on the surface of substrate 200 and component structure 202, form the photoresist layer 208 of dielectric layer 204, conductor layer 206 and patterning in regular turn.In one embodiment, conductor layer 206 can be the composite conductor layer, and it is made of polysilicon layer and position metal silicide layer thereon, and the material of metal silicide layer for example is a tungsten silicide.The material of dielectric layer 204 for example is silica, silicon oxide/silicon nitride/silicon oxide or other suitable material.In addition, can also on conductor layer 206, form the usefulness of the thin dielectric layer of one deck as protective layer.
Then, please refer to Fig. 2 B, is mask with the photoresist layer 208 of patterning, carry out etch process, to remove the segment conductor layer 206 on component structure 202 tops and the sidewall, have the conductor layer 206a of part exposed surface with formation, and still possess a part of photoresist layer 208a.Wherein, above-mentioned etch process for example is an anisotropic etching process.
Next, please refer to Fig. 2 C, remove photoresist layer 208a, form clearance wall 210 then on the exposed surface of the exposed sidewall of component structure 202 and conductor layer 206, this gap wall 210 also is covered on the conductor layer 206.Wherein, the material of clearance wall 210 for example is a silicon nitride, and its formation method for example is prior to deposition one deck silicon nitride layer in the substrate 200, carries out then forming clearance wall 210 in component structure 202 sidewalls and conductor layer 206 tops naturally behind the anisotropic etching process.What deserves to be mentioned is, therefore, in the described step of Fig. 2 C, can have bigger space to form the thicker clearance wall of thickness 210 owing in the described step of Fig. 2 B, the conductor layer 206 on component structure 202 sidewalls is eat-back some.
Continuing it, please refer to Fig. 2 D, is mask with clearance wall 210, carry out etch process, removing exposed conductor layer 206a, and expose substrate 200, and make the conductor layer 206a that remains form conductor clearance wall 206b, and form dielectric layer 204a with exposed sidewall.Wherein, above-mentioned etch process for example is an anisotropic etching process.Particularly owing to before be formed with the thicker clearance wall of thickness 210 and be covered in conductor clearance wall 206b top, therefore at the formed conductor clearance wall of this step 206b in follow-up technology, can obtain more protection.Afterwards, on the exposed sidewall of conductor clearance wall 206b, form clearance wall 212.What deserves to be mentioned is that because the thickness of clearance wall 210 is thicker, therefore it has comparatively vertical sidewall at the formed clearance wall of this step 212.
Then, please refer to Fig. 2 E, in substrate 200, form dielectric layer 214.Wherein the material of dielectric layer 214 for example is a silica, and its formation method for example is a chemical vapor deposition method.Afterwards, carry out etch process,, and expose substrate 200 with formation contact window 216 in dielectric layer 214.Wherein, above-mentioned etch process for example is etched in alignment technology voluntarily.
What deserves to be mentioned is, owing in the described step of Fig. 2 B, the segment conductor layer 206 on component structure 202 sidewalls is removed.Therefore, in the described step of Fig. 2 C, can form the thicker clearance wall of thickness 210.So, when carrying out the described technology of aiming at contact window voluntarily of Fig. 2 E, the problem that can avoid conductor clearance wall 206b to expose, thus can avoid conductor clearance wall 206b to contact and cause problem of short-circuit with conducting elements such as follow-up formed contact holes.In addition and since clearance wall 212 its have comparatively vertical sidewall, therefore when carrying out the described technology of aiming at contact window voluntarily of Fig. 2 E, the problem that equally also can avoid conductor clearance wall 206b to expose.
Below explanation is by the structure of method gained of the present invention.
Fig. 3 is the generalized section according to the semiconductor element that embodiments of the invention illustrated.Please refer to Fig. 3, semiconductor element 30 comprises substrate 300, component structure 302, dielectric layer 304, doped region 306, conductor clearance wall 308 and clearance wall 310.
Wherein, above-mentioned substrate 300 has groove 301, and it for example is the substrate of P type.Component structure 302 is disposed in the groove 301, and the top of component structure 302 is higher than the surface of substrate 300.Wherein, component structure 302 for example is grid structure, conductor structure or plough groove type element.Doped region 306 is collocation component structure 302 or product needed and being provided with.Doped region 306 is disposed in the substrate 300 of component structure 302 bottoms, and it for example is the doped region with N type ion, and can be used as the usefulness of source electrode.Conductor clearance wall 308 is disposed on the sidewall of component structure 302 Lower Halves.Clearance wall 310 is disposed at the sidewall of component structure 302 first halves, and covers on the conductor clearance wall 308.Dielectric layer 304 is disposed between conductor clearance wall 308 and the component structure 302, and is disposed between conductor clearance wall 308 and the substrate 300.
In one embodiment, semiconductor element 30 can also have a clearance wall 312, is disposed on the sidewall of conductor clearance wall 308.In one embodiment, the material of above-mentioned dielectric layer 304 for example is silica or silicon oxide/silicon nitride/silicon oxide, the material of clearance wall 310 is a silicon nitride for example, and conductor clearance wall 308 for example is the composite conductor layer, and it for example is polysilicon layer and position metal silicide layer thereon.Wherein, the material of metal silicide layer for example is a tungsten silicide.
What deserves to be mentioned is, in semiconductor element 30, because the thickness of clearance wall 310 is thicker, so can provide more protection to the conductor clearance wall 308 that is positioned at its below.That is to say that if utilize this semiconductor element 30 to carry out follow-up contact window technology, clearance wall 310 can be protected the conductor clearance wall 308 of its below effectively, avoids it to sustain damage.
In sum, aim at voluntarily in the contact window processing step of the present invention, before forming as the clearance wall among Fig. 2 C 210, remove the segment conductor layer on component structure top and the sidewall earlier, in subsequent technique, can there be bigger space to form the thicker clearance wall of thickness, and when aiming at the etching step of contact window voluntarily, the conductor layer that can avoid being positioned at the clearance wall below exposes, and causes conductor layer to contact and problem of short-circuit with other conductor element.In addition, the present invention has also increased the feasibility of dwindling component size.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (20)
1. manufacture method of aiming at contact window voluntarily comprises:
One substrate is provided, be formed with a plurality of component structures in this substrate, and the top of those component structures is higher than the surface of this substrate;
On the surface of this substrate and those component structures, form one first dielectric layer and a conductor layer in regular turn;
Remove top and this conductor layer of the part on the sidewall of those component structures;
On the exposed sidewall of those component structures, form a plurality of first clearance walls;
With those first clearance walls is that mask is removed exposed this conductor layer and this first dielectric layer, and exposes this substrate, and makes this conductor layer that remains form a plurality of conductor clearance walls; And
On the sidewall of those conductor clearance walls, form a plurality of second clearance walls.
2. manufacture method of aiming at contact window voluntarily as claimed in claim 1, the method for wherein removing the top of those component structures and this conductor layer of part on the sidewall comprises carries out anisotropic etching process.
3. manufacture method of aiming at contact window voluntarily as claimed in claim 1, the step of wherein removing this exposed conductor layer and this first dielectric layer comprises carries out anisotropic etching process.
4. manufacture method of aiming at contact window voluntarily as claimed in claim 1, wherein this conductor layer comprises a composite conductor layer.
5. manufacture method of aiming at contact window voluntarily as claimed in claim 4, wherein this composite conductor layer comprises a polysilicon layer and a position metal silicide layer thereon.
6. manufacture method of aiming at contact window voluntarily as claimed in claim 5, wherein the material of this metal silicide layer comprises tungsten silicide.
7. manufacture method of aiming at contact window voluntarily as claimed in claim 1, wherein those component structures are a plough groove type element.
8. manufacture method of aiming at contact window voluntarily as claimed in claim 1, wherein the material of those first clearance walls comprises silicon nitride.
9. manufacture method of aiming at contact window voluntarily as claimed in claim 1, wherein the material of this first dielectric layer comprises silica or silicon oxide/silicon nitride/silicon oxide.
10. manufacture method of aiming at contact window voluntarily as claimed in claim 1 also is included in and forms after those second clearance walls formation one second dielectric layer in this substrate.
11. manufacture method of aiming at contact window voluntarily as claimed in claim 10, also be included in and form after this second dielectric layer, carry out an etch process, in this second dielectric layer, to form a plurality of contact windows, wherein those contact windows are between two adjacent component structures, and expose this substrate, those first clearance walls and those second clearance walls.
12. a semiconductor element comprises:
One substrate, this substrate has a groove;
One element structure is disposed in this groove, and the top of this component structure is higher than the surface of this substrate;
One doped region is disposed in this substrate of this component structure bottom;
One conductor clearance wall is disposed on the sidewall of Lower Half of this component structure;
One first clearance wall is disposed at the sidewall of the first half of this component structure, and covers on this conductor clearance wall; And
One dielectric layer is disposed between this conductor clearance wall and this component structure, and is disposed between this conductor clearance wall and this substrate.
13. semiconductor element as claimed in claim 12 also comprises one second clearance wall, is disposed on the sidewall of this conductor clearance wall.
14. semiconductor element as claimed in claim 12, wherein those component structures comprise grid structure, conductor structure or plough groove type element.
15. semiconductor element as claimed in claim 12, wherein the material of this first clearance wall comprises silicon nitride.
16. semiconductor element as claimed in claim 12, wherein the material of this dielectric layer comprises silica or silicon oxide/silicon nitride/silicon oxide.
17. semiconductor element as claimed in claim 12, wherein this doped region comprises source electrode.
18. semiconductor element as claimed in claim 12, wherein this conductor clearance wall comprises a composite conductor layer.
19. semiconductor element as claimed in claim 18, wherein this composite conductor layer comprises a polysilicon layer and a position metal silicide layer thereon.
20. semiconductor element as claimed in claim 19, wherein the material of this metal silicide layer comprises tungsten silicide.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100920461A CN100424827C (en) | 2005-08-16 | 2005-08-16 | Method for fabricating openings of self aligned contact window, and semiconductor component |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005100920461A CN100424827C (en) | 2005-08-16 | 2005-08-16 | Method for fabricating openings of self aligned contact window, and semiconductor component |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1917147A CN1917147A (en) | 2007-02-21 |
| CN100424827C true CN100424827C (en) | 2008-10-08 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2005100920461A Expired - Fee Related CN100424827C (en) | 2005-08-16 | 2005-08-16 | Method for fabricating openings of self aligned contact window, and semiconductor component |
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| Country | Link |
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| CN (1) | CN100424827C (en) |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5158910A (en) * | 1990-08-13 | 1992-10-27 | Motorola Inc. | Process for forming a contact structure |
| US5817562A (en) * | 1997-01-24 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) |
| US6165879A (en) * | 1999-10-26 | 2000-12-26 | United Microelectronics Corp. | Method for improving manufacturing process of self-aligned contact |
| CN1148788C (en) * | 1999-12-08 | 2004-05-05 | 三星电子株式会社 | Semiconductor device having self-aligned contact structure and methods of forming same |
| US20050095797A1 (en) * | 2003-10-29 | 2005-05-05 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with use of partial gate recessing process |
-
2005
- 2005-08-16 CN CNB2005100920461A patent/CN100424827C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5158910A (en) * | 1990-08-13 | 1992-10-27 | Motorola Inc. | Process for forming a contact structure |
| US5817562A (en) * | 1997-01-24 | 1998-10-06 | Taiwan Semiconductor Manufacturing Company, Ltd | Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC) |
| US6165879A (en) * | 1999-10-26 | 2000-12-26 | United Microelectronics Corp. | Method for improving manufacturing process of self-aligned contact |
| CN1148788C (en) * | 1999-12-08 | 2004-05-05 | 三星电子株式会社 | Semiconductor device having self-aligned contact structure and methods of forming same |
| US20050095797A1 (en) * | 2003-10-29 | 2005-05-05 | Hynix Semiconductor Inc. | Method for fabricating semiconductor device with use of partial gate recessing process |
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| Publication number | Publication date |
|---|---|
| CN1917147A (en) | 2007-02-21 |
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Granted publication date: 20081008 |