CN100426067C - Drive circuit of liquid crystal display apparatus - Google Patents
Drive circuit of liquid crystal display apparatus Download PDFInfo
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- CN100426067C CN100426067C CNB200610148621XA CN200610148621A CN100426067C CN 100426067 C CN100426067 C CN 100426067C CN B200610148621X A CNB200610148621X A CN B200610148621XA CN 200610148621 A CN200610148621 A CN 200610148621A CN 100426067 C CN100426067 C CN 100426067C
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Abstract
This invention relates to drive circuit, which comprises multiple drive circuit units, wherein, each drive unit comprises input unit, output unit, first control unit, second control unit and lift circuit; each drive circuit receives initial signal and sequence signal to output signals to next drive circuit unit and to release summed charge and to output signals through first and second control units and lift circuit.
Description
Technical field
The invention relates to a kind of driving circuit, and particularly relevant for a kind of about LCD drive circuits.
Background technology
Scientific and technological industry prosperity in recent years, each electronic product are maked rapid progress especially.Wherein because LCD has slimming, low power consumption, and can with advantage such as manufacture of semiconductor technical compatibility, in the short time, extended to the application of each scope, even become the main flow of flat-panel screens.And in LCD, one of gordian technique that driving circuit is important often.Therefore, how driving circuit is improved and become problem demanding prompt solution.
In the driving circuit of the LCD that develops recently, its practice is to make the driving circuit that comprises a plurality of drive circuit units on glass substrate, and utilize these drive circuit units in regular turn output drive signal to sweep trace, so just can replace and use general drive integrated circult, and then save the expensive cost that uses drive integrated circult.Yet such practice can produce charges accumulated, and then cause driving circuit can't export stable drive signal in the process of driving circuit operation in circuit.
The known practice is the drive circuit unit that the output signal of drive circuit unit is fed back to upper level, with charges accumulated in the release upper level drive circuit unit, and the output signal of stable upper level drive circuit unit.But along with the size of LCD is more and more big, thin film transistor (TFT) in order to charging also becomes big thereupon, and this moment, the load of circuit also and then increased, and makes also to produce too much stored charge in the circuit, and then cause the operating delay of driving circuit and the maloperation of whole driving circuit.
Therefore, be necessary to propose a kind of driving circuit, can avoid the maloperation of accumulation of too much electric charge and driving circuit.
Summary of the invention
The objective of the invention is is providing a kind of driving circuit, solving the problem of too much stored charge, and the drive signal of stable output, to avoid the maloperation of driving circuit.
According to above-mentioned purpose of the present invention, a kind of driving circuit is proposed.According to one embodiment of the invention, this driving circuit is controlled by clock signal, to drive the multi-strip scanning line of LCD.This driving circuit comprises a plurality of drive circuit units that connect in proper order, and wherein each drive circuit unit comprises input block, output unit, first control module, second control module and draws and fall circuit.Input block receives and opens the beginning signal, to produce first signal.And output unit couples input block, and receives the clock signal and first signal, with output signal output.In addition, first control module couples input block, output unit and voltage source, and receives the output signal of next stage drive circuit unit.Second control module then couples input block, output unit and voltage source, and receives the output signal of secondary drive circuit unit down.In addition, draw and fall circuit and then couple output unit and voltage source.
By using above-mentioned driving circuit, can avoid accumulating the maloperation that causes, and drive signal is stably exported because of electric charge.
Description of drawings
For above and other objects of the present invention, feature, advantage and embodiment can be become apparent, appended graphic being described in detail as follows:
Fig. 1 is the synoptic diagram that illustrates according to the drive circuit unit structure of first embodiment of the invention.
Fig. 2 is the synoptic diagram that illustrates according to the drive circuit unit structure of second embodiment of the invention.
Fig. 3 is the synoptic diagram that illustrates according to the drive circuit unit structure of third embodiment of the invention.
Fig. 4 is the sequential chart of operating in a kind of drive circuit unit that illustrates according to one embodiment of the invention.
Fig. 5 is the synoptic diagram that illustrates according to the drive circuit unit structure of fourth embodiment of the invention.
Fig. 6 is the synoptic diagram that illustrates according to the drive circuit unit structure of fifth embodiment of the invention.
Fig. 7 is the synoptic diagram that illustrates according to the drive circuit unit structure of sixth embodiment of the invention.
Fig. 8 is the sequential chart of operating in the another kind of drive circuit unit that illustrates according to another embodiment of the present invention.
Fig. 9 is the synoptic diagram that illustrates according to a kind of display panels of one embodiment of the invention.
[main element label declaration]
100,100a～100e, 500: drive circuit unit
102,402: input block
104,404: output unit 110,410: draw and fall circuit
106,406: the first control modules 112,412: positive draws and falls circuit
108,108a, 108b, 408,408a, 114,414: circuit falls in anti-phase drawing
408b: 502: the three control modules of second control module
CK: positive clock signal ST
N: N level carry signal
XCK: anti-phase clock signal SD
N: N level drive signal
FS: first signal M1～M18: transistor
VSS: voltage source
Embodiment
The present invention proposes a kind of driving circuit, in order to solving the problem of too much stored charge, and the drive signal of stable output, use the maloperation of avoiding driving circuit.
This driving circuit is that wherein driving circuit also comprises a plurality of drive circuit units that connect in proper order, and the structure of each drive circuit unit is all identical by the multi-strip scanning line of clock signal control with the driving LCD.And clock signal is divided into positive clock signal CK and anti-phase clock signal XCK, and two signals phase place is opposite each other.Wherein, appoint two adjacent drive circuit units, one of them receives positive clock signal CK, and another then receives anti-phase clock signal XCK.According to an embodiment, if the drive circuit unit of N level receives positive clock signal CK, the drive circuit unit of (N+1) level and (N-1) level then receives anti-phase clock signal XCK.
Please refer to Fig. 1, is the synoptic diagram that illustrates according to the drive circuit unit structure of first embodiment of the invention.In the present embodiment, the drive circuit unit 100 with the N level is an example.This drive circuit unit 100 comprises input block 102, output unit 104, first control module 106, second control module 108 and draws and fall circuit 110.Be in the present embodiment of example with N stage drive circuit unit 100, output unit 104 is in order to receiving positive clock signal CK, and output is at the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace.And input block 102 is in order to receiving by prime, i.e. (N-1) level, the drive signal SD that drive circuit unit is exported
N-1, and with it as the corresponding levels, i.e. N level, open the beginning signal, and input block 102 couples with output unit 104, and produces the first signal FS and be sent in the output unit 104.In addition, first control module 106 couples input block 102, output unit 104 and voltage source V SS, and receives next stage, i.e. (N+1) level, the drive signal SD of drive circuit unit output
N+1And second control module 108 also couples input block 102, output unit 104 and voltage source V SS, receives in addition secondary down, i.e. (N+2) level, the drive signal SD of drive circuit unit output
N+2In addition, draw and fall circuit 110 and also be coupled to input block 102, output unit 104 and voltage source V SS, use and stablize the drive signal SD at the corresponding levels that output unit 104 is exported
N
Be to be example with N stage drive circuit unit 100 in the present embodiment, wherein input block 102 comprises transistor M1, and wherein the gate terminal of transistor M1 and the first source-drain electrode end all receive by prime, i.e. (N-1) level, the drive signal SD that drive circuit unit is exported
N-1, and its second source-drain electrode end is in order to producing the first signal FS, and be sent in the output unit 104.And output unit 104 comprises transistor M2, wherein the gate terminal of transistor M2 couples the second source-drain electrode end of transistor M1 and receives the first signal FS, and its first source-drain electrode end is in order to receive positive clock signal CK, and its second source-drain electrode end is in order to export the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and this drive signal SD
NAlso be sent to next stage, promptly (N+1) stage drive circuit unit is as drive signal.
In addition, first control module 106 comprises transistor M3 and transistor M4, and wherein the gate terminal of transistor M3 and M4 is coupled to each other and receives next stage, i.e. the drive signal SD that exported of (N+1) stage drive circuit unit
N+1, and the second source-drain electrode end of transistor M3 and M4 all couples voltage source V SS, and the first source-drain electrode end of transistor M3 and the gate terminal of transistor M2 couple, the first source-drain electrode end of transistor M4 then couples with the second source-drain electrode end of transistor M2.
The operational scenario of drive circuit unit 100 below will be described in the present embodiment.Fig. 4 is the sequential chart of operating in a kind of drive circuit unit that illustrates according to one embodiment of the invention.Please be simultaneously with reference to Fig. 1 and Fig. 4, and be example with N stage drive circuit unit 100.When time t1, by prime, i.e. the drive signal SD that exported of (N-1) stage drive circuit unit
N-1Be high level state.This drive signal SD wherein
N-1Be sent to the gate terminal and the first source-drain electrode end of transistor M1 simultaneously, use turn-on transistor M1, and by transistor M1, with the drive signal SD of first source-drain electrode termination receipts
N-1Be sent to the second source-drain electrode end, with as the first signal FS, and be sent to transistor M2.At this moment, connect because the Q node among Fig. 1 has many element load, so the current potential of Q node can present the situation of slow rising as shown in Figure 4 according to the first signal FS.
Then when time t2, positive clock signal CK switches to high level state by end level state, and be sent to the first source-drain electrode end of transistor M2, and because of the current potential of Q node rises to high level state, cause transistor M2 to be unlocked, and by transistor M2 output positive clock signal CK, as the corresponding levels, i.e. the drive signal SD of N level
N, with the sweep trace in the driving LCD, and this drive signal SD
NAlso be sent to next stage, with as next stage, i.e. the drive signal of (N+1) stage drive circuit unit.
Then when time t3, (N+1) stage drive circuit unit wherein, because of receiving the corresponding levels, i.e. the N stage drive circuit unit output drive signal SD of institute
NAnd the drive signal SD that produces
N+1, can be fed the common joint place of transistor M3 and M4 to the N stage drive circuit unit, make transistor M3 and M4 be unlocked, discharging the stored charge of Q node, and stabilized driving signal SD
N, to avoid the maloperation of circuit.
Similarly, when time t4, (N+2) stage drive circuit unit wherein is because of receiving the drive signal SD of (N+1) stage drive circuit unit output
N+1The drive signal SD that is produced
N+2, also can be fed the gate terminal of transistor M5 to the N stage drive circuit unit, make transistor M5 be unlocked, and discharge the stored charge of Q node, to avoid the maloperation of circuit.
Please refer to Fig. 2, is the synoptic diagram that illustrates according to the drive circuit unit structure of second embodiment of the invention.In the present embodiment, same drive circuit unit 100a with the N level is an example.This drive circuit unit 100a comprises the second control module 108a and input block as shown in Figure 1 102, output unit 104, first control module 106 and draws and fall circuit 110, and receive prime by input block 102 equally, promptly (N-1) level, the drive signal SD that drive circuit unit is exported
N-1, receive positive clock signal CK by output unit 104, and output is at the corresponding levels, i.e. N level, a drive signal SD
NTo sweep trace.And first control module 106 couples input block 102, output unit 104 and voltage source V SS equally, and receives next stage, i.e. (N+1) level, the drive signal SD of drive circuit unit output
N+1In addition, the second control module 108a couples input block 102, output unit 104 and voltage source V SS too, receives in addition secondary down, i.e. (N+2) level, the drive signal SD of drive circuit unit output
N+2And draw and fall circuit 110 and be coupled to input block 102, output unit 104 and voltage source V SS too, use and stablize the drive signal SD at the corresponding levels that output unit 104 is exported
N
Be to be example with N stage drive circuit unit 100a in the present embodiment, wherein input block 102 comprises transistor M1 equally, and receives by prime, i.e. (N-1) level, the drive signal SD that drive circuit unit is exported
N-1, be sent in the output unit 104 to produce the first signal FS.And output unit 104 comprises transistor M2 equally, and receives the first signal FS and positive clock signal CK, to export the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and this drive signal SD
NAlso be sent to next stage, promptly (N+1) stage drive circuit unit is as drive signal.
In addition, first control module 106 comprises transistor M3 and transistor M4 equally, and wherein the gate terminal of transistor M3 and M4 is coupled to each other and receives next stage, i.e. the drive signal SD that exported of (N+1) stage drive circuit unit
N+1, and the second source-drain electrode end of transistor M3 and M4 all couples voltage source V SS.And the first source-drain electrode end of transistor M3 and the gate terminal of transistor M2 couple, and the first source-drain electrode end of transistor M4 then couples with the second source-drain electrode end of transistor M2.
The second control module 108a then comprises transistor M6, and wherein the gate terminal of transistor M6 receives secondary down, i.e. the drive signal SD that exported of (N+2) stage drive circuit unit
N+2, and the second source-drain electrode end of its first source-drain electrode end and transistor M2 couples, its second source-drain electrode end couples voltage source V SS.In addition, draw and fall circuit 110 and comprise positive equally and draw and fall circuit 112 and circuit 114 falls in anti-phase drawing, wherein positive draws and falls circuit 112 and anti-phase drawing fallen circuit 114 gate terminal, the second source-drain electrode end and voltage source V SS same and transistor M2 and coupled, and wherein positive draws and falls circuit 112 and stablize drive signal SD at the corresponding levels according to positive clock signal CK
N, anti-phase drawing fallen circuit 114 and stablized drive signal SD at the corresponding levels according to anti-phase clock signal XCK
N
The operational scenario of drive circuit unit 100a, and the operational scenario of its operational scenario in first embodiment below will be described in the present embodiment.Please be simultaneously with reference to Fig. 2 and Fig. 4, and be example with N stage drive circuit unit 100a equally.When time t1, by prime, promptly (N-1) level, the drive signal SD that drive circuit unit is exported
N-1Be high level state.This drive signal SD wherein
N-1Be sent to the gate terminal and the first source-drain electrode end of transistor M1 simultaneously, use turn-on transistor M1, and by transistor M1, with the drive signal SD of first source-drain electrode termination receipts
N-1Be sent to the second source-drain electrode end, with as the first signal FS, and be sent to transistor M2.At this moment, connect because the Q node among Fig. 2 has many element load, so the current potential of Q node can present the situation of slow rising as shown in Figure 4 according to the first signal FS.
Then when time t2, positive clock signal CK switches to high level state by end level state, and be sent to the first source-drain electrode end of transistor M2, and because of the current potential of Q node rises to high level state, cause transistor M2 to be unlocked, and by transistor M2 output positive clock signal CK, as the corresponding levels, i.e. the drive signal SD of N level
N, with the sweep trace in the driving LCD, and this drive signal SD
NAlso be sent to next stage, with as next stage, i.e. the drive signal of (N+1) stage drive circuit unit.
Then when time t3, (N+1) stage drive circuit unit wherein, because of receiving the corresponding levels, i.e. the drive signal SD that exported of N stage drive circuit unit
NAnd the drive signal SD that produces
N+1, can be fed the common joint place of transistor M3 and M4 to the N stage drive circuit unit, make transistor M3 and M4 be unlocked, discharging the stored charge of Q node, and stabilized driving signal SD
N, to avoid the maloperation of circuit.
Similarly, when time t4, (N+2) stage drive circuit unit wherein is because of receiving the drive signal SD of (N+1) stage drive circuit unit output
N+1The drive signal SD that is produced
N+2, also can be fed the gate terminal of transistor M6 to the N stage drive circuit unit, make transistor M6 be unlocked, and the drive signal SD of stable output at the corresponding levels
N, to avoid the maloperation of circuit.
Please refer to Fig. 3, is the synoptic diagram that illustrates according to the drive circuit unit structure of third embodiment of the invention.In the present embodiment, same drive circuit unit 100b with the N level is an example.This drive circuit unit 100b comprises the second control module 108b and input block as shown in Figure 1 102, output unit 104, first control module 106 and draws and fall circuit 110, and receive by prime by input block 102 equally, promptly (N-1) level, the drive signal SD that drive circuit unit is exported
N-1, receive positive clock signal CK by output unit 104, and output is at the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace.And first control module 106 couples input block 102, output unit 104 and voltage source V SS equally, and receives next stage, i.e. (N+1) level, the drive signal SD of drive circuit unit output
N+1In addition, the second control module 108b couples input block 102, output unit 104 and voltage source V SS too, receives in addition secondary down, i.e. (N+2) level, the drive signal SD of drive circuit unit output
N+2And draw and fall circuit 110 and be coupled to input block 102, output unit 104 and voltage source V SS too, use and stablize the drive signal SD at the corresponding levels that output unit 104 is exported
N
Be to be example with N stage drive circuit unit 100b in the present embodiment, wherein input block 102 comprises transistor M1 equally, and receives by prime, i.e. (N-1) level, the drive signal SD that drive circuit unit is exported
N-1, be sent in the output unit 104 to produce the first signal FS.And output unit 104 comprises transistor M2 equally, and receives the first signal FS and positive clock signal CK, to export the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and this drive signal SD
NAlso be sent to next stage, promptly (N+1) stage drive circuit unit is as drive signal.
In addition, first control module 106 comprises transistor M3 and transistor M4 equally, and wherein the gate terminal of transistor M3 and M4 is coupled to each other and receives next stage, i.e. the drive signal SD that exported of (N+1) stage drive circuit unit
N+1, and the second source-drain electrode end of transistor M3 and M4 all couples voltage source V SS.And the first source-drain electrode end of transistor M3 and the gate terminal of transistor M2 couple, and the first source-drain electrode end of transistor M4 then couples with the second source-drain electrode end of transistor M2.
The second control module 108b then comprises transistor M7 and transistor M8, and wherein the gate terminal of transistor M7 and M8 all receives down secondary, i.e. the drive signal SD that exported of (N+2) stage drive circuit unit
N+2, and the second source-drain electrode end of transistor M7 and M8 all couples voltage source V SS.And the first source-drain electrode end of transistor M7 and the gate terminal of transistor M2 couple, and the first source-drain electrode end of transistor M8 and the second source-drain electrode end of transistor M2 couple.In addition, draw and fall circuit 110 and comprise positive equally and draw and fall circuit 112 and circuit 114 falls in anti-phase drawing, wherein positive draws and falls circuit 112 and anti-phase drawing fallen circuit 114 gate terminal, the second source-drain electrode end and voltage source V SS same and transistor M2 and coupled, and wherein positive draws and falls circuit 112 and stablize drive signal SD at the corresponding levels according to positive clock signal CK
N, anti-phase drawing fallen circuit 114 and stablized drive signal SD at the corresponding levels according to anti-phase clock signal XCK
N
The operational scenario of drive circuit unit 100b, and the operational scenario of its operational scenario in first embodiment below will be described in the present embodiment.Please be simultaneously with reference to Fig. 3 and Fig. 4, and be example with N stage drive circuit unit 100b equally.When time t1, by prime, promptly (N-1) level, the drive signal SD that drive circuit unit is exported
N-1Be high level state.This drive signal SD wherein
N-1Be sent to the gate terminal and the first source-drain electrode end of transistor M1 simultaneously, use turn-on transistor M1, and by transistor M1, with the drive signal SD of first source-drain electrode termination receipts
N-1Be sent to the second source-drain electrode end, with as the first signal FS, and be sent to transistor M2.At this moment, connect because the Q node among Fig. 3 has many element load, so the current potential of Q node can present the situation of slow rising as shown in Figure 4 according to the first signal FS.
Then when time t2, positive clock signal CK switches to high level state by end level state, and be sent to the first source-drain electrode end of transistor M2, and because of the current potential of Q node rises to high level state, cause transistor M2 to be unlocked, and by transistor M2 output positive clock signal CK, as the corresponding levels, i.e. the drive signal SD of N level
N, with the sweep trace in the driving LCD, and this drive signal SD
NAlso be sent to next stage, with as next stage, i.e. the drive signal of (N+1) stage drive circuit unit.
Then when time t3, (N+1) stage drive circuit unit wherein, because of receiving the corresponding levels, i.e. the drive signal SD that exported of N stage drive circuit unit
NAnd the drive signal SD that produces
N+1, can be fed the common joint place of transistor M3 and M4 to the N stage drive circuit unit, make transistor M3 and M4 be unlocked, discharging the stored charge of Q node, and stabilized driving signal SD
N, to avoid the maloperation of circuit.
Similarly, when time t4, (N+2) stage drive circuit unit wherein is because of receiving the drive signal SD of (N+1) stage drive circuit unit output
N+1The drive signal SD that is produced
N+2, also can be fed the gate terminal of transistor M7 and M8 to the N stage drive circuit unit, make transistor M7 and M8 be unlocked, and discharge the stored charge of Q node, and the drive signal SD of stable output at the corresponding levels
N, to avoid the maloperation of circuit.
Please refer to Fig. 5, is the synoptic diagram that illustrates according to the drive circuit unit structure of fourth embodiment of the invention.In the present embodiment, the drive circuit unit 100c with the N level is an example.This drive circuit unit 100c comprises input block 402, output unit 404, first control module 406, second control module 408 and draws and fall circuit 410.Be in the present embodiment of example with N stage drive circuit unit 100c, output unit 404 is in order to receiving positive clock signal CK, and output is at the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and output carry signal ST
NTo next stage, promptly (N+1) level, drive circuit unit, in order to drive signal as next stage.And input block 402 is in order to receiving by prime, i.e. (N-1) level, the carry signal ST that drive circuit unit is exported
N-1, and with it as the corresponding levels, i.e. N level, open the beginning signal, and input block 402 couples with output unit 404, and produces the first signal FS and be sent in the output unit 404.In addition, first control module 406 couples input block 402, output unit 404 and voltage source V SS, and receives next stage, i.e. (N+1) level, the carry signal ST of drive circuit unit output
N+1And second control module 408 also couples input block 402, output unit 404 and voltage source V SS, receives in addition secondary down, i.e. (N+2) level, the carry signal ST of drive circuit unit output
N+2In addition, draw and fall circuit 410 and also be coupled to input block 402, output unit 404 and voltage source V SS, use and stablize the drive signal SD at the corresponding levels that output unit 404 is exported
N
Be to be example in the present embodiment with N stage drive circuit unit 100c, wherein input block 402 comprises transistor M9, wherein the gate terminal of transistor M9 and the first source-drain electrode end all receive by prime, promptly (N-1) level, the carry signal ST that drive circuit unit is exported
N-1, and its second source-drain electrode end is in order to producing the first signal FS, and be sent in the output unit 404.And output unit 404 comprises transistor M10 and transistor M11, wherein the gate terminal of transistor M10 and M11 all couples the second source-drain electrode end of transistor M9, and receive the first signal FS, and the first source-drain electrode end of transistor M10 and M11 is all in order to receive positive clock signal CK.And the second source-drain electrode end of transistor M10 output is at the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and the second source-drain electrode end of transistor M11 output is at the corresponding levels, i.e. N level, carry signal ST
NTo next stage, promptly (N+1) stage drive circuit unit is as drive signal.
In addition, first control module 406 comprises transistor M12 and transistor M13, and wherein the gate terminal of transistor M12 and M13 is coupled to each other and receives next stage, i.e. the carry signal ST that exported of (N+1) stage drive circuit unit
N+1, and the second source-drain electrode end of transistor M12 and M13 all couples voltage source V SS, and the first source-drain electrode end of transistor M12 and the gate terminal of transistor M11 couple, the first source-drain electrode end of transistor M13 then couples with the second source-drain electrode end of transistor M10.
The operational scenario of drive circuit unit 100c below will be described in the present embodiment.Fig. 8 is the sequential chart of operating in the another kind of drive circuit unit that illustrates according to another embodiment of the present invention.Please be simultaneously with reference to Fig. 5 and Fig. 8, and be example with N stage drive circuit unit 100c.When time t1, by prime, i.e. the carry signal ST that exported of (N-1) stage drive circuit unit
N-1Be high level state.This drive signal SD wherein
N-1Be sent to the gate terminal and the first source-drain electrode end of transistor M9 simultaneously, use turn-on transistor M9, and by transistor M9, with the drive signal SD of first source-drain electrode termination receipts
N-1Be sent to the second source-drain electrode end, with as the first signal FS, and be sent to transistor M10 and M11.At this moment, connect because the Q node among Fig. 5 has many element load, so the current potential of Q node can present the situation of slow rising as shown in Figure 8 according to the first signal FS.
Then when time t2, positive clock signal CK switches to high level state by end level state, and be sent to the first source-drain electrode end of transistor M10 and M11, and because of the current potential of Q node rises to high level state, cause transistor M10 and M11 to be unlocked, and by transistor M10 output positive clock signal CK, as the corresponding levels, i.e. the drive signal SD of N level
N, driving the sweep trace in the LCD, and transistor M11 also exports positive clock signal CK, as the corresponding levels, i.e. and the carry signal ST of N level
N, to be sent to next stage, promptly (N+1) stage drive circuit unit is as drive signal.
Then when time t3, wherein (N+1) stage drive circuit unit is because of receiving the corresponding levels, i.e. the carry signal ST that exported of N stage drive circuit unit
NAnd the carry signal ST that produces
N+1, can be fed the common joint place of transistor M12 and M13 to the N stage drive circuit unit, make transistor M12 and M13 be unlocked, discharging the stored charge of Q node, and stabilized driving signal SD
N, to avoid the maloperation of circuit.
Similarly, when time t4, (N+2) stage drive circuit unit wherein is because of receiving the carry signal ST of (N+1) stage drive circuit unit output
N+1The carry signal ST that is produced
N+2, also can be fed the gate terminal of transistor M14 to the N stage drive circuit unit, make transistor M14 be unlocked, and discharge the stored charge of Q node, to avoid the maloperation of circuit.
Please refer to Fig. 6, is the synoptic diagram that illustrates according to the drive circuit unit structure of fifth embodiment of the invention.In the present embodiment, same drive circuit unit 100d with the N level is an example.This drive circuit unit 100d comprises the second control module 408a and input block as shown in Figure 4 402, output unit 404, first control module 406 and draws and fall circuit 410, and receive by prime by input block 402 equally, promptly (N-1) level, the carry signal ST that drive circuit unit is exported
N-1, and receive positive clock signal CK, and output is at the corresponding levels by output unit 404, i.e. N level, drive signal SD
NTo sweep trace, and output carry signal ST
NTo next stage, promptly (N+1) level, drive circuit unit, with drive signal as next stage.And first control module 406 couples input block 402, output unit 404 and voltage source V SS equally, and receives next stage, i.e. (N+1) level, the carry signal ST of drive circuit unit output
N+1In addition, the second control module 408a couples input block 402, output unit 404 and voltage source V SS too, receives in addition secondary down, i.e. (N+2) level, the carry signal ST of drive circuit unit output
N+2And draw and fall circuit 410 and be coupled to input block 402, output unit 404 and voltage source V SS too, use and stablize the drive signal SD at the corresponding levels that output unit 404 is exported
N
Be to be example with N stage drive circuit unit 100d in the present embodiment, wherein input block 402 comprises transistor M9 equally, and receives by prime, i.e. (N-1) level, the carry signal ST that drive circuit unit is exported
N-1, be sent in the output unit 404 to produce the first signal FS.And output unit 404 comprises transistor M10 equally and M11 couples transistor M9, and receives the first signal FS and positive clock signal CK, to export the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and output is at the corresponding levels, i.e. N level, carry signal ST
NTo next stage, promptly (N+1) stage drive circuit unit is as drive signal.
In addition, first control module 406 comprises transistor M12 and transistor M13 equally, and wherein the gate terminal of transistor M12 and M13 is coupled to each other and receives next stage, i.e. the carry signal ST that exported of (N+1) stage drive circuit unit
N+1, and the second source-drain electrode end of transistor M12 and M13 all couples voltage source V SS.And the first source-drain electrode end of transistor M12 and the gate terminal of transistor M11 couple, and the first source-drain electrode end of transistor M13 then couples with the second source-drain electrode end of transistor M10.
The second control module 408a then comprises transistor M15, and wherein the gate terminal of transistor M15 receives secondary down, i.e. (N+2) level, the carry signal ST of drive circuit unit output
N+2, and the second source-drain electrode end of its first source-drain electrode end and transistor M10 couples, its second source-drain electrode end couples voltage source V SS.In addition, draw and fall circuit 410 and comprise positive equally and draw and fall circuit 412 and circuit 414 falls in anti-phase drawing, wherein positive draws and falls circuit 412 and anti-phase drawing fallen circuit 414 same and the gate terminal of transistor M11, the second source-drain electrode end and the voltage source V SS of transistor M10 and coupled, and wherein positive draws and falls circuit 412 and stablize drive signal SD at the corresponding levels according to positive clock signal CK
N, and anti-phase drawing fallen circuit 414 and stablized drive signal SD at the corresponding levels according to anti-phase clock signal XCK
N
The operational scenario of drive circuit unit 100d, and the operational scenario of its operational scenario in the 4th embodiment below will be described in the present embodiment.Please be simultaneously with reference to Fig. 6 and Fig. 8, and be example with N stage drive circuit unit 100d equally.1 o'clock time, by prime, i.e. the carry signal ST that exported of (N-1) stage drive circuit unit
N-1Be high level state.This drive signal SD wherein
N-1Be sent to the gate terminal and the first source-drain electrode end of transistor M9 simultaneously, use turn-on transistor M9, and by transistor M9, with the drive signal SD of first source-drain electrode termination receipts
N-1Be sent to the second source-drain electrode end, with as the first signal FS, and be sent to transistor M10 and M11.At this moment, connect because the Q node among Fig. 6 has many element load, so the current potential of Q node can present the situation of slow rising as shown in Figure 8 according to the first signal FS.
Then when time t2, positive clock signal CK switches to high level state by end level state, and be sent to the first source-drain electrode end of transistor M10 and M11, and because of the current potential of Q node rises to high level state, cause transistor M10 and M11 to be unlocked, and by transistor M10 output positive clock signal CK, as the corresponding levels, i.e. the drive signal SD of N level
N, driving the sweep trace in the LCD, and transistor M11 also exports positive clock signal CK, as the corresponding levels, i.e. and the carry signal ST of N level
NTo be sent to next stage, promptly (N+1) stage drive circuit unit is as drive signal.
Then when time t3, (N+1) stage drive circuit unit wherein, because of receiving the corresponding levels, i.e. N level, the carry signal ST of drive circuit unit output
NAnd the carry signal ST that produces
N+1, can be fed the common joint place of transistor M12 and M13 to the N stage drive circuit unit, make transistor M12 and M13 be unlocked, discharging the stored charge of Q node, and stabilized driving signal SD
N, to avoid the maloperation of circuit.
Similarly, when time t4, (N+2) stage drive circuit unit wherein is because of receiving the carry signal ST of (N+1) stage drive circuit unit output
N+1The carry signal ST that is produced
N+2, also can be fed the gate terminal of transistor M15 to the N stage drive circuit unit, make transistor M15 be unlocked, and the drive signal SD of stable output at the corresponding levels
N, to avoid the maloperation of circuit.
Please refer to Fig. 7, is the synoptic diagram that illustrates according to the drive circuit unit structure of sixth embodiment of the invention.In the present embodiment, same drive circuit unit 100e with the N level is an example.This drive circuit unit 100e comprises the second control module 408b and input block as shown in Figure 4 402, output unit 404, first control module 406 and draws and fall circuit 410, and receive by prime by input block 402 equally, promptly (N-1) level, the carry signal ST that drive circuit unit is exported
N-1, and receive positive clock signal CK, and output is at the corresponding levels by output unit 404, i.e. N level, drive signal SD
NTo sweep trace, and output carry signal ST
NTo next stage, promptly (N+1) level, drive circuit unit, with drive signal as next stage.And first control module 406 couples input block 402, output unit 404 and voltage source V SS equally, and receives next stage, i.e. (N+1) level, the carry signal ST of drive circuit unit output
N+1In addition, the second control module 408b couples input block 402, output unit 404 and voltage source V SS too, receives in addition secondary down, i.e. (N+2) level, the carry signal ST of drive circuit unit 100e output
N+2And draw and fall circuit 410 and be coupled to input block 402, output unit 404 and voltage source V SS too, use and stablize the drive signal SD at the corresponding levels that output unit 404 is exported
N
Be to be example with N stage drive circuit unit 100e in the present embodiment, input block 402 comprises transistor M9 equally, and receives by prime, i.e. (N-1) level, the carry signal ST that drive circuit unit is exported
N-1, be sent in the output unit 404 to produce the first signal FS.And output unit 404 comprises transistor M10 equally and M11 couples transistor M9, and receives the first signal FS and positive clock signal CK, to export the corresponding levels, i.e. N level, drive signal SD
NTo sweep trace, and output is at the corresponding levels, i.e. N level, carry signal ST
NTo next stage, promptly (N+1) stage drive circuit unit is as drive signal.
In addition, first control module 406 comprises transistor M12 and transistor M13 equally, and wherein the gate terminal of transistor M12 and M13 is coupled to each other and receives next stage, i.e. the carry signal ST that exported of (N+1) stage drive circuit unit
N+1, and the second source-drain electrode end of transistor M12 and M13 all couples voltage source V SS.And the first source-drain electrode end of transistor M12 and the gate terminal of transistor M11 couple, and the first source-drain electrode end of transistor M13 then couples with the second source-drain electrode end of transistor M10.
The second control module 408b then comprises transistor M16 and transistor M17, and wherein the gate terminal of transistor M16 and M17 receives secondary down, i.e. (N+2) level, the carry signal ST of drive circuit unit output
N+2, and the second source-drain electrode end of transistor M16 and M17 all couples voltage source V SS.And the first source-drain electrode end of transistor M16 and the gate terminal of transistor M11 couple, and the first source-drain electrode end of transistor M17 and the second source-drain electrode end of transistor M10 couple.In addition, draw and fall circuit 410 and comprise positive equally and draw and fall circuit 412 and circuit 414 falls in anti-phase drawing, wherein positive draws and falls circuit 412 and anti-phase drawing fallen circuit 414 same and the gate terminal of transistor M11, the second source-drain electrode end and the voltage source V SS of transistor M10 and coupled, and wherein positive draws and falls circuit 412 and stablize drive signal SD at the corresponding levels according to positive clock signal CK
N, and anti-phase drawing fallen circuit 414 and stablized drive signal SD at the corresponding levels according to anti-phase clock signal XCK
N
The operational scenario of drive circuit unit 100e, and the operational scenario of its operational scenario in the 4th embodiment below will be described in the present embodiment.Please be simultaneously with reference to Fig. 7 and Fig. 8, and be example with N stage drive circuit unit 100e equally.When time t1, by prime, i.e. the carry signal ST that exported of (N-1) stage drive circuit unit
N-1Be high level state.This drive signal SD wherein
N-1Be sent to the gate terminal and the first source-drain electrode end of transistor M9 simultaneously, use turn-on transistor M9, and by transistor M9, with the drive signal SD of first source-drain electrode termination receipts
N-1Be sent to the second source-drain electrode end, with as the first signal FS, and be sent to transistor M10 and M11.At this moment, connect because the Q node among Fig. 7 has many element load, so the current potential of Q node can present the situation of slow rising as shown in Figure 8 according to the first signal FS.
Then when time t2, positive clock signal CK switches to high level state by end level state, and be sent to the first source-drain electrode end of transistor M10 and M11, and because of the current potential of Q node rises to high level state, cause transistor M10 and M11 to be unlocked, and by transistor M10 output positive clock signal CK, as the corresponding levels, i.e. the drive signal SD of N level
N, driving the sweep trace in the LCD, and transistor M11 also exports positive clock signal CK, as the corresponding levels, i.e. and the carry signal ST of N level
NTo be sent to next stage, as next stage, promptly (N+1) stage drive circuit unit is as drive signal.
Then when time t3, (N+1) stage drive circuit unit wherein, because of receiving the corresponding levels, i.e. N level, the carry signal ST of drive circuit unit output
NAnd the carry signal ST that produces
N+1, can be fed the common joint place of transistor M12 and M13 to the N stage drive circuit unit, make transistor M12 and M13 be unlocked, discharging the stored charge of Q node, and stabilized driving signal SD
N, to avoid the maloperation of circuit.
Similarly, when time t4, (N+2) stage drive circuit unit wherein is because of receiving the carry signal ST of (N+1) stage drive circuit unit output
N+1The carry signal ST that is produced
N+2, also can be fed the gate terminal of transistor M16 and M17 to the N stage drive circuit unit, make transistor M16 and M17 be unlocked, and discharge the stored charge of Q node, and the drive signal SD of stable output at the corresponding levels
N, to avoid the maloperation of circuit.
Yet except the above embodiments, this driving circuit also can comprise and is arranged in display panels, with respect to a plurality of control modules of an end of this driving circuit, and utilizes these control modules equally as the usefulness of stabilized driving signal.Seeing also Fig. 9, is the synoptic diagram that illustrates according to a kind of display panels of one embodiment of the invention.According to present embodiment, this driving circuit comprises a plurality of drive circuit units 500 of an end that is positioned at display panel, and a plurality of the 3rd control modules 502 that are positioned at the other end of display panel, and these the 3rd control modules 502 couple with drive circuit unit 500 respectively, and receive its drive signal of secondary drive circuit unit 500 outputs down, use the drive signal SD of stabilized driving circuit unit 500 outputs respectively
1... SD
NThe 3rd control module 502 with the N level is an example, is the drive signal SD that receives 500 outputs of N+2 stage drive circuit unit
N+2, to stablize the drive signal SD of N stage drive circuit unit 500 outputs
NWherein, each the 3rd control module 502 all comprises a transistor M18, wherein the gate terminal of transistor M18 is in order to receive down the output signal of secondary drive circuit unit 500, and its first source-drain electrode end couples this drive circuit unit 500, and its second source-drain electrode end couples voltage source V SS.Thus, just can make each transistor M18 be unlocked in regular turn by receiving the drive signal of secondary drive circuit unit 500 outputs down, and the drive signal SD that stabilized driving circuit unit 500 is exported
1... SD
N
By some embodiment of the invention described above as can be known, the drive signal of next stage by drive circuit unit and secondary output is down fed back so far in the drive circuit unit, stored charge in the drive circuit unit can be discharged fully, and the serviceable life of prolongation driving circuit.And, also can stablize output drive signal, drive signal is correctly exported, avoid causing the maloperation of circuit.In addition, if will avoid feeding back to the consume that drive circuit unit causes drive signal because of drive signal, by other embodiment of the invention described above as can be known, also can make each drive circuit unit output carry signal, and the carry signal of next stage by drive circuit unit and secondary output is down fed back so far in the drive circuit unit, stored charge is discharged fully, and prolong the serviceable life of driving circuit.And, also can stablize the drive signal of output, drive signal is correctly exported, avoid causing the maloperation of circuit.
Though the present invention discloses as above with some embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can being used for a variety of modifications and variations, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (19)
1. driving circuit, driving the multi-strip scanning line of LCD, and this driving circuit comprises a plurality of drive circuit units that connect in proper order by clock signal control, and wherein each this drive circuit unit comprises:
Input block receives and opens the beginning signal to produce first signal;
Output unit couples this input block, and receives this clock signal and this first signal with output signal output, and this output signal is sent to the next stage drive circuit unit opens the beginning signal as next stage;
First control module couples this input block, this output unit and voltage source, and receives the output signal of next stage drive circuit unit;
Second control module couples this input block, this output unit and this voltage source, and receives the output signal of secondary drive circuit unit down; And
Draw and fall circuit, couple this input block, this output unit and this voltage source.
2. driving circuit according to claim 1, wherein this output unit also comprises: the first transistor, wherein the gate terminal of this first transistor couples this input block to receive this first signal, the first source-drain electrode termination of this first transistor is received this clock signal, the second source-drain electrode end of this first transistor export this output signal with as the next stage drive circuit unit open the beginning signal, and this output signal is that drive signal is in order to drive this sweep trace.
3. driving circuit according to claim 2, wherein this second control module also comprises: transistor seconds, wherein the gate terminal of this transistor seconds receives the drive signal of secondary drive circuit unit down, the second source-drain electrode end of this transistor seconds couples this voltage source, and the first source-drain electrode end of this transistor seconds couples the gate terminal of this first transistor.
4. driving circuit according to claim 2, wherein this second control module also comprises: the 3rd transistor, wherein the 3rd transistorized gate terminal receives the drive signal of secondary drive circuit unit down, the 3rd transistorized second source-drain electrode end couples this voltage source, and the 3rd transistorized first source-drain electrode end couples the second source-drain electrode end of this first transistor.
5. driving circuit according to claim 2, wherein this second control module also comprises:
The 4th transistor, wherein the 4th transistorized gate terminal receives the drive signal of secondary drive circuit unit down, and the 4th transistorized second source-drain electrode end couples this voltage source, and the 4th transistorized first source-drain electrode end couples the gate terminal of this first transistor; And
The 5th transistor, wherein the 5th transistorized gate terminal receives the drive signal of secondary drive circuit unit down, the 5th transistorized second source-drain electrode end couples this voltage source, and the 5th transistorized first source-drain electrode end couples the second source-drain electrode end of this first transistor.
6. driving circuit according to claim 2, wherein this first control module also comprises:
The 6th transistor, wherein the 6th transistorized gate terminal receives the drive signal of next stage drive circuit unit, and the 6th transistorized second source-drain electrode end couples this voltage source, and the 6th transistorized first source-drain electrode end couples the gate terminal of this first transistor; And
The 7th transistor, wherein the 7th transistorized gate terminal receives the drive signal of next stage drive circuit unit, the 7th transistorized second source-drain electrode end couples this voltage source, and the 7th transistorized first source-drain electrode end couples the second source-drain electrode end of this first transistor.
7. driving circuit according to claim 2, wherein this input block also comprises: the 8th transistor, wherein the 8th transistorized gate terminal and the first source-drain electrode termination are received the drive signal of upper level drive circuit unit, and the 8th transistorized second source-drain electrode end couples the gate terminal of this first transistor.
8. driving circuit according to claim 1, wherein this output unit also comprises:
The 9th transistor, wherein the 9th transistorized gate terminal couples this input block to receive this first signal, the 9th transistorized first source-drain electrode termination is received this clock signal, and the 9th transistorized second source-drain electrode end output drive signal is in order to drive this sweep trace; And
The tenth transistor, wherein the tenth transistorized gate terminal couples this input block to receive this first signal, the tenth transistorized first source-drain electrode termination is received this clock signal, the tenth transistorized second source-drain electrode end is exported this output signal, and this output signal is a carry signal in order to open the beginning signal as the next stage drive circuit unit.
9. driving circuit according to claim 8, wherein this second control module also comprises: the 11 transistor, wherein the 11 transistorized gate terminal receives the carry signal of secondary drive circuit unit down, the 11 transistorized second source-drain electrode end couples this voltage source, and the 11 transistorized first source-drain electrode end couples the tenth transistorized gate terminal.
10. driving circuit according to claim 8, wherein this second control module also comprises: the tenth two-transistor, wherein the gate terminal of the tenth two-transistor receives the carry signal of secondary drive circuit unit down, the second source-drain electrode end of the tenth two-transistor couples this voltage source, and the first source-drain electrode end of the tenth two-transistor couples the 9th transistorized second source-drain electrode end.
11. driving circuit according to claim 8, wherein this second control module also comprises:
The 13 transistor, wherein the 13 transistorized gate terminal receives the carry signal of secondary drive circuit unit down, the 13 transistorized second source-drain electrode end couples this voltage source, and the 13 transistorized first source-drain electrode end couples the tenth transistorized gate terminal; And
The 14 transistor, wherein the 14 transistorized gate terminal receives the carry signal of secondary drive circuit unit down, the 14 transistorized second source-drain electrode end couples this voltage source, and the 14 transistorized first source-drain electrode end couples the 9th transistorized second source-drain electrode end.
12. driving circuit according to claim 8, wherein this first control module also comprises:
The 15 transistor, wherein the 15 transistorized gate terminal receives the carry signal of next stage drive circuit unit, the 15 transistorized second source-drain electrode end couples this voltage source, and the 15 transistorized first source-drain electrode end couples the tenth transistorized gate terminal; And
The 16 transistor, wherein the 16 transistorized gate terminal receives the carry signal of next stage drive circuit unit, the 16 transistorized second source-drain electrode end couples this voltage source, and the 16 transistorized first source-drain electrode end couples the 9th transistorized second source-drain electrode end.
13. driving circuit according to claim 8, wherein this input block also comprises: the 17 transistor, wherein the 17 transistorized gate terminal and the first source-drain electrode termination are received the carry signal of upper level drive circuit unit, and the 17 transistorized second source-drain electrode end couples the tenth transistorized gate terminal.
14. driving circuit according to claim 1, wherein this clock signal also comprises positive clock signal and anti-phase clock signal.
15. driving circuit according to claim 14, wherein this positive clock signal and this anti-phase clock signal are clock signal and phase place is opposite each other.
16. driving circuit according to claim 14 is wherein appointed two adjacent drive circuit units, one of them drive circuit unit receives this positive clock signal, and another drive circuit unit receives this anti-phase clock signal.
17. driving circuit according to claim 14, wherein this draws and falls circuit and comprise also that positive draws and fall circuit and circuit falls in anti-phase drawing, and this positive draws and fall circuit and receive this positive clock signal, and this is anti-phase to draw and fall circuit and receive this anti-phase clock signal.
18. driving circuit according to claim 1, wherein this driving circuit also comprises:
A plurality of the 3rd control modules couple with those drive circuit units respectively, and receive the output signal of secondary drive circuit unit down, and are arranged in the end of display panels with respect to this driving circuit.
19. driving circuit according to claim 18, wherein each the 3rd control module comprises a transistor, wherein this transistorized gate terminal receives the output signal of secondary drive circuit unit down, this transistorized first source-drain electrode end couples this drive circuit unit, and this transistorized second source-drain electrode end couples this voltage source.
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| CNB200610148621XA CN100426067C (en) | 2006-11-14 | 2006-11-14 | Drive circuit of liquid crystal display apparatus |
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| CNB200610148621XA CN100426067C (en) | 2006-11-14 | 2006-11-14 | Drive circuit of liquid crystal display apparatus |
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| CN100426067C true CN100426067C (en) | 2008-10-15 |
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| CN1049755C (en) * | 1993-10-28 | 2000-02-23 | Rca·汤姆森许可公司 | Shift register useful as a select line scanner for a liquid crystal |
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|---|---|
| CN1963608A (en) | 2007-05-16 |
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