CN100431135C - 存储器芯片和使用该芯片的“芯片上芯片”器件及其制造方法 - Google Patents

存储器芯片和使用该芯片的“芯片上芯片”器件及其制造方法 Download PDF

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CN100431135C
CN100431135C CNB021405964A CN02140596A CN100431135C CN 100431135 C CN100431135 C CN 100431135C CN B021405964 A CNB021405964 A CN B021405964A CN 02140596 A CN02140596 A CN 02140596A CN 100431135 C CN100431135 C CN 100431135C
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basic chips
memory chip
memory
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CN1463036A (zh
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浦川幸宏
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Toshiba Corp
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Abstract

在晶片内配置多个基本芯片。基本芯片具有i兆字节的存储容量。借助于划片法，从晶片上切出含有4个基本芯片F的存储器芯片。存储器芯片具有4×i兆字节的存储容量。在构成存储器芯片的4个基本芯片F之间，配置划片线。4个基本芯片F可以分别借助于控制信号改变字构成。

Description

存储器芯片和使用该芯片的“芯片上芯片”器件及其制造方法
技术领域
本发明涉及在半导体芯片上边叠层上具有与其功能不同的功能的别的半导体芯片以构成一个系统的所谓的COC(芯片上芯片)器件和采用把多个芯片放入到一个封装内的办法构成一个系统的MCM(多芯片组件)等构成的SiP(封装内系统)器件。
背景技术
近些年来，把可以用CPU、IP(知识产权)实现的功能、存储器(例如，SRAM、DRAM、闪速存储器)或模拟LSI(例如，RF电路)等混合载置到一个芯片内，在一个芯片内形成系统的所谓的SOC(芯片上系统)技术的研究、开发一直在进行。如果在一个芯片内形成系统，由于就没有必要用外部布线把多个芯片彼此连接起来，故可以实现系统的高性能化和小型化。
但是，要想实现在一个芯片内混合载置多个功能的LSI(以下，叫做SoC)，存在着许多难于解决的问题。
例如，作为SoC的代表性的器件，人们熟知存储器混合载置逻辑LSI和模拟混合载置LSI。在存储器混合载置LSI的情况下，必须给逻辑工艺追加上存储器所特有的工艺(例如，在DRAM的情况下，刻槽/叠层电容器的制造工艺)。此外，在模拟混合载置LSI的情况下，则必须给逻辑工艺追加上模拟电路所特有的工艺(例如，双极晶体管的制造工艺)。
为此，在上述那样的SoC的情况下，存在着其制造工艺(以下，叫做混合载置工艺)将变得复杂而且长，成品率降低或制造成本增大的问题。
此外，SoC由于是使原本用彼此不同的制造工艺形成的多个功能(芯片)单芯片化的器件，故重要的是单芯片化时的混合载置工艺的优化。但是，由于是要把不同的多个制造工艺共通化为一个混合载置工艺，故在共通化之际，当然会出现在器件的性能或集成度等方面必须进行折中妥协的问题。
例如，在DRAM混合载置逻辑LSI中，就要以逻辑工艺为基础，给之追加上DRAM所特有的工艺。在这里，在逻辑工艺中，应含有目的为降低MOS晶体管的栅极、源极、漏极的电阻的自对准硅化物(Saliside)工艺。另一方面，在DRAM工艺中，则具备目的为使存储单元高集成化的SAC(自对准接触)工艺。
但是，在现在的工艺技术的情况下，使自对准硅化物工艺和SAC工艺这双方含于一个制造工艺(混合载置工艺)之内，实现起来困难度高，将会招致工艺步骤的大幅度增加，因而招致芯片成本增加。为了抑制芯片成本的增加，就不得不采用任何一方而不能使自对准硅化物工艺和SAC工艺同时并存。
假如说在逻辑性能优先的情况下，由于结果就变成为采用自对准硅化物工艺而不采用SAC工艺。作为结果，存储单元的尺寸变大，对高集成化是不利的。反之，在存储单元的高集成化优先的情况下，由于结果变成为采用SAC工艺而不采用自对准硅化物工艺，故作为结果，逻辑性能降低。
发明内容
本发明的第一技术方案提供一种从晶片切出的存储器芯片，具备：每一个都可以独立地作为存储器芯片起作用的多个基本芯片和配置在上述多个基本芯片之间，把上述基本芯片结合起来的划片线，其中上述划片线构成上述存储器芯片的一部分，上述多个基本芯片的一部分的布局，具有使上述多个基本芯片的另外一部分的布局反转后的布局。
本发明的第二技术方案提供一种“芯片上芯片”器件，具备：具有逻辑电路的逻辑芯片；要装载到上述逻辑芯片上边的第一技术方案中的存储器芯片；把上述逻辑芯片和上述存储器芯片结合起来的突点。
本发明的第三技术方案一种存储器芯片的制造方法，具备以下工序：在晶片内形成多个基本芯片；进行多个基本芯片的测试；根据预先决定的存储容量决定构成上述存储器芯片的上述基本芯片的个数；根据上述测试的结果和上述基本芯片的个数决定上述存储器芯片的形状；通过对上述晶片进行划片得到上述存储器芯片；把上述存储器芯片装载在具有逻辑电路的逻辑芯片上边。
附图说明
图1示出了成为本发明对象的COC器件。
图2示出了本发明的一个例子的存储器芯片。
图3扩大示出了图2的区域B。
图4示出了从晶片中取出来的芯片的例子。
图5示出了从晶片中取出来的芯片的例子。
图6A示出了本发明的一个例子的存储器芯片。
图6B示出了本发明的一个例子的存储器芯片。
图6C示出了本发明的一个例子的存储器芯片。
图7示出了用来变更字构成的电路。
图8示出了本发明的一个例子的制造方法。
图9示出了芯片尺寸与总体之间的关系。
图10示出了芯片尺寸与芯片效率之间的关系。
图11示出了芯片尺寸与总体之间的关系。
图12示出了芯片尺寸与芯片效率之间的关系。
图13示出了芯片尺寸与总体之间的关系。
图14示出了芯片尺寸与芯片效率之间的关系。
图15A示出了现有的芯片效率。
图15B示出了本发明的芯片效率。
图16示出了本发明的一个例子的存储器芯片。
图17示出了本发明的一个例子的存储器芯片。
图18示出了本发明的一个例子的存储器芯片。
图19到图21示出了本发明的一个例子的MCM器件。
具体实施方式
以下，边参看附图，边对本发明的一个例子的存储器芯片和使用该芯片的SiP器件以及它们制造方法详细地进行说明。在这里以作为其中之一的COC器件为中心进行说明，至于MCM器件将在后边讲述。
[COC技术]
首先，对作为本发明的对象的COC技术进行说明。
为了解决现有的问题，最近，在半导体芯片上边叠层上具有与其功能不同的功能的别的半导体芯片构成一个系统的所谓的COC技术登上了舞台。
在COC器件中，例如，如图1所示，通过突点(例如，Au突点)直接把存储器芯片(DRAM芯片、闪速存储器芯片等)装载到具有逻辑电路的LSI芯片(以下，叫做逻辑芯片)上边。
在现在，由于突点例如可以以40到50微米的节距形成，故从原理上说可以以400个/mm2的高密度把突点配置到各个芯片上边。即，在COC器件中，由于也可以形成多个数据输入输出端子，故与系统LSI同样，也可以使总线宽度(可以同时进行输入输出的位数)变成为非常大。
此外，由于借助于突点把逻辑芯片和存储器芯片彼此连接起来，故各个芯片的接口部分的输入输出端子上不会连接大的寄生电容，而且，也不会从该输入输出端子输入噪声。因此，就没有必要把缓冲器和保护电路连接到逻辑芯片和存储器芯片的接口部分的输入输出端子上。即，逻辑芯片和存储器芯片的接口部分可以简化，各个芯片的尺寸可以形成得小。
另外，逻辑芯片上边的突点的位置和存储器芯片上边的突点的位置彼此对应，例如，借助于倒装芯片键合，逻辑芯片和存储器芯片的结合就可以容易地进行。
此外，如图1所示，在把存储器芯片装载到逻辑芯片上边的情况下，存储器芯片，由于可以用在现存的通用存储器上仅仅追加一个布线层(用来形成突点的布线层)的办法形成，故还可以降低开发成本。
如上所述，倘采用COC技术，由于可以容易地解决在用混合载置工艺实现COC的情况下成为问题的各种问题(伴随着单芯片化的工艺的共通化，开发成本的问题等)，故COC技术，是一种在将来非常有希望的技术。
但是，在COC技术中也并不是没有问题。
例如，在把存储器芯片装载到逻辑芯片上边以构成系统的情况下，虽然只要存在着与使用者所要求的存储容量或字构成(数据输入输出端子数)一致的现存的通用存储器即可，但是，在不存在该存储器的情况下，就必须用存储器产生器等的EDA(工程设计自动化)工具设计与使用者所要求的规格一致的存储器芯片，然后对之进行评价。但是，这样的话，就要加长开发期间、增加开发成本。
于是，在COC技术的情况下，通常，要采用从预先准备好的COC用存储器芯片的序列中选择具有与使用者的所要求最近的规格的芯片。
因此，如果COC用存储器芯片的序列数很多，就能够从该序列中选择具有与用户要求接近或实质相同规格的芯片。但是，如果COC用存储器芯片的序列数很多，则结果就变成为为此要花费巨大的时间和费用。
另一方面，如果COC用存储器芯片的序列数少，则虽然为此所花费的时间和费用少，但是在该序列内存在具有与使用者的要求接近或实质上同一的规格的概率降低，其结果是使用者所要求的规格与可以从序列中选择的规格之差(开销)增大。
例如，在使用者所要求的规格为1兆字×64位的情况下，在序列化的COC用存储器芯片之内，既满足该规格又具有与该规格最接近的规格的芯片，在2兆字×64位的情况下，1兆字×64位(＝8兆位)的存储容量就白白浪费了，效率很差。
于是，由于采用从晶片内任意地切出一个或由多个基本芯片构成的一个存储器芯片而不是增加COC用存储器芯片的序列数的办法，就可以自由地得到具有使用者所希望的存储容量的存储器芯片，故是便利的。
此外，如果可以用控制信号自由地改变基本芯片内的字构成则是非常便利的。
[存储器芯片和COC器件]
图2示出了本发明的一个例子的存储器芯片。
在晶片11内，形成多个基本芯片(用F表示)。基本芯片的存储容量为恒定值，在本例中，被设定为4MB(兆字节)。对于基本芯片的字构成来说，也是规定的字(例如，1兆字×32位，512千字×64位等)。
在晶片状态中，在晶片11内配置有多个基本芯片，变成为一般的晶片11。但是，在本发明的情况下，要从该晶片11切出含有多个基本芯片的存储器芯片。例如，沿着图1的网格线A切断晶片。
就是说，本发明的存储器芯片由每一个都可以作为一个存储器芯片起作用的多个基本芯片(在本例的情况下)的集合构成。因此，多个基本芯片，已经电隔离(未用布线连接起来)，并在多个基本芯片之间配置划片线。在划片线内，如图3所示，形成有对准标记MARK或TEG(测试元件组)。
如上所述，在本发明中，具有16MB的存储容量的存储器芯片，可以用4个基本芯片构成。一般地说，如设一个基本芯片的存储容量为i字节，则I字节的存储器芯片可以由(I/i)个基本芯片的集合得到。但是规定I是i的整数倍。
另外，如图4所示，也可以从晶片上仅仅切出一个基本芯片。
图5示出了可以从晶片得到的存储器芯片的种类。
首先，作为前提，基本芯片的存储容量定为4MB(＝32兆字节)，字构成定为1兆字×32位(＝4兆字节)。
在存储器芯片由一个基本芯片构成的情况下，存储器芯片的存储容量为4MB，字构成为1兆字×32位。在存储器芯片由2个基本芯片构成的情况下，存储器芯片的存储容量为8MB，字构成为1兆字×64位。此外，在存储器芯片由4个基本芯片构成的情况下，存储器芯片的存储容量为16MB，字构成为1兆字×128位。
另外，存储器芯片的形状，理想的是使之变成为四角形而和构成存储器芯片的基本芯片的个数无关。这是因为只要芯片形状是四角形，则与通常的情况同样，在存储器芯片的搬运时或对准时其处理会变得容易的缘故。
此外，如图6A、6B、6C所示，如果用在上下左右相邻接的多个基本芯片构成存储器芯片，则其形状易于变成为正方形或接近于正方形的形状，故如果用仅仅上下或左右相邻接的多个基本芯片构成存储器芯片，则其形状易于变成为长方形。
如果存储器芯片的形状变成为正方形或接近正方形，则具有易于处理的优点，若仅仅在一个方向上把多个基本芯片连接起来，则对于减小划片线的面积、缩小芯片尺寸是有利的。
如上所述，本发明的一个例子的存储器芯片，由于用多个基本芯片构成，故采用改变基本芯片的个数的办法，就可以自由地改变存储器芯片的存储容量。
因此，特别是在开发COC用存储器芯片时，仅仅预先进行基本芯片的设计、开发和评价，对于使用者所要求的规格(存储容量)来说，采用改变存储器芯片内的基本芯片的个数的办法，就可以容易地满足。
然而，在使用者所要求的规格中，除去存储容量之外，还包括字构成。因此如果可以借助于控制信号改变基本芯片的字构成，则可以提供图1所示的那样的最佳的COC用存储器芯片。
图7示出了变更基本芯片的字构成的电路的一个例子。
在本例中，为了简化说明起见，对可以对32兆字×1位和16兆字×2位进行切换的基本芯片进行说明。
为了对2种字构成进行选择，要使用1位的字构成控制信号CNT。一般地说，为了可以进行2n种字构成的选择，只要使用n位的字构成控制信号CNT即可。
数据输入输出端子，存在2个(I/O·A，I/O·B)。
输入电路由缓冲器和多路分解器de-mux构成，输出电路则由缓冲器和多路复用器mux构成。
首先，考虑采用32兆字×1位的字构成的情况。在该情况下，仅仅使用数据输入输出端子I/O·A，不使用数据输入输出端子I/O·B。
多路分解器de-mux，根据字构成控制信号CNT的值，把从数据输入输出端子I/O·A输入的写入数据输出给输出节点a或输出节点b。此外，多路复用器mux，根据字构成控制信号CNT的值向数据输入输出端子I/O·A，输出输入节点a或输入节点b的读出数据。
其次，考虑采用16兆字×2位的字构成的情况。在该情况下，要使用2个数据输入输出端子I/O·A、I/O·B。
字构成控制信号CNT的值被固定，多路分解器de-mux总是向输出节点a输出从数据输入输出端子I/O·A输入的写入数据。从数据输入输出端子I/O·B输入的写入数据则被传送至多路分解器de-mux的输出节点b。此外，多路复用器mux则总是向数据输入输出端子I/O·A输出输入节点a的读出数据。多路复用器mux的输入节点b的读出数据，被传送给数据输入输出端子I/O·B。
如上所述，若可以借助于控制信号改变基本芯片的字构成，则可以容易地提供使用者所要求的字构成的存储器芯片。
另外，基本芯片的构成，要如下所示地决定。
就是说，首先，根据使用者所要求的存储容量，决定构成存储器芯片的基本芯片的个数。然后基本芯片的构成，由(使用者所要求的字构成)/(基本芯片的个数)决定。用控制信号CNT选择与已经决定的基本芯片的字构成一致的字构成。
在这里，图5示出了可以用1位的控制信号CNT选择的字构成的另外的例子。
在本例中，基本芯片可以选择1兆字×32位和512千字×64位中的任何一方。在该情况下，如果用2个基本芯片构成存储器芯片，结果就变成为可以从1兆字×64位和512千字×128位之内的一个。此外，如果用4个基本芯片构成存储器芯片，则结果就变成为可以从1兆字×128位和512千字×256位之内选择一个。
另外，本发明的COC器件，如果把上述的存储器芯片装载到逻辑芯片上边，则可以容易地得到。用来改变字构成的控制信号，从逻辑芯片提供给存储器芯片内的基本芯片。
如上所述，在本发明的存储器芯片和COC器件中，采用改变含于存储器芯片内的基本芯片的个数的办法，就可以容易地改变存储容量。此外，对于字构成，也可以用控制信号进行变更。
因此，不需要增加COC用存储器芯片的序列数，就可以大幅度削减开发成本。此外，还可以削减存储器芯片的种类，可以大幅度地削减制造价格、储藏价格和管理价格。再有，由于仅仅改变存储器芯片内基本芯片个数，就可以改变存储容量，可以借助于控制信号改变字构成，故即便是不增加COC用存储器芯片的序列数，也可以使存储容量或字构成的变化变得丰富起来。
[制造方法]
其次，对本发明的一个例子的存储器芯片和使用该芯片的COC器件的制造方法进行说明。
图8示出了本发明的一个例子的存储器芯片和使用该芯片的COC器件的制造方法。
首先决定基本芯片的存储容量(步骤ST1)。
基本芯片的存储容量，为了范围广阔地应对使用者所要求的规格，理想的是要尽可能地小。但是，当减小存储容量后，存储器芯片将变小，此外，后边要讲述，当芯片尺寸过小时，芯片面积的合计值对晶片面积的比率减小，芯片效率恶化。
于是，估计可能为使用者所要求的规格(存储容量)的最小值，把该最小值定为基本芯片的存储容量。例如，基本芯片的存储容量可以设定为1MB以上16Mb以下的值(例如4MB)。
其次，形成晶片内的多个基本芯片(步骤ST2)。
多个基本芯片，如上所述，每一个都是独立的存储器芯片，在多个存储器芯片之间，配置划片线(或划片线)。
其次，进行多个基本芯片的测试(步骤ST3)。
对晶片内的多个基本芯片，进行芯片分类测试(判别是否合格的测试)和老化。此外，在各个基本芯片中，在可以救济存储单元的不合格部分的情况下，就用冗余电路进行存储单元不合格部分的救济。对于那些不可能进行不合格部分的救济的基本芯片，就当作是不合格芯片，在晶片内的多个芯片之内，预先分选出可以装配的基本芯片(合格品)。
其次，决定构成存储器芯片的基本芯片的个数(步骤ST4)。
在基本芯片的存储容量为i字节，使用者所要求的存储容量为I字节的情况下，基本芯片数变成为以下那样。
①在可以用I＝i×m(其中，m为自然数)表示的情况下基本芯片数为m个
②在可以用I＝i×m+j(其中，m为自然数)且i＞j表示的情况下
基本芯片数为m+1个
③在可以用I＜i表示的情况下
基本芯片数为1个。
其次，决定存储器芯片的切出方法(步骤ST5)。
根据在步骤ST3中，被确认为合格品的基本芯片的位置，和在步骤ST4中决定的基本芯片的个数，决定存储器芯片的切出方法。例如，在基本芯片的个数为4个的情况下，要使得不含有作为不合格品的基本芯片那样地，而且，芯片形状变成为正方形或接近于正方形那样地，决定存储器芯片的切出方法。
其次，进行划片(步骤ST6、ST7)。
根据在步骤ST5中决定的切出方法，进行划片，完成存储器芯片。
最后，形成图1所示的那样的COC器件(步骤ST8)。
借助于倒装芯片键合，把上述存储器芯片装载到预先准备好了的逻辑芯片上边，完成COC器件。
借助于以上的工序，得以形成存储器芯片和使用该芯片的COC器件。另外，在使基本芯片具有可以变更字构成的功能的情况下，在形成了COC器件之后，就可以借助于控制信号变更基本芯片(或存储器芯片)的字构成。就是说，基本芯片的字构成可以设定为{使用者所要求的字构成(×k位)}/{基本芯片的个数}。
倘采用这样的制造方法，采用改变存储器芯片的切出方法的办法，就可以从一个晶片得到不同的规格，就是说，得到不同的存储容量和不同的字构成的存储器芯片。为此，就没有必要增加COC用存储器芯片的序列数，也没有必要对每一种使用者所要求的规格都开发存储器芯片。因此，可以大幅度地分别降低开发成本、制造成本、储存成本和管理成本。
[芯片尺寸和芯片效率]
本发明的一个例子的存储器芯片，由每一个都可以独立地作为存储器芯片起作用的多个基本芯片构成，在多个基本芯片之间，配置划片线。在这里，基本芯片的尺寸可以任意地设定，但是划片线的尺寸(宽度)却被设定为大体上的恒定值(例如，0.1mm左右)。
于是，要对芯片尺寸和芯片效率(芯片面积的合计值对晶片面积的比率)的关系进行研究。
图9示出了在使用6英寸晶片的情况下的芯片尺寸和总数(可以从晶片上取出的芯片数)PCS(片)之间的关系。图10示出了在使用6英寸晶片的情况下的芯片尺寸和芯片效率之间的关系。
此外，表1用数值示出了图9和图10的关系。
表1*晶片尺寸  ：6英寸
   *划片线宽度：0.1mm
 芯片尺寸A   芯片尺寸B   总数   芯片效率
 1234567891011121314151617181920   1.12.13.14.15.16.17.18.19.110.111.112.113.114.115.116.117.118.119.120.1   14792400418011017649440325240188149121968976604944403729   0.81090030.87800020.88858050.89203420.88945760.86835180.87301160.84203810.83480190.81682090.80262240.75783430.82455050.81660160.74007260.68766450.69709360.71046970.73223330.6359142
划片线宽度假定为0.1mm。
由图9、图10可知：
①随着芯片尺寸增大，晶片内的划片线的比率减小，芯片效率增加。
②随着芯片尺寸减小，在晶片的边缘部分中不满足芯片尺寸的区域减少，芯片效率增加。
①和②处于一种彼此折中妥协关系，在图9、图10和表1的情况下，芯片效率，在芯片尺寸为2mm(2mm×2mm)到7mm(7mm×7mm)的范围内变成为最大(0.85以上)。
然而，归因于近些年来的晶片的大口径化(晶片尺寸相对于芯片尺寸变得足够大)，②对芯片效率的影响已逐渐减小。为此，芯片效率变得充分地大(例如，0.85以上)的芯片尺寸的上限也跟着逐渐增大。
例如，图11、图12和表2，示出了使用8英寸晶片的情况下的芯片尺寸和芯片效率的关系，芯片效率在芯片尺寸为2mm(2mm×2mm)到8mm(8mm×8mm)的范围内变成为最大(0.85以上)。
表2
*晶片尺寸  ：8英寸
*划片线宽度；0.1mm
  芯片尺寸A   芯片尺寸B   总数   芯片效率
  1234567891011121314151617181920   1.12.13.14.15.16.17.18.19.110.111.112.113.114.115.116.117.118.119.120.1   2645271763249182911778055844413402842241881571321219689736860   0.81568330.88512680.90168590.90239520.90735980.89363770.88241320.87032540.84923330.87575260.83578860.83480190.81818110.79779830.83951980.75783430.7931420.72934150.75697090.7400726
此外，图13、图14和表3示出了使用12英寸晶片的情况下的芯片尺寸和芯片效率的关系，芯片效率在芯片尺寸为2mm(2mm×2mm)到17mm(17mm×17mm)的范围内变成为最大(0.85以上)。
表3
*晶片尺寸  ：12英寸
*划片线宽度：0.1mm
  芯片尺寸A   芯片尺寸B   总数   芯片效率
  1234567891011121314151617181920   1.12.13.14.15.16.17.18.19.110.111.112.113.114.115.116.117.118.119.120.1   5974916257739242002701186913641041813656553449385333284248221188177149   0.81886290.89121190.91176940.92097920.92543340.92213040.91599060.91308510.90251850.89905110.91704590.88611360.89171890.89450110.87575260.87010610.87532770.83480190.87571150.8168209
就是说，为了提高芯片效率，把芯片尺寸设定在规定范围内是重要的。因此，在划片线宽度为恒定值(例如，0.1mm)的情况下，该规定范围的下限将变成为大体上2mm而与晶片尺寸无关。另一方面，该规定范围，其倾向是伴随着晶片尺寸的大口径化逐渐上升。
因此，从理论上说，如果晶片尺寸变成为无限大，那么芯片尺寸的上限也将变成为无限大，结果是为了提高芯片尺寸、芯片效率，理想的是要设定为2mm以上。
在这里，对本发明和芯片效率之间的关系，说明具体例子。
如果以12英寸晶片的情况为例，则芯片效率在芯片尺寸为2mm(2mm×2mm)到17mm(17mm×17mm)的范围内，将变成为最大(0.85以上)。在这里，为了满足使用者所要求的规格(存储容量)，例如，假定芯片尺寸需要20mm。
在该情况下，若使用现有的存储器芯片，则芯片尺寸理所当然地要变成为20mm(20mm×20mm)，根据表3，芯片效率将变成为0.816821。对此，若使用本发明的存储器芯片，则存储器芯片例如可以由4个基本芯片构成。即，倘采用本发明，芯片尺寸将变成为5mm(5mm×5mm)，根据表3，芯片效率将变成为0.925433.
如上所述，倘采用本发明的一个例子的存储器芯片，则可以大幅度地提高芯片效率。简单地示出了其这一原理的是图15A和图15B。
就是说，在现有的存储器芯片(图15A)的情况下，在晶片11的边缘部分，会产生不能形成存储器芯片的大的区域R。该区域R招致芯片效率降低。对此，在本发明的存储器芯片(图15B)的情况下，是在晶片11边缘部分，也可以形成多个基本芯片F，该边缘部分的基本芯片F将产生本发明与现有技术之间芯片效率之差。
[变形例]
以下，对本发明的存储器芯片的变形例进行说明。
图16的存储器芯片在基本芯片上边形成的突点的排列上具有特征。对于本发明来说，突点排列自身，没有什么特别限定，不论什么样的图形都没有关系。在本例中，把突点布满基本芯片的整个表面上，端子数被设定为可以在芯片上边配置的突点的最大个数。
在图17的存储器芯片的情况下，准备了两种基本芯片的布局。就是说，一种是具有通常的布局的基本芯片，另一种是具有使通常的布局反转后的布局的基本芯片。这样的2种基本芯片，在制造工艺中采用使光掩模进行反转的办法，就可以容易地得到。
在本例的情况下，即便是存储器芯片的形状和基本芯片的个数相同，取决于存储器芯片的切出方法，也可以得到多种存储器芯片，可以增加存储器芯片的种类。例如，即便是同一晶片，如果像图17那样地切出，则可以得到突点集中在芯片中央部分的存储器芯片，而如果像图18那样地切出，则可以得到突点集中在芯片边缘部分的存储器芯片。
本发明的一个例子的存储器芯片，除去COC器件中应用之外，还可以在例如超级连接(super connect)技术或内部保持器(inter holder)技术等的装配技术中应用。所谓超级连接技术，就是把芯片装载到已形成了布线图形的硅衬底的一个主面上边的装配技术，而内部保持器技术，就是把芯片装载到已形成了布线图形的硅衬底的两面上边的装配技术。
如上所述，在本发明的一个例子的存储器芯片和COC器件的情况下，采用改变含于存储器芯片内的基本芯片的个数的办法就可以容易地变更存储容量。此外，对于字构成，也可以借助于控制信号进行变更。
因此，可以大幅度地削减开发成本而无须增加COC用存储器芯片的序列数。此外，还可以削减存储器芯片的种类、制造成本、储存成本、管理成本。再有，由于仅仅改变存储器芯片内的基本芯片的个数就可以改变存储容量，可以借助于控制信号改变字构成，故即便是不增加COC用存储器芯片的序列数，也可以使存储容量和字构成的种类变得丰富起来。
作为SiP技术，除去COC之外，还有MCM(多芯片组件)技术。
所谓MCM是一种把多个芯片装配到单个封装内的技术。图19、20、21示出了其例子。在图19中，在封装基板上边具备要装配的芯片间的信号布线和使从这些芯片组与封装外进行接口的输入输出信号与封装端子(焊针或焊球)进行连接的信号布线。一般地说，封装基板与PCB基板比较基板上边的信号布线节距可以形成得小一些。这是因为封装基板与PCB基板比较要小得多，所以可以导入基板制造成本高得多的微细基板工艺的缘故。因此，与像现有技术那样在PCB基板上边对单个芯片进行信号结线的现有的情况比较，信号的带宽可以取得高，可以构筑更高性能的系统。同样，如图20所示，也可以使用键合技术把芯片间连接起来。
此外，如图21所示，在芯片的装配中，也可以使用封装基板的两面。在这样的构成的情况下，由于可以把信号布线定为Z方向(与基板垂直的方向)，故可以把布线长度控制得短而均一。
本发明不仅可以应对COC，对于这些MCM也可以应对，这是不言而喻的。
对于那些本专业的熟练的技术人员来说还存在着另外一些优点和变形。因此，本发明就其更为广阔的形态来说并不限于上述附图和说明。此外，就如所附权利要求及其等效要求所限定的那样，还可以有许多变形而不偏离总的发明的宗旨。

Claims (18)

1.一种从晶片切出的存储器芯片，具备：
每一个都可以独立地作为存储器芯片起作用的多个基本芯片，和
配置在上述多个基本芯片之间，把上述基本芯片结合起来的划片线，
其中，上述划片线构成上述存储器芯片的一部分，
上述多个基本芯片的一部分的布局，具有使上述多个基本芯片的另外一部分的布局反转后的布局。
2.根据权利要求1所述的存储器芯片，其特征在于：上述多个基本芯片具有完全相同的布局。
3.根据权利要求1所述的存储器芯片，其特征在于：在上述划片线内形成有对准标记和测试元件组之内的至少一方。
4.根据权利要求1所述的存储器芯片，其特征在于：在上述多个基本芯片为正方形的情况下，上述基本芯片的一边的长度在2mm以上。
5.根据权利要求4所述的存储器芯片，其特征在于：上述划片线的宽度为0.1mm。
6.根据权利要求1所述的存储器芯片，其特征在于：上述基本芯片具有突点。
7.根据权利要求1所述的存储器芯片，其特征在于：上述基本芯片具有可以借助于控制信号改变字构成的电路。
8.一种“芯片上芯片”器件，具备：
具有逻辑电路的逻辑芯片；
要装载到上述逻辑芯片上边的存储器芯片；上述存储器芯片具有每一个都独立地作为芯片起作用且可以借助于控制信号改变字构成的多个基本芯片，和被配置在上述多个基本芯片之间，把上述基本芯片结合起来，并成为上述存储器芯片的一部分的划片线；和
把上述逻辑芯片和上述存储器芯片结合起来的突点，
其中，上述控制信号，从上述逻辑芯片提供给上述存储器芯片。
9.根据权利要求8所述的“芯片上芯片”器件，其特征在于：上述多个基本芯片具有完全相同的布局。
10.根据权利要求8所述的“芯片上芯片”器件，其特征在于：上述多个基本芯片的一部分的布局，具有使上述多个基本芯片的另外一部分的布局反转后的布局。
11.根据权利要求8所述的“芯片上芯片”器件，其特征在于：在上述划片线内形成有对准标记和测试元件组之内的至少一方。
12.根据权利要求8所述的“芯片上芯片”器件，其特征在于：在上述基本芯片为正方形的情况下，上述基本芯片的一边的长度在2mm以上。
13.根据权利要求12所述的“芯片上芯片”器件，其特征在于：上述划片线的宽度为0.1mm。
14.根据权利要求8所述的“芯片上芯片”器件，其特征在于：上述基本芯片具有突点。
15.一种存储器芯片的制造方法，具备以下工序：
在晶片内形成多个基本芯片；
进行上述多个基本芯片的测试；
根据预先决定的存储容量决定构成上述存储器芯片的上述基本芯片的个数；
根据上述测试的结果和上述基本芯片的个数决定上述存储器芯片的形状；
通过对上述晶片进行划片得到上述存储器芯片；以及
把上述存储器芯片装载在具有逻辑电路的逻辑芯片上边。
16.根据权利要求15所述的制造方法，还具备决定上述多个基本芯片的字构成；
其中，上述多个基本芯片的字构成，由(上述存储器芯片的字构成)/(构成上述存储器芯片的上述基本芯片的个数)决定。
17.根据权利要求15所述的制造方法，其特征在于：上述预先决定的存储容量，是使用者所要求的存储容量。
18.根据权利要求15所述的制造方法，其特征在于：上述存储器芯片借助于倒装芯片键合法装载到上述逻辑芯片上边。
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US6737743B2 (en) 2004-05-18
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