CN100433819C - Method of scrambling process for analog video signal and scrambling circuit - Google Patents
Method of scrambling process for analog video signal and scrambling circuit Download PDFInfo
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- CN100433819C CN100433819C CNB2004100659439A CN200410065943A CN100433819C CN 100433819 C CN100433819 C CN 100433819C CN B2004100659439 A CNB2004100659439 A CN B2004100659439A CN 200410065943 A CN200410065943 A CN 200410065943A CN 100433819 C CN100433819 C CN 100433819C
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Abstract
The present invention relates to an analog video signal processing method and a circuit. In the method, analog video signals of a television or a video disk device are added with sine wave interference signals, and the scrambled analog video signals can be normally played in the television; when a home video tape recorder with the AGC function records the scrambled analog video signals, severe distortion is generated; picture quality becomes worse obviously when the video tape recorder is used for playing, and thereby, normal watch is influenced. When the scrambling circuit of the present invention works, the analog video signals are divided into two paths: one path is used for forming time interval control signals added with interference signals and time interval control signals which are not added with interference signals; sine wave signals used as the interference signals are added to the other path of analog video signals at a corresponding time interval under the control of control signals; consequently, the scrambling processing of the analog video signals is realized. The method of the present invention has the advantages of artful design and practicability, and the scrambling circuit of the present invention has the advantages of simple structure and low cost.
Description
Technical field
The present invention relates to a kind of Method and circuits that analog video signal is handled, be specifically related to a kind of Method and circuits that in analog video signal, adds interference signal.
Background technology
Along with the fast development of communication satellite and broadband networks technology, the high-quality film and television constantly increase, and the industry of watching for paying has caused great challenge.TV special channel program and DVD program have brought the visual enjoyment of consumer's superior quality, use video signal recording system easily in some never protected programs and movie and video programs are recorded into the copy of commercial quality yet but allow.The illegal copies of this form, constituted a serious infringement intellectual property owner and legitimate sales merchant's interests.Analog video signal anti-copy technology is developed at the anti-copy of special channel program, and this technology can prevent to utilize the copy of home video tape recording to TV programme.That Chinese patent application 86102600 discloses is a kind of " vision signal is handled to forbid that video tape recorder accepts the method and apparatus of this signal ", this method and apparatus is by in the blanking time interval of vision signal the pulse of orderly pseudo-lock-out pulse and direct impulse being followed in lock-out pulse back adding vision signal sequence, with the realization scrambling, thereby can prevent that the family expenses video tape recorder from copying out the normal vision signal that can be used for playing.The shortcoming of above-mentioned signal scrambling technique is a complex circuit designs, based on discrete component, and is not suitable for adopting the high definition colour TV of a large amount of digital processing technologies.
Summary of the invention
The object of the present invention is to provide a kind of simple in structure, cost is lower and be suitable for the high definition colour TV analog video signal is carried out method and the scrambling circuit that scrambling is handled.
The total technical conceive of the present invention is: analog video signal is divided into two-way, wherein one the tunnel be used for forming the time interval controls signal that adds interference signal and do not add interference signal, as the sine wave signal of interference signal then under the control of control signal, in the corresponding time interval, joining on another road analog video signal, thereby realize the scrambling of analog video signal is handled.
Realize that a kind of technical scheme that analog video signal is carried out the method that scrambling handles that provides in the object of the invention is: analog signal is divided into two-way, wherein the control of one tunnel analog signal is as the sine wave of interference signal, it is closelyed follow at interval at each vertical blanking time of analog video signal and behind field system chronizing impulse, to join in another road analog video signal, thereby after this includes the common video tape recorder of analog video signal input family expenses of sinusoidal wave interference signal, make the AGC (automatic gain control) system in the video signal recording system of this video tape recorder when measuring the video level of scrambling, obtain wrong indication, and then the generation gain calibration, cause abnormal video record.
In the said method, the frequency that joins the sinusoidal wave interference signal in the analog video signal is 150 to 300kHz, and amplitude is 0.7 to 1V; The length of sinusoidal wave interference signal is the length of 5 to 10 line periods.
Realize that the another kind of technical scheme that analog video signal is carried out the method that scrambling handles that provides in the object of the invention is: analog signal is divided into two-way, add on each horizontal synchronizing pulse back porch of one road analog video signal therein by another road analog signal control as the sine wave signal of interference signal and will by one tunnel analog signal control wherein as the sine wave signal of interference signal immediately following each equalizing pulse in field blanking interval, dyke dashes, the back of horizontal synchronizing pulse joins in another road analog video signal, thereby after this includes the analog video signal input home video tape recording of sinusoidal wave interference signal, make the AGC (automatic gain control) system in the video signal recording system of this video tape recorder when measuring the video level of scrambling, obtain wrong indication, and then the generation gain calibration, cause abnormal video record.
In the said method, the frequency that joins the sinusoidal wave interference signal in the analog video signal is 150 to 300kHz, and amplitude is 0.7 to 1V; Join the sine wave signal on each horizontal synchronizing pulse back porch and join in field blanking interval that each equalizing pulse, dyke dash, the duration of the sinusoidal wave interference signal after the horizontal synchronizing pulse is 1.5 to 2.5 microseconds.
A kind of scrambling circuit that analog video signal is carried out the scrambling processing that provides of the present invention is provided, is had sync separator circuit, summation operation amplifying circuit; Its design feature is: also have timing circuit, analog switching circuit, sine wave oscillation circuit and level correction circuit; The input of sync separator circuit is the analog video signal input, the line synchronizing signal output of sync separator circuit or field sync signal output are connected with the input of timing circuit, and the output of timing circuit is connected with the control end of analog switching circuit; The output of sine wave oscillation circuit is connected with the input of video simulation switch; The summation operation amplifying circuit has the analog video signal output after video analog signal input, level correction signal input part, sine wave signal input and the scrambling; The level correction signal input part of the output termination summation operation amplifying circuit of level correction circuit, the sine wave signal input of the output termination summation operation amplifying circuit of analog switching circuit.
Above-mentioned sync separator circuit 1 has the video synchronization signal separator that model is LM1881.Timing circuit 2 has two monostable flipflops that model is 74LS221, and timing circuit 2 is can be to the timing circuit that synchronizing signal is delayed time and pulsewidth is adjusted.Analog switching circuit 3 has the integrated circuit that model is MAX4529.Sine wave oscillation circuit 4 is made up of integrated transporting discharging and auxiliary circuit.Summation operation amplifying circuit 6 has the integrated circuit that model is AD8055, and summation operation amplifying circuit 6 is with analog video signal and sine wave signal and the level correction signal is sued for peace jointly, linear amplification, produces the vision signal output of scrambling.
For the analog video signal after handling through above-mentioned scrambling circuit, when transporting to the home video tape recording record, because the AGC (automatic gain control) system in the home video tape recording is produced interference, thereby causes home video tape recording not carry out normal record to the analog video signal after the scrambling.Therefore, can in television set, play-over and do not have an influence through the analog video signal after the processing of circuit of the present invention, but when home video tape recording is recorded the analog video signal of scrambling, what record will be abnormal signal, the serious distortion of image during playback produces phenomenons such as shake, image diffusion be unclear.
The present invention has positive effect: (1) all is equipped with automatic gain control (AGC) circuit in television receiver and video tape recorder, the effect of agc circuit is when the power of input signal changes, automatically the gain of the whole receiver of control makes the signal voltage of output keep invariable.At present, what adopt in television receiver is mean value formula or peak value formula, and what adopt in the video tape recorder then is the keying formula.Maximum different being of keying formula and mean value formula and peak value formula, the detection of keying formula AGC is to carry out under the control of keyed pulse, because keyed pulse comes from the line flyback pulse of line output transformer, therefore, the AGC detection retrace interval of can only being expert at carries out, the reaction speed of this agc circuit will be higher than the agc circuit of other two kinds of forms, utilize these characteristics just can add and disturb, to reach the purpose of disturbing the video tape recorder agc circuit but not influencing the television set agc circuit in the appropriate location of vision signal.The difference on the operation principle of agc circuit according to television set and video tape recorder, if after on the analog video signal passage of television set or video disc player scrambling circuit of the present invention being set, can carry out scrambling to the analog video signal that input television set or be about to is exported video disc player handles, also promptly closelying follow in analog video signal adds a suitable amplitude and the interference signal of suitable duration on the signal after the synchronizing signal, and obtains the analog video signal of scrambling.The analog video signal of this scrambling can be in television set normal play, but if after recording with home video tape recording then because the AGC (automatic gain control) system role in the home video tape recording, upset the level of the analog video signal of input, what record will be abnormal signal, so what playback time was produced on television equipment is of poor quality, unsettled image.(2) the present invention adopts sine wave signal that analog video signal is carried out the scrambling processing, the validity of its anti-copy is higher, and sinusoidal wave scrambling is wideer to the brightness influence adjustable extent little, parameter of TV signal than impulse wave scrambling, and the field that vision signal is handled is widened relatively.(3) scrambling circuit of the present invention is particularly useful for the high definition colour TV, and simplicity of design, cost are lower.(4) after scrambling circuit of the present invention adopted integration module, good reliability, cost were lower.
Description of drawings
Fig. 1 is the former road block diagram of scrambling circuit of the present invention.
Fig. 2 is the present invention adds sinusoidal wave interference signal behind the field system chronizing impulse of analog video signal a oscillogram.
Fig. 3 is the present invention adds sinusoidal wave interference signal at the back porch of the horizontal synchronizing pulse of analog video signal a oscillogram.
Fig. 4 is the oscillogram that adds sinusoidal wave interference signal behind the equalizing pulse of the present invention in the vertical blanking period of analog video signal.
Fig. 5 is the dyke of the present invention in the vertical blanking period of analog video signal adds sinusoidal wave interference signal towards the back a oscillogram.
Fig. 6 is the oscillogram that adds sinusoidal wave interference signal after the horizontal synchronizing pulse of the present invention in the vertical blanking period of analog video signal.
Fig. 7 is the oscillogram at the Chosen Point place of each relevant circuit when adding sinusoidal wave interference signal in the scrambling circuit of the present invention behind field system chronizing impulse.
Fig. 8 is the oscillogram at the Chosen Point place of each relevant circuit when adding sinusoidal wave interference signal in the positions such as back porch of horizontal synchronizing pulse in the scrambling circuit of the present invention.
Fig. 9 is a kind of circuit theory diagrams of scrambling circuit of the present invention.
Figure 10 is the another kind of circuit theory diagrams of scrambling circuit of the present invention.
Embodiment
(embodiment 1)
See Fig. 1, the scrambling circuit of present embodiment has sync separator circuit 1, timing circuit 2, analog switching circuit 3, sine wave oscillation circuit 4, level correction circuit 5, summation operation amplifying circuit 6.The input of sync separator circuit 1 is the analog video signal input, and the field sync signal output of sync separator circuit 1 is connected with the input of timing circuit 2, and the output of timing circuit 2 is connected with the control end of analog switching circuit 3; The output of sine wave oscillation circuit 4 is connected with the input of analog switching circuit 3; Summation operation amplifying circuit 6 has the analog video signal output after analog video signal input, level correction signal input part, sine wave signal input and the scrambling; The level correction signal input part of the output termination summation operation amplifying circuit 6 of level correction circuit 5, the sine wave signal input of the output termination summation operation amplifying circuit 6 of analog switching circuit 3.
See Fig. 9, sync separator circuit 1 has the synchronizing signal separator U1 that model is LM1881; Timing circuit 2 is can be to the timing circuit that synchronizing signal is delayed time and pulsewidth is adjusted, and timing circuit 2 has two monostable flipflop U4 that model is 74LS221; Analog switching circuit 3 has the integrated circuit U3 that model is MAX4529; It is LM318 integrated operational amplifier circuit U5 that sine wave oscillation circuit 4 has model; Summation operation amplifying circuit 6 has the integrated circuit U3 that model is AD8055, and model is the voltage stabilizing didoe of 1N4733A; Level correction circuit 5 has variable resistor.The scrambling circuit of present embodiment also has connector J1, J1 has video signal input terminal and VT, its VT links to each other with the capacitance C1 of sync separator circuit 1 on the one hand, links to each other with the resistance R 1 of summation operation amplifying circuit 6 on the other hand.The other end of capacitor C 1 links to each other with 2 pin of U1; The 8 pin VCC end of U1 is positive power source terminal, and is connected with filter capacitor C8; The 6 pin SET end of U1 is connected with the auxiliary circuit that is composed in parallel by capacitor C 2 and resistance R 11; The 3 pin VSO end of U1 links to each other with 1 pin of the U4 of timing circuit 2, and 2 pin of U4 link to each other with 3 pin conllinear and with power supply VCC and by capacitor C 4 ground connection, are connected with capacitor C 3 between 14 pin of U4 and 15 pin, are connected with variable resistor RP2 between 15 pin of U4 and the power supply VCC; 4 pin of U4 directly link to each other with 10 pin, and the 9 pin ground connection of U4,11 pin meet power supply VCC, are connected with capacitor C 6 between 6 pin of U4 and 7 pin, are connected with variable resistor RP5 between 7 pin of U4 and the power supply VCC; Output 12 pin of U4 are connected with signal input end 4 pin of the U2 of analog switching circuit 3, and the 8 pin VCC end of U2 is positive power source terminal, and is connected with filter capacitor C9, the other end ground connection of capacitor C 9; The 5 pin ground connection of U2.7 pin and 4 pin of the amplifier U5 of sine wave oscillation circuit 4 meet power supply VCC and power supply-VCC respectively; Be connected with resistance R 7 between inverting input 2 pin of U5 and output 6 pin, inverting input 2 pin of U5 are by variable resistor R9 ground connection; The negative pole of voltage stabilizing didoe D1 is connected with the negative pole of voltage stabilizing didoe D2, variable resistor R6 is connected in parallel between the positive pole of the positive pole of voltage stabilizing didoe D1 and voltage stabilizing didoe D2, the plus earth of voltage stabilizing didoe D1, the positive pole of voltage stabilizing didoe D2 links to each other with capacitor C 7, and the other end of capacitor C 7 links to each other with the input of U5 6 pin; The positive pole of voltage stabilizing didoe D2 also links to each other with variable resistor R12, and the other end of variable resistor R12 is connected with the normal phase input end of U5 3 pin, and normal phase input end 3 pin of U5 are also by capacitor C 5 ground connection; Output 6 pin of U5 are connected with variable resistor R8, and the other end of variable resistor R8 is connected with signal input part 2 pin of analog switching circuit U2.7 pin of U2 are connected with the resistance R 5 of summation operation amplifying circuit 6; The other end of resistance R 5 is connected with variable resistor RP3, variable resistor RP3 other end ground connection, resistance R 5 is connected with an end of resistance R 4 with the common junction of variable resistor RP3, and the other end of resistance R 4 is connected with signal input part 3 pin of the U3 of summation operation amplifying circuit 6; 7 pin of U3 meet power supply VCC, and 4 pin of U3 meet power supply-VCC; 2 pin of U3 are by resistance R 2 ground connection, also are connected with output 6 pin of U3 by behind serial resistance R3 and the variable resistor RP4, and output 6 pin of U3 are connected with connector J2; Be connected with 3 pin of U3 by resistance R 1 back from the vision signal of connector J1 output; The variable resistor RP1 two ends of level correction circuit 5 meet power supply VCC and power supply-VCC respectively, are connected with input 3 pin of U3 behind the convertible tip connecting resistance R10 of RP1.
See Fig. 2, the scrambling circuit of present embodiment can will be closelyed follow as the sine wave signal of interference signal at interval at each vertical blanking time of analog video signal and join in the analog video signal behind field system chronizing impulse in being handled the analog video signal imported.Fig. 2 has provided the portion waveshape figure of the analog video signal after the scrambling, and wherein label is that 10 part is an image information, and 11 are the field blanking width, and 12 is the field system chronizing impulse width, and 19 are horizontal synchronizing pulse, and 20 is sine wave signal.Sine wave signal is followed and is joined in the analog video signal behind field system chronizing impulse, sinusoidal wave frequency can be selected a definite numerical value in 150 to 300kHz scope, amplitude can be selected a definite numerical value in 0.7 to 1V scope, the sinusoidal wave length that analog switching circuit 3 is intercepted is selected a definite numerical value in the length range of 5 to 10 line periods.
See Fig. 7 and Fig. 9, in the scrambling process, analog video signal is divided into two-way, one road analog video signal is the output field synchronizing signal after sync separator circuit 1 separates, field sync signal is the rising edge generation at first sawtooth waveforms of field system chronizing impulse phase, field sync signal realizes time-delay by timing circuit 2, as shown in Figure 7, the time-delay process is as follows: when field sync signal is passed through first order monostable flipflop U4A, the trailing edge of field system chronizing impulse triggers first order monostable flipflop U4A and makes its output prime negative sense monostable signal, by adjusting the variable resistor RP2 in the timing circuit 2, making the negative sense length of the prime negative sense monostable signal of first order monostable flipflop U4A output is the length of 5 line periods; This prime negative sense monostable signal inserts second level monostable flipflop U4B, rising edge at prime negative sense monostable signal triggers second level monostable flipflop U4B and makes its output back level negative sense monostable signal, by adjusting the variable resistor RP5 in the timing circuit 2, making the negative sense length of the back level negative sense monostable signal of second level monostable flipflop U4B output is 5 line period length.The back level negative sense monostable signal that obtains by timing circuit 2 time-delay inserts the signal input end of analog switching circuit 3, is used for controlling opening constantly and the length of service time of analog switching circuit 3.Sine wave oscillation circuit 4 is used for producing sine wave signal; By adjusting variable resistor R6 and the R12 in the sine wave oscillation circuit 4, the frequency that makes the sine wave signal of output is 150kHz, and by adjusting variable resistor R8, the amplitude that makes the sine wave signal of output is 0.7V; Sine wave signal is transported to summation operation amplifying circuit 6 by analog switching circuit 3, the unlatching moment of analog switching circuit 3 is controlled by the trailing edge of the back level negative sense monostable signal that timing circuit 2 produces, the opening time length of analog switching circuit 3 is by the length control of the negative sense time of back level negative sense monostable signal, thereby make analog switching circuit 3 in the time of its unlatching, finish intercepting to the sine wave signal that is passed through, and the sine wave signal that is intercepted to 6 outputs of summation operation amplifying circuit.
Finishing superposition in summation operation amplifying circuit 6 after, the level correction signal that sine wave signal after the quilt intercepting and another road analog video signal and level correction circuit 5 produce amplifies output, variable resistor RP3 is a balance resistance in the summation operation amplifying circuit 6, and variable resistor RP4 adjusts the voltage gain of output.Because treated analog video signal can produce the displacement phenomenon, the result causes image deepening, shake, therefore need add a level correction signal again when superposition, therefore is provided with level correction circuit 5.The scrambling analog video signal of output is not influence when play-overing, but through behind the family expenses video tape recorder record, the serious distortion of image during playback produces shake, image blurring unclear.
(embodiment 2)
See Fig. 7 and Fig. 9, the remainder of present embodiment is substantially the same manner as Example 1, difference is: in the time-delay process of timing circuit 2, variable resistor RP2 makes first order monostable flipflop U4A produce the prime negative sense monostable signal of 8 line period length in the timing circuit 2 by adjusting; Variable resistor RP5 makes second level monostable flipflop U4B produce the back level negative sense monostable signal of 8 line period length in the timing circuit 2 by adjusting; By adjusting variable resistor R6 and R12 in the sine wave oscillation circuit 4, making the frequency of the sine wave signal of sine wave oscillation circuit 4 outputs is 250kHz; By adjusting variable resistor R8 in the sine wave oscillation circuit 4, making the amplitude of the sine wave of sine wave oscillation circuit 4 outputs is 0.8V.
(embodiment 3)
See Fig. 7 and Fig. 9, the remainder of present embodiment is substantially the same manner as Example 1, difference is: in the time-delay process of timing circuit 2, variable resistor RP2 makes first order monostable flipflop U4A produce the prime negative sense monostable signal of 10 line period length in the timing circuit 2 by adjusting; Variable resistor RP5 makes second level monostable flipflop U4B produce the back level negative sense monostable signal of 10 line period length in the timing circuit 2 by adjusting; By adjusting variable resistor R6 and R12 in the sine wave oscillation circuit 4, making the sinusoidal wave frequency of sine wave oscillation circuit 4 outputs is 300kHz; By adjusting variable resistor R8 in the sine wave oscillation circuit 4, making the amplitude of the sine wave signal of sine wave oscillation circuit 4 outputs is 1V.
(embodiment 4)
See Fig. 1, the scrambling circuit of present embodiment has sync separator circuit 1, timing circuit 2, analog switching circuit 3, sine wave oscillation circuit 4 and level correction circuit 5, summation operation amplifying circuit 6; The input of sync separator circuit 1 is the analog video signal input, and the line synchronizing signal output of sync separator circuit 1 is connected with the input of timing circuit 2, and the output of timing circuit 2 is connected with the control end of analog switching circuit 3; The output of sine wave oscillation circuit 4 is connected with the input of analog switching circuit 3; Summation operation amplifying circuit 6 has the analog video signal output after analog video signal input, level correction signal input part, sine wave signal input and the scrambling; The level correction signal input part of the output termination summation operation amplifying circuit 6 of level correction circuit 5, the sine wave signal input of the output termination summation operation amplifying circuit 6 of analog switching circuit 3.
See Figure 10, sync separator circuit 1 has the synchronizing signal separator U1 that model is LM1881, timing circuit has two monostable flipflop U4 that model is 74LS221, analog switching circuit 3 has the integrated circuit U3 that model is MAX4529, it is LM318 integrated operational amplifier circuit U5 that sine wave oscillation circuit 4 has model, summation operation amplifying circuit 6 has the integrated circuit U3 that model is AD8055, and model is the voltage stabilizing didoe of 1N4733A; Level correction circuit 5 has variable resistor.The scrambling circuit of present embodiment also has connector J1, J1 has video signal input terminal and VT, its VT links to each other with the capacitance C1 of sync separator circuit 1 on the one hand, links to each other with the resistance R 1 of summation operation amplifying circuit 6 on the other hand.The other end of capacitor C 1 links to each other with 2 pin of U1; The 8 pin VCC end of U1 is positive power source terminal, and is connected with filter capacitor C8; The 6 pin SET end of U1 is connected with the auxiliary circuit that is composed in parallel by capacitor C 2 and resistance R 11; The 5 pin BO end of U1 links to each other with 1 pin of the U4 of timing circuit 2, and 2 pin of U4 are connected with 3 pin conllinear and with power supply VCC and by capacitor C 4 ground connection, are connected with capacitor C 3 between 14 pin of U4 and 15 pin, are connected with variable resistor RP2 between 15 pin of U4 and the power supply VCC; 4 pin of U4 directly link to each other with 10 pin, and the 9 pin ground connection of U4,11 pin meet power supply VCC, are connected with capacitor C 6 between 6 pin of U4 and 7 pin, are connected with variable resistor RP5 between 7 pin of U4 and the power supply VCC; Output 12 pin of U4 are connected with signal input end 4 pin of the U2 of analog switching circuit 3, and the 8 pin VCC end of U2 is positive power source terminal, and is connected with filter capacitor C9, the other end ground connection of capacitor C 9; The 5 pin ground connection of U2.7 pin and 4 pin of the amplifier U5 of sine wave oscillation circuit 4 meet power supply VCC and power supply-VCC respectively; Be connected with resistance R 7 between inverting input 2 pin of U5 and output 6 pin, inverting input 2 pin of U5 are by variable resistor R9 ground connection; The negative pole of voltage stabilizing didoe D1 is connected with the negative pole of voltage stabilizing didoe D2, variable resistor R6 is connected in parallel between the positive pole of the positive pole of voltage stabilizing didoe D1 and voltage stabilizing didoe D2, the plus earth of voltage stabilizing didoe D1, the positive pole of voltage stabilizing didoe D2 links to each other with capacitor C 7, and the other end of capacitor C 7 links to each other with the input of U5 6 pin; The positive pole of voltage stabilizing didoe D2 also links to each other with variable resistor R12, and the other end of variable resistor R12 is connected with the normal phase input end of U5 3 pin, and normal phase input end 3 pin of U5 are also by capacitor C 5 ground connection; Output 6 pin of U5 are connected with variable resistor R8, and the other end of variable resistor R8 is connected with signal input part 2 pin of analog switching circuit U2.7 pin of U2 are connected with the resistance R 5 of summation operation amplifying circuit 6; The other end of resistance R 5 is connected with variable resistor RP3, variable resistor RP3 other end ground connection, resistance R 5 is connected with an end of resistance R 4 with the common junction of variable resistor RP3, and the other end of resistance R 4 is connected with signal input part 3 pin of the U3 of summation operation amplifying circuit 6; 7 pin of U3 meet power supply VCC, and 4 pin of U3 meet power supply-VCC; 2 pin of U3 are by resistance R 2 ground connection, also are connected with output 6 pin of U3 by behind serial resistance R3 and the variable resistor RP4, and output 6 pin of U3 are connected with connector J2; Be connected with 3 pin of U3 by resistance R 1 back from the vision signal of connector J1 output; The variable resistor RP1 two ends of level correction circuit 5 meet power supply VCC and power supply-VCC respectively, are connected with input 3 pin of U3 behind the convertible tip connecting resistance R10 of RP1.
See Fig. 3, Fig. 4, Fig. 5, Fig. 6, the scrambling circuit of present embodiment can add as the sine wave signal of interference signal on each horizontal synchronizing pulse back porch of analog video signal and will join in the analog video signal immediately following each equalizing pulse in field blanking interval, dyke back towards, horizontal synchronizing pulse as the sine wave signal of interference signal in handling the analog video signal imported.
Fig. 3 has provided the portion waveshape figure that adds sinusoidal wave interference signal on the horizontal synchronizing pulse back porch, wherein label is that 10 part is an image information, 13 is the horizontal blanking impulse width, 14 is the horizontal blanking impulse front porch width, 15 are the horizontal synchronizing pulse width, 16 are horizontal synchronizing pulse back porch width, 20 is sine wave signal, begin to add sinusoidal wave interference signal on back triggering edge immediately following horizontal synchronizing pulse, sinusoidal wave frequency can be selected a definite numerical value in 150 to 300kHz scope, amplitude can be selected a definite numerical value, the duration of the sine wave signal that analog switching circuit 3 is intercepted in 0.7 to 1V scope be to select a definite numerical value in the scope of 1.5 to 2.5 microseconds.
Fig. 4 has provided the portion waveshape figure that adds interference signal behind the blanking zone equalizing pulse on the scene, wherein label is that 17 part is an equalizing pulse, 20 sine waves for adding, all add sinusoidal wave interference signal at each equalizing pulse and then, sine wave freuqency can be selected a definite numerical value in 150 to 300kHz scope, amplitude can be selected a definite numerical value, the duration of the sine wave signal that analog switching circuit 3 is intercepted in 0.7 to 1V scope be to select a definite numerical value in the scope of 1.5 to 2.5 microseconds.
Fig. 5 has provided blanking zone dyke on the scene and has dashed the portion waveshape figure that the back adds interference signal, wherein label is that 18 part is that dyke is towards width, 20 sine waves for adding, 21 is slotted impulse, add sinusoidal wave interference signal at the rising edge that dashes followed by each dyke, sine wave freuqency can be selected a definite numerical value in 150 to 300kHz scope, amplitude can be selected a definite numerical value, the duration of sine wave signal in 0.7 to 1V scope be to select a definite numerical value in the scope of 1.5 to 2.5 microseconds.
Fig. 6 has provided the portion waveshape figure that adds interference signal after the blanking zone horizontal synchronizing pulse on the scene, wherein label is that 19 part is horizontal synchronizing pulse, 20 sine waves for adding, after followed by each horizontal synchronizing pulse, all add sinusoidal wave interference signal, sine wave freuqency can be selected a definite numerical value in 150 to 300kHz scope, amplitude can be selected a definite numerical value, the duration of sine wave signal in 0.7 to 1V scope be to select a definite numerical value in the scope of 1.5 to 2.5 microseconds.
See Fig. 8 and Figure 10, in the scrambling process, analog video signal is divided into two-way, and one road analog video signal is the output line synchronizing signal after sync separator circuit 1 separates, and the rising edge that the horizontal synchronizing pulse in analog video signal of the line synchronizing signal of output, equalizing pulse, dyke dash produces; The line synchronizing signal of output realizes time-delay by timing circuit 2, as shown in Figure 8, the time-delay process is as follows: when line synchronizing signal is passed through first order monostable flipflop U4A, the trailing edge of line synchronizing signal triggers first order monostable flipflop U4A and makes its output prime negative sense monostable signal, by adjusting the variable resistor RP2 in the timing circuit 2, making the negative sense length of the prime negative sense monostable signal of first order monostable flipflop U4A output is 0.4 microsecond; This prime negative sense monostable signal input second level monostable flipflop U4B, rising edge at prime negative sense monostable signal triggers second level monostable flipflop U4B and makes its output back level negative sense monostable signal, by adjusting the variable resistor RP5 in the timing circuit 2, making the negative sense length of the back level negative sense monostable signal of second level monostable flipflop U4B output is 1.5 microseconds.The back level negative sense monostable signal that obtains by timing circuit 2 time-delay inserts the signal input end of analog switching circuit 3, is used for controlling opening constantly and the length of service time of analog switching circuit 3.By adjusting variable resistor R6 and the R12 in the sine wave oscillation circuit 4, the sinusoidal wave frequency that makes output is 150kHz; By adjusting variable resistor R8, the amplitude that makes the sine wave of output is 0.7V, sine wave signal is transported to summation operation amplifying circuit 6 by analog switching circuit 3, the unlatching moment of analog switching circuit 3 is by the trailing edge control of the back level negative sense monostable signal of timing circuit 2 outputs, the opening time length of analog switching circuit 3 is by the length control of the negative sense time of back level negative sense monostable signal, thereby make analog switching circuit 3 in the time of its unlatching, finish intercepting to the sine wave signal that is passed through, and the sine wave signal that is intercepted to 6 outputs of summation operation amplifying circuit.
Sine wave signal after the quilt intercepting and another road analog video signal and level correction circuit 5 produce and amplify output the level correction signals are finished superposition in summation operation amplifying circuit 6 after, variable resistor RP3 is a balance resistance in the summation operation amplifying circuit 6, and variable resistor RP4 adjusts the voltage gain of output.Because treated vision signal can produce the displacement phenomenon, the result causes image deepening, shake, therefore need add a level correction signal again when superposition, therefore is provided with level correction circuit 5.The scrambling analog video signal of output is not influence when play-overing, but through behind the family expenses video tape recorder record, the serious distortion of image during playback produces shake, image blurring unclear.
(embodiment 5)
See Fig. 8 and Figure 10, the remainder of present embodiment is substantially the same manner as Example 4, difference is: in the time-delay process of timing circuit 2, variable resistor RP2 makes first order monostable flipflop U4A produce the prime negative sense monostable signal of one 2 microsecond length in the timing circuit 2 by adjusting; Variable resistor RP5 makes second level monostable flipflop U4B produce the back level negative sense monostable signal of one 2 microsecond length in the timing circuit 2 by adjusting; By adjusting variable resistor R6 and R12 in the sine wave oscillation circuit 4, the sinusoidal wave frequency that makes output is 250kHz; By adjusting variable resistor R8 in the sine wave oscillation circuit 4, the amplitude that makes the sine wave of output is 0.8V.
(embodiment 6)
See Fig. 8 and Figure 10, the remainder of present embodiment is substantially the same manner as Example 4, difference is: in the time-delay process of timing circuit 2, variable resistor RP2 makes first order monostable flipflop U4A produce the prime negative sense monostable signal of one 3.5 microsecond length in the timing circuit 2 by adjusting; Variable resistor RP5 makes second level monostable flipflop U4B produce the back level negative sense monostable signal of one 2.5 microsecond length in the timing circuit 2 by adjusting; By adjusting variable resistor R6 and R12 in the sine wave oscillation circuit 4, the sinusoidal wave frequency that makes output is 300kHz; By adjusting variable resistor R8 in the sine wave oscillation circuit 4, the amplitude that makes the sine wave of output is 1V.
Claims (8)
1, a kind of method of treatment of simulated vision signal, it is characterized in that: this method comprises analog signal is divided into two-way, wherein the control of one tunnel analog signal is as the sine wave of interference signal, it is closelyed follow at interval at each vertical blanking time of analog video signal and behind field system chronizing impulse, to join in another road analog video signal, thereby after this includes the common video tape recorder of analog video signal input family expenses of sinusoidal wave interference signal, make the AGC (automatic gain control) system in the video signal recording system of this video tape recorder when measuring the video level of scrambling, obtain wrong indication, and then the generation gain calibration, cause abnormal video record.
2, the method for treatment of simulated vision signal according to claim 1 is characterized in that: the frequency that joins the sinusoidal wave interference signal in the analog video signal is 150 to 300kHz, and amplitude is 0.7 to 1V; The length of sinusoidal wave interference signal is the length of 5 to 10 line periods.
3, a kind of method of treatment of simulated vision signal, it is characterized in that: this method comprises analog signal is divided into two-way, add on each horizontal synchronizing pulse back porch of one road analog video signal therein by another road analog signal control as the sine wave signal of interference signal and will by one tunnel analog signal control wherein as the sine wave signal of interference signal immediately following each equalizing pulse in field blanking interval, dyke dashes, the back of horizontal synchronizing pulse joins in another road analog video signal, thereby after this includes the common video tape recorder of analog video signal input family expenses of sinusoidal wave interference signal, make the AGC (automatic gain control) system in the video signal recording system of this video tape recorder when measuring the video level of scrambling, obtain wrong indication, and then the generation gain calibration, cause abnormal video record.
4, the method for treatment of simulated vision signal according to claim 3 is characterized in that: the frequency that joins the sinusoidal wave interference signal in the analog video signal is 150 to 300kHz, and amplitude is 0.7 to 1V; Join the sine wave signal on each horizontal synchronizing pulse back porch and join in field blanking interval that each equalizing pulse, dyke dash, the duration of the sinusoidal wave interference signal after the horizontal synchronizing pulse is 1.5 to 2.5 microseconds.
5, a kind ofly carry out the scrambling circuit that scrambling is handled, have sync separator circuit (1), summation operation amplifying circuit (6) simulating vision signal; It is characterized in that: also have timing circuit (2), analog switching circuit (3), sine wave oscillation circuit (4) and level correction circuit (5); The input of sync separator circuit (1) is the analog video signal input, the line synchronizing signal output of sync separator circuit (1) or field sync signal output are connected with the input of timing circuit (2), and the output of timing circuit (2) is connected with the control end of analog switching circuit (3); The output of sine wave oscillation circuit (4) is connected with the input of analog switching circuit (3); Summation operation amplifying circuit (6) has the analog video signal output after analog video signal input, level correction signal input part, sine wave signal input and the scrambling; The level correction signal input part of the output termination summation operation amplifying circuit (6) of level correction circuit (5), the sine wave signal input of the output termination summation operation amplifying circuit (6) of analog switching circuit (3).
6, according to claim 5ly carry out the scrambling circuit that scrambling is handled to simulating vision signal, it is characterized in that: timing circuit (2) is can be to the timing circuit that synchronizing signal is delayed time and pulsewidth is adjusted.
7, according to claim 6ly carry out the scrambling circuit that scrambling is handled to simulating vision signal, it is characterized in that: it is the two monostable flipflops of 74LS221 that timing circuit (2) has model.
8, according to claim 5ly carry out the scrambling circuit that scrambling is handled to simulating vision signal, it is characterized in that: analog switching circuit (3) has the integrated circuit that model is MAX4529; Sine wave oscillation circuit (4) is made up of integrated transporting discharging and auxiliary circuit thereof; It is the LM1881 video synchronous separator that sync separator circuit (1) has model; Summation operation amplifying circuit (6) has the integrated circuit that model is AD8055.
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100659439A CN100433819C (en) | 2004-12-28 | 2004-12-28 | Method of scrambling process for analog video signal and scrambling circuit |
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| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100659439A CN100433819C (en) | 2004-12-28 | 2004-12-28 | Method of scrambling process for analog video signal and scrambling circuit |
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| CN1798310A CN1798310A (en) | 2006-07-05 |
| CN100433819C true CN100433819C (en) | 2008-11-12 |
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| CN110057456A (en) * | 2019-04-22 | 2019-07-26 | 北京科益虹源光电技术有限公司 | A kind of pulse energy measurement method and measuring circuit for excimer laser |
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| US5251041A (en) * | 1991-06-21 | 1993-10-05 | Young Philip L | Method and apparatus for modifying a video signal to inhibit unauthorized videotape recording and subsequent reproduction thereof |
| CN1181156A (en) * | 1995-04-07 | 1998-05-06 | 奇沃·福兰克林 | Method and apparatus for treating video signal |
| JPH11103440A (en) * | 1997-09-29 | 1999-04-13 | Gotenba Nippon Denki Kk | Circuit for preventing vtr recording |
| JP2000253352A (en) * | 1999-03-03 | 2000-09-14 | Kiyoumei:Kk | Video tape copy preventing signal insertion releasing device |
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- 2004-12-28 CN CNB2004100659439A patent/CN100433819C/en not_active Expired - Fee Related
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| US4819098A (en) * | 1983-11-23 | 1989-04-04 | Macrovision Corporation | Method and apparatus for clustering modifications made to a video signal to inhibit the making of acceptable videotape recordings |
| US5194965A (en) * | 1983-11-23 | 1993-03-16 | Macrovision Corporation | Method and apparatus for disabling anti-copy protection system in video signals |
| CN86102600A (en) * | 1985-04-17 | 1987-03-04 | 约翰·O·里安 | Vision signal is handled, accepted the method and apparatus of this signal to forbid video tape recorder |
| CN2083369U (en) * | 1990-03-06 | 1991-08-21 | 武汉电子技术研究所 | Encrypting device for video tape |
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| CN1181156A (en) * | 1995-04-07 | 1998-05-06 | 奇沃·福兰克林 | Method and apparatus for treating video signal |
| JPH11103440A (en) * | 1997-09-29 | 1999-04-13 | Gotenba Nippon Denki Kk | Circuit for preventing vtr recording |
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| CN1798310A (en) | 2006-07-05 |
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Assignee: CHANGZHOU NO.2 ELECTRONIC INSTRUMENT Co.,Ltd. Assignor: CHANGZHOU CAMPUS OF HOHAI University Contract fulfillment period: 2008.12.15 to 2014.12.14 Contract record no.: 2009320000426 Denomination of invention: Method of scrambling process for analog video signal and scrambling circuit Granted publication date: 20081112 License type: Exclusive license Record date: 20090318 |
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