CN100435287C - Method for removing wafer needle shape flaw and method for producing capacitor - Google Patents
Method for removing wafer needle shape flaw and method for producing capacitor Download PDFInfo
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- CN100435287C CN100435287C CNB2006100254215A CN200610025421A CN100435287C CN 100435287 C CN100435287 C CN 100435287C CN B2006100254215 A CNB2006100254215 A CN B2006100254215A CN 200610025421 A CN200610025421 A CN 200610025421A CN 100435287 C CN100435287 C CN 100435287C
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Abstract
The invention discloses method for removing needle shaped defect formed in procedure of etching grooves on substrate of wafer. The method includes steps: depositing adulterated silicide of covering surface of the wafer and grooves; painting photoresistive layer; removing out photoresistive layer on periphery of wafer to expose needle shaped defect; first etching step to remove needle shaped defect; second etching step etching step etches the photoresistive layer in certain depth inside depth to determined position of polar plate of capacitance. The invention does not need dedicated step to remove needle shaped defect. Using two times of etching phases inside reaction chamber, the invention accomplishes procedure of removing needle shaped defect, and procedure of defining position of polar plate of capacitance in one time of etching step. Integrating procedures, the invention reaches same effect, raises efficiency, and ensures yield.
Description
Technical field
The present invention relates to the manufacturing process of a kind of semiconductor memory system (Semiconductor memory device), particularly relate to and a kind ofly can improve processing procedure, effectively remove the process of wafer (wafer) edge needle shape flaw (needle-like defects) and the manufacture method of using the deep-trench capacitor of this technology.
Background technology
Integrated circuit (integrated circuits) or chip generally use electric capacity to come store charge, and the integrated circuit of present common use electric capacity comprises the storage-type integrated circuit, and (Dynamic Random Access Memory) is a kind of widely used storage-type integrated circuit as dynamic random access memory.
Dynamic random access memory mainly is made up of memory cell, and memory cell generally comprises selects transistor and electric capacity, selects transistor drain to electrically connect capacitor, and its source electrode then electrically connects the bit line.When transistor turns, the electric charge that is stored in electric capacity promptly is sent to bit line and sensing amplifier, and after sensing amplifier compared, what the decision memory cell was stored was logical zero or 1, and it is sent to the I/O data line reads.
In the manufacturing of dynamic random access memory, the widely used capacitor of industry is a deep groove capacity at present, and this deep groove capacity is generally and is formed at the suprabasil a kind of stereochemical structure of semiconductor.Generally speaking, can increase the volume or the capacitance of deep groove capacity by an etching step that gos deep into the semiconductor-based end.Under above-mentioned condition, the capacitance that deep groove capacity increased can't have any influence to the occupied area of memory cell.Generally, deep groove capacity comprises that one is etched in the groove at the semiconductor-based end, thereby and general using p type or n type doped polycrystalline silicon fill up this groove as first capacitance electrode (or a storage capacitors).In addition, this a semiconductor-based end or an embedded electrode are as second capacitance electrode; Generally can be used as insulating barrier and separate two capacitance electrodes by a capacitance dielectric layer (can also comprise a nitration case).For example, No. 02106596 application documents of No. the 200510063917th, Chinese patent and Chinese patent just disclose the manufacture method of the deep groove capacity of two kinds of dynamic random access memory respectively.
With reference to Fig. 1; wherein Fig. 1 a to Fig. 1 c simply shows the technical process of a kind of formation deep trench commonly used (deeptrench); at first; deposited oxide layer 4 (for example on wafer substrate 2; silicon nitride layer); deposition is used for the die layer 6 that shields in the etched trench process again, and etching forms deep trench then, removes die layer 6 at last and gets final product.Fig. 1 d shows the amplification situation of Waffer edge A position, can clearly find out needle shape flaw.In order to prevent that crystal round fringes is cracked, prevent thermal stress that (Thermal Stress) concentrates and in order to increase the flatness at crystal round fringes such as epitaxial layer, photoresist layer, need carry out crystal edge circle mill, be arc thereby cause the edge of wafer.So form in the process of deep trench because the edge of wafer is the etching on silicon base of arc, photoresistance or die layer are thinner at Waffer edge, and can't reach identical thickness or the evenness of wafer central authorities, thereby can't keep out etching fully; In addition, because Waffer edge more coarse (relative and wafer central authorities), so cause photoresistance or die layer in the Waffer edge out-of-flatness, thus cause etch-rate inconsistent.In the manufacture process of capacitor, owing to the existence of above-mentioned two reasons, make that the ditch trench etch is finished after, can form the needle shape flaw (needle-like defects) shown in Fig. 1 d at the marginal position of wafer.
Because the manufacturing process of semiconductor device is very complicated, all can make the spicule fracture that the marginal position of wafer exists usually, thereby pollute other zones of wafer, cause the reduction of device yield.So the needle shape flaw that generally all needs to take special step to remove the marginal position of wafer guarantees device yield.U.S. Pat 2004/0067654A1 application documents disclose a kind of method of removing the Waffer edge needle shape flaw: etching forms after the deep trench on silicon base, applies the photoresist layer that a layer thickness is approximately 1-3 μ m; Expose the then marginal position of wafer, make it to form one do not have the photoresist layer protection, width is approximately the annular region of 0-3mm; Adopt the annular region of dry etching Waffer edge, thereby remove needle shape flaw.
Though the removal method shown in this patent can effectively be removed needle shape flaw, but but in the making flow process of the deep groove capacity of dynamic random access memory, increased the special step of removing needle shape flaw of a step, make manufacture process complicated more, especially for semiconductor device, increase a step, just mean that risk increases, and might reduce rate of finished products.Therefore, adopting how can effectively remove needle shape flaw improving processing procedure, not increasing under the situation of risk, is the difficult problem that those skilled in the art need capture.
Summary of the invention
In view of the above problems, technical problem solved by the invention is: provide a kind of and can improve processing procedure, also effective process of removing wafer (wafer) edge needle shape flaw (needle-like defects), and the manufacture method of using the deep-trench capacitor of this technology.
For solving the problems of the technologies described above, the objective of the invention is to be achieved through the following technical solutions:
A kind of method of removing wafer needle shape flaw, described needle shape flaw forms in the etched process of wafer substrates groove, comprising:
The dopant deposition silicide, the surface of described doping silicide cover wafers and groove;
Apply photoresist layer;
The photoresistance of wafer perimeter is removed, exposed needle shape flaw;
First etching step is removed needle shape flaw;
Second etching step is etched to photoresist layer and presets the degree of depth in the groove, determines position of polar plate of capacitance.
Preferably, the thickness of described photoresist layer coating is: 2-6 μ m.
Preferably, described doping silicide is for containing the arsenic silicide.
Preferably, the gas of the first etching dry etching is CF
4, the gas of the second etching dry etching is O
2
The invention also discloses a kind of manufacture method of deep-trench capacitor bottom electrode, wafer etching forms deep trench, comprising:
The dopant deposition silicide, the surface of described doping silicide cover wafers and groove;
Apply photoresist layer;
The photoresistance of wafer perimeter is removed, exposed needle shape flaw;
First etching step is removed needle shape flaw;
Second etching step is etched to photoresist layer and presets the degree of depth in the groove;
Remove the doping silicide that is not covered by photoresist layer;
Remove the residue photoresist layer;
The deposition protective layer, the surface of cover wafers and groove;
Annealing or high temperature drive in, and foreign atom is diffused in the wafer substrates, form bottom electrode;
Remove described protective layer and residual doping silicide.
Preferably, the thickness of described photoresist layer coating is: 2-6 μ m.
Preferably, described doping silicide is for containing the arsenic silicide.
Preferably, the gas of the first etching dry etching is CF
4, the gas of the second etching dry etching is O
2
Preferably, described protective layer is the tetraethyl silica.
The present invention also provides a kind of manufacture method of deep-trench capacitor, comprising:
The dopant deposition silicide, the surface of described doping silicide cover wafers and groove;
Apply photoresist layer;
The photoresistance of wafer perimeter is removed, exposed needle shape flaw;
First etching step is removed needle shape flaw;
Second etching step is etched to photoresist layer and presets the degree of depth in the groove;
Remove the doping silicide that is not covered by photoresist layer;
Remove the residue photoresist layer;
The deposition protective layer, the surface of cover wafers and groove;
Annealing or high temperature drive in, and foreign atom is diffused in the wafer substrates, form bottom electrode;
Remove described protective layer and residual doping silicide;
Form dielectric layer in flute surfaces;
Utilize conductive filler to fill this groove, form a deep-trench capacitor.
Can draw from above technical scheme, compared with prior art, the present invention has following advantage:
The present invention does not need the step of special removal needle shape flaw: apply photoresist layer, the photoresist layer of Waffer edge is washed off, do not had the needle shape flaw of photoresist layer protection to remove Waffer edge by inclined-plane etching (bevel etch).The present invention is by carrying out etch phase twice in a reative cell, make the process of removing needle shape flaw in an etching step, finish in the process of definition capacitor plate position, the etching work procedure of twice in the prior art is integrated into one procedure, and can reach identical effect, save cost, raise the efficiency, guarantee rate of finished products.
Description of drawings
The present invention is further detailed explanation below in conjunction with the drawings and specific embodiments.
Fig. 1 a-Fig. 1 d is the section block diagram that forms needle shape flaw in the etched trench process;
Fig. 2 a-Fig. 2 h is the schematic diagram that the specific embodiment of the invention is made capacitor lower electrode;
Fig. 3 a-Fig. 3 b adopts the method for the invention to remove the cross-reference figure of needle shape flaw;
Fig. 4 is the step of manufacturing schematic diagram that the specific embodiment of the invention is made deep-trench capacitor.
Embodiment
Core concept of the present invention is: changed in the prior art, after the needle shape flaw removal, an electrode that carries out electric capacity again (for example, the flow process of manufacturing embedded electrode), by adjustment, make the manufacture process of the existing capacitance electrode of few change of trying one's best, but can effectively remove needle shape flaw the manufacturing step of capacitance electrode, thereby do not increase special step, guarantee rate of finished products.
In the processing procedure of the bottom electrode of general manufacturing capacitor, etching forms after the deep trench on silicon base, applies one deck photoresistance, removes the needle shape flaw of Waffer edge; Then, growth contains arsenic silicide (Arsenic SILICATE GLASS) in groove; Then, making the photoresistance that has a part in the groove cover by steps such as coating, etchings contains on the arsenic silicide; Remove not by what photoresistance was protected and contain the arsenic silicide; And make the arsenic atom diffusion that contains in the arsenic silicide layer to the semiconductor-based end, thereby form the bottom electrode of capacitor by measures such as high temperature.The inventor scrutinizes at above-mentioned processing procedure, obtains a kind of processing procedure that can improve bottom electrode, and can effectively remove the method for needle shape flaw, below the present invention is described in detail.
With reference to Fig. 2, Fig. 2 a-Fig. 2 h shows the schematic diagram that the specific embodiment of the invention is made capacitor lower electrode.
Fig. 2 a shows the situation after the etching formation deep trench on silicon base.Usually can adopt following steps to obtain deep trench: at first on the surface at the semiconductor-based end 21, to form a silicon nitride layer 22; Form the screen (die layer) 23 (generally can be the silicide of boracic and phosphorus, PSG, BPSG or BSG) of a patterning then, in order to define the position of a deep trench; By a dry method etch technology, utilize screen 23 to be hard shielding at last, to form groove 24 in silicon nitride layer 22 and at the semiconductor-based end 21.Among the embodiment shown in Fig. 2 a, the degree of depth of the groove 24 of formation is preferred, is approximately 7.5-8.0 μ m.
The general implementation method of the silicide of boracic and phosphorus is with phosphorus or boron or both unifications, participates in (CVD mode commonly used) in the silicon dioxide; Afterwards chip is pushed high temperature furnace pipe a period of time, this silicon dioxide layer (PSG, BPSG or BSG) promptly can " flow ", makes chip surface become more smooth, and planarization promptly refluxes.After groove 24 forms, the silicide layer of boracic and phosphorus removed get final product.
Form after the groove 24, need deposition to contain arsenic silicide (Arsenic SILICATE GLASS:ASG), in order in subsequent handling, to form embedded electrode.Fig. 2 b shows the generalized section after the superficial growth of surface of the groove 24 of aforementioned formation (comprising bottom and sidewall) and silicon nitride layer 22 contains arsenic silicide ASG layer 25.Certainly, the ASG layer of deposition can not exert an influence to the etching of needle shape flaw, because ASG layer thickness about 300 to 400A is easy to etched.
Deposition contains after the arsenic silicide ASG layer 25, and the present invention need apply one deck photoresist layer (PR coating) 26.Fig. 2 c shows the generalized section that applies photoresist layer groove 24 afterwards.Because photoresist layer is a liquid when applying, so can fill full groove 24.Since the present invention need be in removing the process of this photoresist layer 26 needle shape flaw of best removal Waffer edge simultaneously, so the inventor is by test of many times and calculating, drawing in the present invention, the preferred thickness of this photoresist layer 26 (silicon nitride layer 22 is with top) is 2-6 μ m.
The effect that the appeal step applies photoresist layer 26 is, need imbed in the bottom of groove 24 on the position of bottom electrode and fill photoresist layer, in order to keep need stay contain arsenic silicide ASG layer.Because the bottom electrode of electric capacity does not need to extend to the top of groove 24, so apply after the photoresist layer 26, adopt etch process to remove the photoresist layer on top, stay photoresist layer 261.Fig. 2 d shows photoresist layer and partly removes (recessetch) generalized section afterwards.
Owing to above-mentioned described photoresist layer 26 is carried out in the etched process, needs simultaneously the needle shape flaw of Waffer edge also to be removed.Therefore the present invention adopts following engraving method:
Step s1 after photoresist layer 26 coatings are finished, removes the photoresistance of Waffer edge by washing Waffer edge.The photoresistance of removing Waffer edge can adopt solution commonly used to carry out, for example OKT3.Preferably, the photoresistance of removal 1.0mm width gets final product.
Step s2, phase I etching, the needle shape flaw of removal Waffer edge.Can adopt dry etching, for example adopt CF4 gas, temperature is controlled at 20-60 degree centigrade and gets final product; Certainly, adopt this dry etching, can cause certain loss of the photoresist layer 26 that covers on certain wafer simultaneously, but because the top of photoresist layer 26 all is to need to remove, so whole processing procedure is not exerted an influence.This stage etching also can adopt wet etching to replace, and for example, adopts nitric acid to add the hydrofluoric acid certain ratio, and 10 to 50 degree are rule of thumb controlled etching period and got final product.
Step s3, the second stage etching, part is removed photoresist layer (recess etch) preset height to the deep trench, and the photoresist layer 261 that keeps certain altitude is in groove 24, thus the definition position of polar plate of capacitance.Described second stage etching, preferred, can adopt O
2Gas, temperature are controlled at 20-60 degree centigrade and get final product.
To the etching of described photoresist layer 26, when arriving the height of embedded electrode needs, stop etching.The concrete condition that stops etching is selected by the technical staff, and preferred, the height of the photoresist layer 261 that keeps among Fig. 2 d is preferably apart from zanjon top 1-6 μ m.Certainly, concrete height need be a foundation with circuit design, and the present invention is not limited the height of photoresist layer 261.
Stop accurate control constantly when described photoresist layer 26 is carried out etching, can grope the degree of depth of groove 24 and the experience of etching period by the technical staff, the employing time is controlled.Certainly, also can be by analysis to light signal in the etch chamber, when most of photoresistance of silicon chip surface is etched, the signal of light signal specific wavelength will have obviously and die down in the cavity, and rule of thumb control the moment degree of depth of zanjon inside photoresistance with the time this moment again.
The step of removal that though the present invention has adopted twice etching process to adopt finishes needle shape flaw and definition capacitor plate, advantage of the present invention is conspicuous: the step that has at first reduced by a photoresistance coating; Secondly,, in same reative cell, just can finish, not need the step of repeated washing cleaning because phase I etching of the present invention and second stage etching can be adopted close engraving method, minimum to the influence of whole processing procedure.
Defined by remaining photoresist layer 261 after the position of the capacitive electrode plates that needs, just can remove and unnecessary contained arsenic silicide ASG layer.Fig. 2 e shows and removes the unnecessary generalized section that contains arsenic silicide ASG layer groove 24 afterwards, has kept the ASG layer of being protected by photoresist layer 261 251 in groove 24.Above-mentioned steps can adopt various feasible engraving methods, for example can adopt wet etching, for example, adopts BOE solution commonly used, the NH4F:HF certain ratio, and the 10-50 degree, time 10-50 gets final product second.
Certainly, in above-mentioned etching process, with reference to Fig. 2 e, might cause the height of the ASG layer 251 of reservation to be lower than the situation of photoresist layer 261, because the protection of photoresist layer 261 oppose side walls is not very perfect, but this situation is in the category that can allow in the capacitor processing procedure.
Subsequently, remove photoresist layer 261, and clean; At the surface deposition tetraethyl silica TEOS of ASG layer 251, groove 24 and silicon nitride layer 22 (TETRAETHYLOR THOSI LICATE) layer 27.Fig. 2 f shows the generalized section after the deposition TEOS layer 27.
Then, drive in (drive-in) or annealing (anneal) waits other feasible technologies to make the arsenic atom diffusion in the ASG layer 251 go by high temperature to the semiconductor-based end 21, thereby form embedded electrode (bottom electrode).With reference to Fig. 2 g and Fig. 2 h, Fig. 2 g shows the tendency chart of annealing diffusion, and Fig. 2 h shows after the arsenic atom diffusion, and ASG layer 251 and TEOS layer 27 are removed generalized section afterwards.
With reference to Fig. 3, show the cross-reference figure that adopts method embodiment illustrated in fig. 2 to remove needle shape flaw.
Fig. 3 a shows and removes needle shape flaw situation before, Fig. 3 b shows and adopts the method for the invention etching situation afterwards, Fig. 3 a and Fig. 3 b all adopt electron microscope to amplify observation post and get, and from the contrast of two figure as can be seen, the present invention can effectively remove the needle shape flaw of Waffer edge.
With reference to Fig. 4, make the flow chart of steps of capacitor for the present invention's one specific embodiment.
The semiconductor substrate is provided, forms a silicon nitride layer on its surface; Cover the die layer of a patterning; Etching forms groove; Remove described die layer; The dopant deposition silicide, the surface of cover wafers and groove; Apply photoresist layer; The photoresistance of wafer perimeter is removed, exposed needle shape flaw; First etching step is removed needle shape flaw; Second etching step is etched to certain depth in the groove with photoresist layer; Remove the doping silicide that is not covered by photoresist layer; Remove the residue photoresist layer; The deposition protective layer, the surface of cover wafers and groove; Annealing or high temperature drive in, and foreign atom is diffused in the wafer substrates, form bottom electrode; Remove described protective layer and residual doping silicide.Form dielectric layer in flute surfaces; Utilize conductive filler to fill this groove, form a deep-trench capacitor.
The thickness that described photoresist layer applies is that 2-6 μ m gets final product.Described doping silicide is preferably and contains the arsenic silicide.The gas of the described first etching dry etching is CF
4, the gas of the second etching dry etching is O
2Described protective layer is the tetraethyl silica.Described dielectric layer preferably adopts deposition one silicon nitride layer, and oxidation forms then.Described conductive filler is preferably polysilicon.
Removal process concrete in described each step is described in front, so just repeat no more at this.
More than a kind ofly remove the method for wafer needle shape flaw and the manufacture method of deep-trench capacitor is described in detail to provided by the present invention, used specific case herein principle of the present invention and execution mode are set forth, the explanation of above embodiment just is used for helping to understand method of the present invention and core concept thereof; Simultaneously, for one of ordinary skill in the art, according to thought of the present invention, the part that all can change in specific embodiments and applications, in sum, this description should not be construed as limitation of the present invention.
Claims (10)
1, a kind of method of removing wafer needle shape flaw, described needle shape flaw forms in the etched process of wafer substrates groove, it is characterized in that, comprising:
The dopant deposition silicide, the surface of described doping silicide cover wafers and groove;
Apply photoresist layer;
The photoresistance of wafer perimeter is removed, exposed needle shape flaw;
Carry out etching step, described etching step is made of phase I etching and second stage etching; In the phase I etching process, remove needle shape flaw; In the second stage etching process, photoresist layer is etched to certain depth in the groove, determines position of polar plate of capacitance.
2, the method for removal wafer needle shape flaw as claimed in claim 1 is characterized in that, the thickness that described photoresist layer applies is: 2-6 μ m.
3, the method for removal wafer needle shape flaw as claimed in claim 1 is characterized in that, described doping silicide is for containing the arsenic silicide.
4, the method for removal wafer needle shape flaw as claimed in claim 1 is characterized in that, etching gas is CF in the phase I etching process
4, etching gas is O in the second stage etching process
2
5, a kind of manufacture method of deep-trench capacitor bottom electrode is characterized in that, wafer etching forms deep trench, comprising:
The dopant deposition silicide, the surface of described doping silicide cover wafers and groove;
Apply photoresist layer;
The photoresistance of wafer perimeter is removed, exposed needle shape flaw;
Carry out etching step, described etching step is made of phase I etching and second stage etching; In the phase I etching process, remove needle shape flaw; In the second stage etching process, photoresist layer is etched to certain depth in the groove;
Remove the doping silicide that is not covered by photoresist layer;
Remove the residue photoresist layer;
The deposition protective layer, the surface of cover wafers and groove;
Annealing or high temperature drive in, and the foreign atom in the doping silicide is diffused in the wafer substrates, form bottom electrode;
Remove described protective layer and residual doping silicide.
6, the manufacture method of deep-trench capacitor bottom electrode as claimed in claim 5 is characterized in that, the thickness that described photoresist layer applies is: 2-6 μ m.
7, the manufacture method of deep-trench capacitor bottom electrode as claimed in claim 5 is characterized in that, described doping silicide is for containing the arsenic silicide.
8, the manufacture method of deep-trench capacitor bottom electrode as claimed in claim 5 is characterized in that, etching gas is CF in the phase I etching process
4, etching gas is O in the second stage etching process
2
9, the manufacture method of deep-trench capacitor bottom electrode as claimed in claim 5 is characterized in that, described protective layer is the tetraethyl silica.
10, a kind of manufacture method of deep-trench capacitor is characterized in that, comprising:
Adopt the method for claim 5 to form bottom electrode;
Form dielectric layer in flute surfaces;
Utilize conductive filler to fill this groove, form a deep-trench capacitor.
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| CNB2006100254215A CN100435287C (en) | 2006-04-03 | 2006-04-03 | Method for removing wafer needle shape flaw and method for producing capacitor |
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| CN100435287C true CN100435287C (en) | 2008-11-19 |
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| CN107077639A (en) | 2015-10-23 | 2017-08-18 | 株式会社半导体能源研究所 | Semiconductor device and electronic equipment |
| CN105651582B (en) * | 2015-12-30 | 2018-09-14 | 芜湖东旭光电装备技术有限公司 | A kind of production method of the needle-shaped defect reflection electron microscopic sample of glass |
| CN110473798B (en) * | 2019-08-19 | 2021-10-19 | 上海华力微电子有限公司 | Method for detecting ultra-small-size defects on wafer surface |
| TWI783413B (en) * | 2021-03-19 | 2022-11-11 | 世界先進積體電路股份有限公司 | Methods for forming semiconductor devices |
| US11569121B2 (en) | 2021-05-26 | 2023-01-31 | Vanguard International Semiconductor Corporation | Methods for forming semiconductor devices |
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|---|---|---|---|---|
| JPH05129247A (en) * | 1991-11-07 | 1993-05-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5891807A (en) * | 1997-09-25 | 1999-04-06 | Siemens Aktiengesellschaft | Formation of a bottle shaped trench |
| US20020018377A1 (en) * | 2000-06-13 | 2002-02-14 | Klaus-Dieter Morhard | Method for increasing the trench capacitance |
| US20030170997A1 (en) * | 2002-03-06 | 2003-09-11 | Winbond Electronics Corp. | Method for removing Si-needles of wafer |
| US20040067654A1 (en) * | 2002-10-07 | 2004-04-08 | Promos Technologies, Inc. | Method of reducing wafer etching defect |
| US20040157461A1 (en) * | 2003-02-10 | 2004-08-12 | Seh America, Inc. | Method for fabricating a wafer including dry etching the edge of the wafer |
-
2006
- 2006-04-03 CN CNB2006100254215A patent/CN100435287C/en not_active Expired - Fee Related
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05129247A (en) * | 1991-11-07 | 1993-05-25 | Fujitsu Ltd | Manufacture of semiconductor device |
| US5891807A (en) * | 1997-09-25 | 1999-04-06 | Siemens Aktiengesellschaft | Formation of a bottle shaped trench |
| US20020018377A1 (en) * | 2000-06-13 | 2002-02-14 | Klaus-Dieter Morhard | Method for increasing the trench capacitance |
| US20030170997A1 (en) * | 2002-03-06 | 2003-09-11 | Winbond Electronics Corp. | Method for removing Si-needles of wafer |
| US20040067654A1 (en) * | 2002-10-07 | 2004-04-08 | Promos Technologies, Inc. | Method of reducing wafer etching defect |
| US20040157461A1 (en) * | 2003-02-10 | 2004-08-12 | Seh America, Inc. | Method for fabricating a wafer including dry etching the edge of the wafer |
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