CN100435299C - 布线基板的制备方法 - Google Patents
布线基板的制备方法 Download PDFInfo
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Abstract
具有从基板表面伸出的突点的布线基板的制备方法,包括以下步骤:用电绝缘膜覆盖金属基底的一面并在绝缘膜中形成开孔以在其底部露出基底,用具有开孔的绝缘膜作掩模蚀刻基底,形成凹处,用基底作为镀覆电源层电镀每个凹处的内表面,在其上形成阻挡金属膜,使用基底作为镀覆电源层,通过电镀以材料填充用于突点的凹处,使用基底作为镀覆电源层,在各凹处填充的材料表面上形成阻挡层,在绝缘膜上形成预定数量的布线图形叠层;叠层中的相邻布线图形通过插入的绝缘层相互隔开,并通过其中形成的通路孔相互连接,布线图形电连接到凹处中填充的材料,从具有突点的布线图形的叠层上除去基底,每个突点具有阻挡金属膜,从每个突点上除去阻挡金属膜。
Description
技术领域
本发明涉及布线基板的制备方法。更具体地说,本发明涉及通过使用由金属制成的基底制备提供有连接突点和布线图形的布线基板的方法。
背景技术
对于布线基板的制备方法,如JP 2000-323613A和JP 2002-83893A中介绍的,有以下方法:其中在金属制成的基底的一面上形成随后要连接到半导体元件电极的突点和连接到突点的布线图形,所述金属通常为铜,然后溶解除去基底,由此制备了布线基板。
为了在基底上形成布线图形,可以采用制备布线基板的常见方法。例如,可以使用以下方法形成具有给定图形的布线层:在基底上形成绝缘层,在绝缘层中形成通路孔,随后在绝缘层的表面上以及通路孔的内表面上形成镀覆籽层,使用基底作为镀覆的电源层进行电镀,由此在绝缘层的表面上和通路孔的内表面上形成导电层,以及蚀刻导体层。
对于使用基底制造布线基板期间通过镀覆形成要连接到半导体元件电极的突点的方法,存在以下形成突出的焊料突点的方法:在对应于突点的位置处凹入地蚀刻基底的表面,使用基底作为镀覆的电源层进行焊料电镀,由此用焊料填充基底中形成的凹处,然后溶解除去基底。
当焊料突点形成在基板中对应于半导体元件电极的位置处时,为了使用基底制造布线基板,由于电极的尺寸小并且相邻电极之间的距离小,因此需要高精度地形成突点,而且由于要接合到电极的突点尺寸很小,因此与极板的接触面积小,导致了基板与焊料突点的接合问题。
在使用基底的布线基板的制造中,如上所述,进行热处理以便,例如在形成绝缘层和基底上的布线图形期间加热和固化绝缘层。当形成提供有焊料突点的布线基板时,存在热处理期间焊料突点的表面变色的问题。相信这是由于用于基底的铜(Cu)和焊料中的锡(Sn)相互扩散,由此在焊料和基底之间的界面形成化合物相。变色的焊料突点表面损害了突点的外观,降低了焊料突点和电极之间电连接的可靠性。
发明概述
本发明的一个目的是提供一种布线基板的制备方法,确保了基板和半导体元件之间的电连接,并且可以容易和可靠地制备。
根据本发明,提供一种布线基板的制备方法,布线基板提供有从基板表面伸出的突点,该方法包括以下步骤:用电绝缘膜覆盖金属基底的一面并在绝缘膜中形成开孔以在它的底部露出基底,使用具有开孔的绝缘膜作为掩模蚀刻基底,在基底中形成凹处,使用基底作为镀覆电源层电镀每个凹处的内表面,在每个凹处的内表面上形成阻挡金属膜,使用基底作为镀覆电源层通过电镀填充用于突点的材料凹处,在使用基底作为镀覆电源层的每个凹处中填充的用于突点的材料表面上形成阻挡层,在绝缘膜上形成预定数量的布线图形的叠层;叠层中的相邻布线图形通过插入的绝缘层相互隔开,并通过插入的绝缘层中形成的通路孔相互连接,并且布线图形电连接到凹处中填充的用于突点的材料,从具有突点的布线图形的叠层上除去基底,每个突点具有阻挡金属膜,以及从每个突点上除去阻挡金属膜。
优选使用大尺寸的金属箔作为基底,同时制备多个布线基板。
优选使用粘接周边来接合层叠的两个金属基底,用电绝缘膜覆盖层叠的相对面。
开孔最好形成在绝缘膜中以具有锥形内表面,使开口侧的直径大于露出基底的底部直径。
为形成凹处蚀刻基底使用的蚀刻最好是各向同性的,每个凹处形成得与绝缘膜接合处的直径大于提供在绝缘膜中的孔的底部直径。
最好以这样的方式用材料填充凹处用于突点,即材料完全填充凹处并部分伸入到绝缘膜中的开孔内。
基底最好由铜制成。
更优选地,基底为铜箔。
最好通过蚀刻除去基底。
突点最好由焊料或金制成。
阻挡金属膜最好由镍或钴形成。
每个凹处中填充的用于突点的材料表面上的阻挡层最好由镍形成。
附图简述
考虑下面参考附图做出的详细说明,本领域中的普通技术人员将能很好地明白和理解本发明的以上和其它目的及优点。附图中:
图1A到1M示出了本发明的布线基板的制备方法的一个实施例;以及
图2示出了一种半导体器件,其中一半导体元件安装在根据本发明的方法制成的布线基板上。
发明的详细说明
图1A到1M示出了本发明的一个实施例,表示提供有焊料突点的布线基板的制备,焊料突点上将安装半导体元件。
在本实施例中,通过以下步骤制备布线基板:层叠由金属制成的两个片状基底,在每个基底的一面上形成焊料突点和布线图形,将层叠的基底分成两个,然后溶解除去每个基底。下面介绍布线基板的制造工艺。
如图1A所示,用呈现电绝缘性质的绝缘层12分别覆盖形成芯的两个基底10的叠层的相对面。通过将如聚酰亚胺膜的电绝缘树脂膜层叠到基底10形成绝缘层12。
在本实施例中,使用大尺寸的铜箔作为基底10,两个大尺寸基底10的叠层用作支撑物。使用粘结剂沿基底10的周边窄部位接合层叠基底10。当基底10随后相互分开时,它们在粘附的部位内被切开。
如图1B所示,开孔12a形成在绝缘层12中。形成开孔12a以使其位于对应于将安装在完成的布线基板上的半导体元件电极的位置处,并且具有的尺寸适合于将接合到电极上的焊料突点的直径。可以通过激光加工或蚀刻绝缘层12形成孔12a。优选的是形成开孔12a使其具有锥形内表面,即在开口侧处的直径大于位于绝缘层10上的底部直径,如图所示。
如图1C所示,使用具有开孔12a的绝缘层12作为掩模,化学蚀刻基底10,由此产生用于形成突点的凹处16。通过从具有圆形截面的开孔12a的底部各向同性地蚀刻基底10,每个凹处形成得具有半球形内表面,在与绝缘层12接合处的直径大于提供在绝缘膜12中的孔12a的底部直径,如图所示。
如图1D所示,使用基底10作为镀覆电源层通过电镀在每个凹处16的内表面上形成阻挡金属膜18。提供阻挡金属膜18以覆盖凹处16的整个内表面,并阻止在铜的基底10和焊料突点之间的界面处形成化合物相。可以通过镀镍或钴形成阻挡金属膜18。对于阻挡金属膜18,使用通过可以容易蚀刻除去同时不蚀刻焊料的金属,因为在随后的步骤中通过蚀刻除去了阻挡金属膜。
如图1E所示,使用基底10作为镀覆电源层通过电镀,用焊料填充内表面上有阻挡金属膜18(图1D)的凹处16。如图所示,以焊料完全填充凹处16并且部分伸入绝缘层12中孔12a内的方式进行焊料镀覆。焊料20伸入孔12a内使得很难从布线基板上除去焊料突点。
基底10上多层布线图形的形成示于图1F到1I中。
如图1F所示,使用基底10作为镀覆电源层通过电镀,在凹处16(图1D)内填充的焊料20的表面上形成阻挡层22,然后通过无电镀和电镀铜,在阻挡层22上形成铜层24,填充了孔12a(图1C)并覆盖了绝缘层12的表面。阻挡层22由镀覆的镍形成,并用于阻止在焊料20和铜层24之间形成化合物相。然后蚀刻绝缘层12上的铜层24形成具有给定图形的布线图形(第一布线图形)24a,如图1G所示。
随后,将树脂膜层叠到绝缘层12形成覆盖布线图形24a的第二绝缘层13,通过激光加工在绝缘层13中形成通路孔26,如图1H所示。可以通过这样的方法在绝缘层13中形成通路孔26,其中绝缘层由光敏树脂膜形成,然后曝光和显影。
如图1I所示,通过以下步骤形成第二布线图形24b:在绝缘层13的表面上和通路孔26内(图1H)形成镀覆的籽层(未示出),使用基底10作为镀覆电源层通过电镀铜填充通路孔26并覆盖绝缘层13形成铜层,以及蚀刻铜层以具有给定图形。填充在通路孔26中的铜材料形成通路28,穿过通路28,第一布线图形24a电连接到第二布线图形24b。可以通过,例如:无电镀或溅射工艺形成绝缘层13上以及通路孔26内的镀覆籽层。
如图1J所示,通过用如焊料抗蚀剂的钝化层30覆盖绝缘层13和第二布线图形24b并构图钝化层30露出部分下面的布线层24b形成每个接合到外部连接端的焊台32。焊台32具有镍、金或类似物的保护镀膜32a。
图1K示出了通过沿粘附两个基底的部位内切割,而从两个大尺寸基底的叠层中分离开的一个基底10,在分开的基底10的一个面上提供有给定量(图中示出的实施例中为两个)的布线图形层以及布线图形的顶层中的焊台。
然后通过蚀刻除去基底10,如图1L所示。在这里介绍的实施例中,基底10为铜材料,阻挡金属膜18为镍或钴材料,没有被用于基底10的蚀刻剂蚀刻。由此,通过蚀刻仅除去了基底10,由此露出了用阻挡金属膜18覆盖的焊料20。
如图1M所示,然后选择性地蚀刻除去焊料20上的阻挡金属膜18(图1L),并提供一体地制备在大尺寸基底10上并与其分开的布线基板主体,布线基板具有从绝缘层12表面伸出的球形焊料突点20a。可以通过蚀刻选择性地除去阻挡金属膜18。
除去阻挡金属膜18之后,沿预定的线将一体地制备的布线基板切割成各布线基板。
图2示出了一个半导体器件,其中如此得到的布线基板40具有安装在其上的半导体元件50的。在该半导体器件中,通过将提供在半导体元件50上的电极52接合到基板40上的焊料突点20a,将半导体元件50安装在布线基板40上,由,例如:焊料球制成的外部连接端42接合到具有保护膜32a的焊台32上,外部连接端电连接到半导体元件50。
如上所述,根据本发明,通过使用基底10作为支撑物形成焊料突点20a,并也使用基底10作为支撑物形成多层布线图形24a,24b制备布线基板。由于这个原因,可以这样的方式形成焊料突点20a和布线图形24a,24b,即焊料突点20a和布线图形24a,24b可靠地固定在适当的位置处以便在制造期间不移位,由此能高精度地制备布线基板。在焊料突点与半导体元件的电极对准形成的情况中,半导体元件的电极具有小尺寸并且以小间距排列,此时需要高精度的对准。根据本发明,使用基底材料制备布线基板,可以容易地制备具有需要精度的布线基板。
本发明具有以下优点:通过在基底的一面上形成绝缘层介于其间的布线图形的叠层,然后溶解除去基底,可以有效和容易地得到具有需要的布线图形和焊料突点的布线基板。
根据本发明的方法,其中阻挡金属膜被提供在基底中用于形成突点凹处内表面上,即使布线基板的制备其间进行了热处理,在基底和填充在凹处中的焊接材料之间也没有形成化合物相。由于这个原因,可以确保消除布线基板的制备其间焊料突点的变色问题,由此提高了焊料突点接合到要安装到布线基板上的半导体元件的电极的可靠性。
此外,根据本发明的方法,通过将焊接材料填充在随后从完成的布线基板上除去的基底的凹处中,并部分填充在位于基底上的绝缘层内的孔中,形成焊料突点,每个凹处具有一个开口,通过该开口它与孔相通,它具有的直径小于与绝缘层接合的凹处的直径。由此,根据本发明的方法制备的布线基板具有以下优点:通过从绝缘层伸出的半球形突点部分和埋置在绝缘层的孔中的一部分焊料之间的界面处的收缩可以可靠地支撑焊料突点,因此,突点可以可靠地接合到基板的主体,并且即使突点和基板的主体之间的接触面积不够,也可以防止与布线基板上分离或移位。
虽然,在以上的本发明的实施例中,使用两个基底的叠层作为支撑用于在叠层的两面上同时有效地制造布线基板,根据本发明也可以使用单个基底制造布线基板。
此外,也可以用金或类似物代替以上实施例中使用的镀覆焊料,填充在基底中用于形成突点的凹处,以提供具有除焊料之外的突点材料的布线基板,该突点材料可以可靠地固定到基板。
此外,虽然在以上的实施例中使用了减工艺形成了布线图形,但布线图形形成方法不限于此,可以使用加工艺、半加工艺等在绝缘层上形成布线图形。
如上所述,根据本发明的布线基板的制备方法,其中在用焊料填充凹处形成突点之前,在基底中凹处的内表面上形成阻挡金属膜,可以防止在基底和焊料突点之间界面处形成化合物相,也可以防止突点变色,由此提供了具有高接合可靠性突点的布线基板。此外,根据本发明的方法,在基底中形成焊料突点使用的树脂膜也用作形成布线图形的绝缘层,由此可以容易地制造具有多层布线图形并且绝缘层介于其间的布线基板。
Claims (13)
1.一种布线基板的制备方法,所述布线基板具有从基板表面伸出的突点,该方法包括以下步骤:用电绝缘膜覆盖金属基底的一面并在电绝缘膜中形成开孔以在它的底部露出基底,使用具有开孔的电绝缘膜作为掩模蚀刻基底,在基底中形成凹处,使用基底作为镀覆电源层电镀每个凹处的内表面,在每个凹处的内表面上形成由第一材料构成的阻挡金属膜,使用基底作为镀覆电源层通过电镀用第二材料填充用于突点的凹处,使用基底作为镀覆电源层,在填充到每个凹处中的用于突点的材料表面上形成由第三材料构成的阻挡层,在电绝缘膜上形成预定数量的布线图形的叠层;叠层中的相邻布线图形通过插入的绝缘层相互隔开,并通过插入的绝缘层中形成的通路孔相互连接,并且布线图形电连接到凹处中填充的用于突点的材料,从具有突点的布线图形的叠层上除去基底,每个突点具有阻挡金属膜,且从每个突点上除去阻挡金属膜。
2.根据权利要求1的方法,其中使用金属箔作为基底,该金属箔的尺寸足以同时制备多个布线基板。
3.根据权利要求2的方法,其中使用粘接周边接合层叠的两个金属基底,用电绝缘膜覆盖叠层的相对面。
4.根据权利要求1的方法,其中开孔形成在电绝缘膜中以具有锥形内表面,开口侧的直径大于露出基底的底部直径。
5.根据权利要求1的方法,其中为形成凹处蚀刻基底使用的蚀刻为各向同性的,每个凹处形成得与电绝缘膜接合处的直径大于提供在电绝缘膜中的孔的底部直径。
6.根据权利要求1的方法,其中以这样的方式用用于突点的材料填充凹处,即材料完全填充凹处并部分伸入到电绝缘膜中的开孔内。
7.根据权利要求1的方法,其中基底由铜制成。
8.根据权利要求7的方法,其中基底为铜箔。
9.根据权利要求1的方法,其中通过蚀刻除去基底。
10.根据权利要求1的方法,其中突点由焊料或金制成。
11.根据权利要求9的方法,其中突点由焊料制成。
12.根据权利要求1的方法,其中阻挡金属膜由镍或钴形成。
13.根据权利要求1的方法,其中每个凹处中填充的用于突点的材料表面上的阻挡层由镍形成。
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- 2003-09-15 CN CNB03156948XA patent/CN100435299C/zh not_active Expired - Fee Related
- 2003-09-15 US US10/661,530 patent/US7093356B2/en active Active
- 2003-09-16 KR KR1020030064168A patent/KR101005504B1/ko not_active IP Right Cessation
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KR20040025592A (ko) | 2004-03-24 |
JP3990962B2 (ja) | 2007-10-17 |
TW200405486A (en) | 2004-04-01 |
CN1491076A (zh) | 2004-04-21 |
JP2004111520A (ja) | 2004-04-08 |
US20040060174A1 (en) | 2004-04-01 |
TWI286359B (en) | 2007-09-01 |
US7093356B2 (en) | 2006-08-22 |
KR101005504B1 (ko) | 2011-01-04 |
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