CN100461374C - Nonvolatile memory unit, manufacturing method, and opertion method - Google Patents
Nonvolatile memory unit, manufacturing method, and opertion method Download PDFInfo
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- CN100461374C CN100461374C CNB200510092106XA CN200510092106A CN100461374C CN 100461374 C CN100461374 C CN 100461374C CN B200510092106X A CNB200510092106X A CN B200510092106XA CN 200510092106 A CN200510092106 A CN 200510092106A CN 100461374 C CN100461374 C CN 100461374C
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Abstract
The non-volatile memory includes substrate, selection grid electrode, two charge storage layers, two regions of source electrode/drain electrode and control grid electrodes. At least two grooves are setup in the substrate. The selection grid electrode is setup on substrate between the two grooves. Two charge storage layers are setup at sidewalls of the selection grid electrodes adjacent to two grooves respectively. Two regions of source electrode/drain electrode are setup on substrate of base of two grooves. Being setup on substrate, selection grid electrode is filled to two grooves.
Description
Technical field
The present invention relates to a kind of semiconductor element, particularly relate to a kind of non-volatility memorizer and manufacture method thereof and method of operation.
Background technology
In various non-volatility memorizer products, has the actions such as depositing in, read, erase that to carry out repeatedly data, but and can the erasing and program read-only memory (EEPROM) by electricity of the data that deposit in the advantage that after outage, also can not disappear, become personal computer and electronic equipment a kind of memory component of extensively adopting.
But typically can erase and the polysilicon making floating grid (Floating Gate) and control grid (Control Gate) of program read-only memory by electricity to mix.And, be separated by with dielectric layer between floating grid and the control grid, and be separated by with tunnel oxide (Tunneling Oxide) between floating grid and substrate.When flash memory being write/erases the operation of (Write/Erase) data, by applying bias voltage, so that electronics injects floating grid or electronics is pulled out from floating grid in control grid and source/drain regions.And during the data in reading flash memory, on the control grid, applying an operating voltage, this moment, the electriferous state of floating grid can influence the ON/OFF of its lower channel (Channel), and the ON/OFF of this passage is the foundation of interpretation data value " 0 " or " 1 ".
But when above-mentioned can electricity erase and program read-only memory when carrying out the erasing of data because the electron amount of discharging from floating grid is wayward, have positive charge so easily make floating grid discharge polyelectron, excessively erase (Over-erase) that calls.When this phenomenon of excessively erasing is too serious, in addition the passage that can make the floating grid below grid is undressed when making voltage in control, promptly continue to be conducting state, and cause the erroneous judgement of data.
So, in order to solve the problem that element is excessively erased, but many can electricity erasing and program read-only memory can adopt the design of separated grid (Split Gate).Its architectural feature also has the selection grid (or being called the grid of erasing) that is positioned at above control grid and floating grid sidewall, the substrate except control grid and floating grid.Wherein, this selects to be separated by with dielectric layer between another layer grid between grid and control grid, floating grid and the substrate.So when the phenomenon of excessively erasing is too serious, that is square channel selects the passage of grid below still can keep closed condition when the control grid does not apply the state that promptly presents conducting under the operating voltage state under the floating grid.That is select closing of grid, and can make drain region and source area present non-conduction state, so can prevent the erroneous judgement of data.
Yet, have bigger memory cell size owing to separated grid structure needs bigger separated grid zone, thus its memory cell size to have the stacked gate memory cell size big, and produce the so-called problem that can't increase the element integrated level.Improving under the trend of element integrated level at present, how manufacturing dimension dwindle, high integration, the memory component that can take into account its quality again is the consistent target of industry.
Summary of the invention
In view of this, a purpose of the present invention is providing a kind of non-volatility memorizer and manufacture method thereof and method of operation exactly, and this kind non-volatility memorizer can store two bit data in single memory cell, integrated level that therefore can lift elements.
A further object of the present invention provides a kind of non-volatility memorizer and manufacture method and method of operation, can efficiently carry out sequencing, and improves element operation speed.
Another purpose of the present invention provides a kind of non-volatility memorizer and manufacture method and method of operation, and the technology of this kind non-volatility memorizer is simple, and can reduce manufacturing cost.
The present invention proposes a kind of non-volatility memorizer, and this non-volatility memorizer comprises: substrate, selection grid, two electric charge storage layers, two source/drain regions and control grid.At least two grooves are set in the substrate.Select grid to be arranged in the substrate between two grooves.Two electric charge storage layers are arranged at two grooves respectively on the sidewall of selecting grid.Two source/drain regions are arranged at respectively in the substrate of two channel bottoms.The control grid is arranged in the substrate, and fills up two grooves.
In above-mentioned non-volatility memorizer, the material of two electric charge storage layers comprises doped polycrystalline silicon or silicon nitride.And two electric charge storage layers are in abutting connection with selecting the grid part to have wedge angle respectively.Be provided with a tunneling dielectric layer between two electric charge storage layers and the substrate.Be provided with dielectric layer between grid between two electric charge storage layers and the control grid.Select the material of grid to comprise doped polycrystalline silicon.Select to be provided with the selection gate dielectric between grid and the substrate.
The present invention proposes a kind of non-volatility memorizer, and this non-volatility memorizer comprises: substrate, a plurality of selection grid, a plurality of electric charge storage layer, multiple bit lines, many word lines.A plurality of grooves are set in the substrate, and these grooves extend toward first direction.A plurality of selection grids are arranged at respectively in this substrate between per two adjacent two grooves, and these select grids to extend toward first direction.A plurality of electric charge storage layers are arranged at the sidewall of groove respectively.Multiple bit lines is arranged in the substrate of channel bottom.Many word line is set in parallel in the substrate, and fills up groove, and these word lines extend toward a second direction, and second direction and first direction are staggered.
In above-mentioned non-volatility memorizer, the material of electric charge storage layer comprises doped polycrystalline silicon or silicon nitride.Each electric charge storage layer selects the grid part to have wedge angle in abutting connection with each.Be provided with tunneling dielectric layer between each electric charge storage layer and the substrate.Be provided with dielectric layer between grid between each electric charge storage layer and each word line.
In above-mentioned non-volatility memorizer, be provided with in the substrate between the line of two-phase ortho position to resist and wear doped region.Each selects to be provided with between grid and the substrate selection gate dielectric.The electric charge storage layer that is arranged at trenched side-wall is separated from each other.
Non-volatility memorizer of the present invention owing to do not have the gap between memory cell, therefore can promote the integrated level of memory.And, at the electric charge storage layer of the two side of each groove in abutting connection with two electric charge storage layers of selecting grid structure) can store one data respectively, that is the single memory cell of non-volatility memorizer of the present invention can store two data.And, by the degree of depth of control groove, passage length that also can the control store unit, and avoid the abnormal electrical perforation of memory cell.
The invention provides a kind of manufacture method of non-volatility memorizer, substrate at first is provided, and in substrate, form a plurality of first conductor layers that extend toward a first direction.Then, be mask with first conductor layer, remove the part substrate in substrate, to form a plurality of grooves.In substrate, form first dielectric layer, and form first electric charge storage layer and second electric charge storage layer respectively in the two side of groove.Then, in the substrate of channel bottom, form a plurality of doped regions, and in substrate, form second dielectric layer.Afterwards, form a plurality of second conductor layers that extend toward a second direction in substrate, these second conductor layers fill up groove, and second direction is interlocked with first direction.
In the manufacture method of above-mentioned non-volatility memorizer, form first electric charge storage layer respectively in the two side of groove and the second electric charge storage layer step is as follows.At first, in groove, insert the charge storage material layer.Carry out the etch-back step then, so that the top of charge storage material layer is lower than substrate surface.Sidewall in groove forms clearance wall, and covers Partial charge storage material layer.Afterwards, be etching mask with the clearance wall and first conductor layer, remove Partial charge storage material layer, and form first electric charge storage layer and second electric charge storage layer in the sidewall of groove.
In the manufacture method of above-mentioned non-volatility memorizer, in the method that the sidewall of groove forms first electric charge storage layer and second electric charge storage layer is to insert the charge storage material layer in prior to groove, patterning electric charge storage material layer forms first electric charge storage layer and second electric charge storage layer with the sidewall in groove then.
In the manufacture method of above-mentioned non-volatility memorizer, after the method that forms first conductor layer in the substrate is to form gate dielectric layer on prior to substrate, on gate dielectric layer, form conductor material layer.After forming cap layer on the conductor material layer, patterning cap layer, conductor material layer and gate dielectric layer.
In the manufacture method of above-mentioned non-volatility memorizer, the material of first electric charge storage layer and second electric charge storage layer comprises doped polycrystalline silicon or silicon nitride.
The manufacture method of non-volatility memorizer of the present invention, because electric charge storage layer (floating grid) is formed in the groove of substrate with the control grid, so its memory cell size can dwindle, and can increase the integrated level of element.Electric charge storage layer (in abutting connection with two electric charge storage layers of first conductor layer) in the two side of each groove can store one data respectively, that is the single memory cell of non-volatility memorizer of the present invention can store two data.And, by the degree of depth of control groove, passage length that also can the control store unit, and avoid the abnormal electrical perforation of memory cell.In addition, the technology of non-volatility memorizer of the present invention is comparatively simple, and can promote the integrated level of memory array.
The present invention proposes a kind of method of operation of non-volatility memorizer, is applicable to above-mentioned memory array.This memory array comprises: a plurality of selection grids are arranged in the substrate, and have a groove respectively in adjacent two substrates of selecting between the grid; A plurality of electric charge storage layers are arranged at groove respectively on the sidewall of selecting grid; A plurality of control grids are inserted in adjacent two a little grooves of selecting between the grid; Many word lines are arranged in parallel on column direction and connect the control grid of same row; Select gate lines on line direction, to be arranged in parallel to connect selection grid for many with delegation; Multiple bit lines is arranged in parallel on line direction, is arranged in the substrate of beneath trenches; Wherein adjacent two control grids on the column direction, the selection grids of adjacent two controls between the grids with constitute a memory cell respectively in abutting connection with two electric charge storage layers of selecting grid; In each memory cell, selecting the electric charge storage layer of first side of grid is first, selecting the electric charge storage layer of second side of grid is second: the method is included in when carrying out programming operations, applies first voltage in the selected word line that selected memory cell connected; The first selected bit line in the left side of car that is positioned at selected memory cell applies second voltage; The second selected bit line in the right side of car that is positioned at selected memory cell applies tertiary voltage; Selected selection gate line in selected memory cell applies the 4th voltage, and wherein the 4th voltage is near the start voltage of selecting grid, and second voltage is greater than tertiary voltage, and first voltage is greater than second voltage, to utilize first of source side injection effect sequencing.
In the method for operation of above-mentioned non-volatility memorizer, first voltage is about 8 volts, and second voltage is about 5 volts, and tertiary voltage is about 0 volt, and the 4th voltage is about 2 volts.
In the method for operation of above-mentioned non-volatility memorizer, also be included in when carrying out programming operations, apply first voltage in the selected word line that selected memory cell connected; The first selected bit line in the left side of car that is positioned at selected memory cell applies tertiary voltage; The second selected bit line in the right side of car that is positioned at selected memory cell applies second voltage; Selected selection gate line in selected memory cell applies the 4th voltage, and wherein the 4th voltage is near the start voltage of selecting grid, and second voltage is greater than tertiary voltage, and first voltage is greater than second voltage, to utilize second of source side injection effect sequencing.
In the method for operation of above-mentioned non-volatility memorizer, first voltage is about 8 volts, and second voltage is about 5 volts, and tertiary voltage is about 0 volt, and the 4th voltage is about 2 volts.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out programming operations, be included in not selected selection gate line for applying the 5th voltage, make the pathway closure of not selected selection grid below.The 5th voltage is about-1 volt.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out erase operation for use, apply the 6th voltage in word line, apply the 7th voltage in substrate, so that the electronics that is stored in the electric charge storage layer imports in the word line, wherein a voltage difference of the 6th voltage and the 7th voltage can cause the FN tunneling effect.
In the method for operation of above-mentioned non-volatility memorizer, voltage difference is about 12 to 20 volts.The 6th voltage is 15 volts, and the 7th voltage is 0 volt.
In the method for operation of above-mentioned non-volatility memorizer, the 6th voltage is 10 volts, and the 7th voltage is-5 volts.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out erase operation for use, in selecting gate line to apply the 8th voltage, apply the 9th voltage in substrate, so that the electronics that is stored in the electric charge storage layer imports in the selection gate line, wherein the voltage difference of the 8th voltage and the 9th voltage can cause the FN tunneling effect.
In the method for operation of above-mentioned non-volatility memorizer, voltage difference is about 12 to 20 volts.The 8th voltage is about 15 volts, and the 9th voltage is about 0 volt.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out read operation, apply the tenth voltage in the selected word line that selected memory cell connected; The first selected bit line in the left side of car that is positioned at this selected memory cell applies the 11 voltage; The second selected bit line in the right side of car that is positioned at selected memory cell applies the 12 voltage; Selected selection gate line in selected memory cell applies the 13 voltage, to read first, the 11 voltage is greater than the 12 voltage, and the tenth voltage is greater than the start voltage of the memory cell of not depositing electronics and less than the start voltage of the memory cell that has electronics.
In the method for operation of above-mentioned non-volatility memorizer, the tenth voltage is that the 11 voltage is about 1.5 volts about 5 volts～7 volts, and the 12 voltage is about 0 volt, and the 13 voltage is about 4 volts.
In the method for operation of above-mentioned non-volatility memorizer, when carrying out read operation, apply the tenth voltage in the selected word line that selected memory cell connected; The first selected bit line in the left side of car that is positioned at selected memory cell applies the 12 voltage; The second selected bit line in the right side of car that is positioned at selected memory cell applies the 11 voltage; Selected selection gate line in selected memory cell applies the 13 voltage, to read second, the 11 voltage is greater than the 12 voltage, and the tenth voltage is greater than the start voltage of the memory cell of not depositing electronics and less than the start voltage of those memory cell that have electronics.
In the method for operation of above-mentioned non-volatility memorizer, the tenth voltage is that the 11 voltage is about 1.5 volts about 5 volts～7 volts, and the 12 voltage is about 0 volt, and the 13 voltage is about 4 volts.
In the method for operation of non-volatility memorizer of the present invention, it utilizes source side injection effect (Source-Side Injection, SSI) the single position with single memory cell is that unit carries out sequencing, and utilizes the FN tunneling effect to carry out erasing of memory cell.Therefore, its electron injection efficiency is higher, thus can reduce the memory cell current when operating, and can improve service speed simultaneously.Therefore, current drain is little, can effectively reduce the power loss of entire chip.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Figure 1A illustrate is the top view of a preferred embodiment of non-volatility memorizer of the present invention.
Figure 1B for illustrate among Figure 1A along the section of structure of A-A ' line.
Fig. 1 C for illustrate among Figure 1A along the section of structure of B-B ' line.
Fig. 2 illustrate is the electrical schematic diagram of the memory array of a preferred embodiment of the present invention.
Fig. 3 A is the schematic diagram of an example of the programming operations of non-volatility memorizer of the present invention.
Fig. 3 B is the schematic diagram of another example of the programming operations of non-volatility memorizer of the present invention.
Fig. 3 C is the schematic diagram of an example of the read operation of non-volatility memorizer of the present invention.
Fig. 3 D is the schematic diagram of another example of the read operation of non-volatility memorizer of the present invention.
Fig. 3 E is the schematic diagram of an example of the erase operation for use of non-volatility memorizer of the present invention.
Fig. 3 F is the schematic diagram of an example of the erase operation for use of non-volatility memorizer of the present invention.
Fig. 4 A to Fig. 4 E is the manufacturing process profile that illustrates a preferred embodiment of non-volatility memorizer of the present invention.
The simple symbol explanation
100,200: substrate
102: component isolation structure
104a～104c: select grid structure
106a～106f, 214a, 214b: electric charge storage layer
108a～108e: control grid.
112a～112d, 210: groove
114: select gate dielectric
116: select grid
118,206,206a: cap layer
120,216: clearance wall
122: wedge angle
124,212: tunneling dielectric layer
126,220: dielectric layer between grid
128a～128d: doped region (source/drain regions)
130,224: resist and wear doped region
202,202a: dielectric layer
204: conductor material layer
208: select grid structure
204a, 222: conductor layer
214: the charge storage material layer
218: source/drain regions
M11～M33: memory cell
WL1～WL3: word line
SG1～SG3: select gate line
BL1～BL4: bit line
Embodiment
Figure 1A illustrate is the top view of a preferred embodiment of non-volatility memorizer of the present invention.Figure 1B for illustrate among Figure 1A along the section of structure of A-A ' line.Fig. 1 C for illustrate among Figure 1A along the section of structure of B-B ' line.
Please refer to Figure 1A, the array of non-volatility memorizer of the present invention comprises substrate 100, a plurality of memory cell M11～M33, many word line WL1～WL3, many selection gate line SG1～SG3, bit line BL1～BL4.
Memory cell M11～M33 is arranged in the substrate 100 and is arranged in rows/column array.Many word line WL1～WL3 connect the control grid of same array storage unit respectively, and many word line WL1～WL3 for example are arranged in parallel, and extend toward directions X.Select gate line SG1～SG3 to connect the selection grid of same line storage unit respectively, select gate line SG1～SG3 for example to be arranged in parallel, and extend, and directions X interlocks with the Y direction toward the Y direction.Bit line BL1～BL4 connects the source/drain regions of same line storage unit respectively, and bit line BL1～BL4 for example is arranged in parallel, and extends toward the Y direction, and its memory cell of adjacent two can be shared a bit lines (source/drain regions).
The structure of non-volatility memorizer of the present invention then, is described.At this memory cell M11～memory cell M13 that only is connected in series with word line WL1 is that example explains.
Please be simultaneously with reference to Figure 1A, Figure 1B, Fig. 1 C, non-volatile memory structure of the present invention comprises substrate 100, a plurality of selection grid structure 104a～104c, a plurality of charge storing structure 106a～106f, a plurality of control grid 108a～108e.
Selecting grid structure 104a～104c for example is in the substrate 100 that is arranged at respectively between adjacent two groove 112a～112d.Select grid structure 104a～104c to comprise respectively and select gate dielectric 114, select grid 116, cap layer 118 and clearance wall 120.Selecting gate dielectric 114 for example is to be arranged to select between grid 116 and the substrate 100.Selecting the material of gate dielectric 104 for example is silica.Selecting the material of grid 116 for example is doped polycrystalline silicon.Cap layer 118 is arranged at selects grid 116 tops.The material of cap layer 118 comprises insulating material, for example is silica, silicon nitride etc.Clearance wall 120 is arranged at the sidewall of selecting grid 116.The material of clearance wall 120 comprises insulating material, for example is silica, silicon nitride etc.Select gate line SG1～SG3 to connect the selection grid 116 of same line storage unit respectively.
Electric charge storage layer 106a～106f for example is the sidewall that is arranged at groove 112a～112d respectively.But the material that the material of electric charge storage layer 106a～106f comprises store charge for example conductor material (as: doped polycrystalline silicon) or electric charge is absorbed in material (as: silicon nitride).When the material of electric charge storage layer 106a～106f was doped polycrystalline silicon, electric charge storage layer 106a～106f was as floating grid.Shown in Figure 1B, can select whether to form wedge angle 122 in abutting connection with selection grid structure 104a～104c part at electric charge storage layer 106a～106f.This wedge angle 122 helps the erase operation for use of memory cell.Be provided with tunneling dielectric layer 124 between each electric charge storage layer 106a～106f and substrate 100, the material of tunneling dielectric layer 124 for example is a silica.
A plurality of control grid 108a～108d are arranged at respectively in the substrate 100, and insert the groove 112a～112d (shown in Figure 1B) between two adjacent selection grid structure 104a～104c.Control grid 108a～108d is serially connected by word line WL1.Wherein, control grid 108a～108d and word line WL1 for example are integrated, that is control grid 108a～108d extends to and selects grid structure 104a～104c top and be connected to each other together and formation word line WL1.The material of control grid 108a～108d (word line WL1) comprises conductor material, for example is doped polycrystalline silicon.Between each electric charge storage layer 106a～106f and control grid 108a～108d, be provided with dielectric layer 126 between grid.The material of dielectric layer 126 comprises insulating material between grid, and it can be made of one or more layers of composite bed, for example is silicon oxide layer, silicon oxide/nitride layer, silicon oxide/silicon nitride/silicon oxide etc.
A plurality of doped region 128a～128d (source/drain regions) are arranged at respectively in the substrate 100 of groove 112a～112d bottom.These doped regions 128a～128d (source/drain regions) extends toward Y direction (Figure 1A), and constitutes bit line BL1～BL4.For example be to be provided with to resist to wear doped region 130 in the substrate 100 between the line BL1～BL4 of two-phase ortho position.Doped region 130 is worn in this resistance can avoid abnormal electrical perforation between the line BL1～BL4 of two-phase ortho position.
Shown in Figure 1B, the two electric charge storage layer 106a～106f of adjacent two control grid 108a～108d, the selection grid structure 104a～104c between adjacent two control grid 108a～108d, adjacency selection grid structure 104a～104c and the doped region 128a～128d (source/drain regions) in abutting connection with two electric charge storage layer 106a～106f constitute a plurality of memory cell M11～M3 respectively.
For instance, control grid 108a, control grid 108b, select grid structure 104a with in abutting connection with the two electric charge storage layer 106a～106b that select grid structure 104a, constitute memory cell M11 in abutting connection with doped region 128a～128b (source/drain regions) of two electric charge storage layer 106a～106b; Control grid 108b, control grid 108c, select grid structure 104b and constitute memory cell M12 in abutting connection with two electric charge storage layer 106c～106d of selection grid structure 104a, doped region 128b～128c (source/drain regions) of adjacency two electric charge storage layer 106c～106d; Control grid 108c, control grid 108d, select grid structure 104c and constitute memory cell M13 in abutting connection with two electric charge storage layer 106e～106f of selection grid structure 104c, doped region 128c～128d (source/drain regions) of adjacency two electric charge storage layer 106a～106e.Memory cell M11～M13 does not have the gap each other at directions X (column direction) and is serially connected, and adjacent memory unit M11～M13 shares control grid 108b～108c and doped region 128b～128c (source/drain regions) (bit line BL2～BL3).For instance, memory cell M12 and memory cell M11 share control grid 108b and doped region 128b (source/drain regions) (bit line BL2) and memory cell M13 and memory cell M12 shared control grid 108c and doped region 128c (source/drain regions) (bit line BL3).
Electric charge storage layer 106a～106e of each memory cell M11～M13 can store one data respectively.With memory cell M11 is example, and the electric charge storage layer 106a (position, a left side) that is arranged at the left side of selecting grid structure 104a can store one data, selects the electric charge storage layer 106b (right position) on the right side of grid structure 104a also can store one data.Same, memory cell M12～M13 also has two electric charge storage layers (position, a left side and right position) respectively.So the single memory cell of non-volatility memorizer of the present invention can store two data.In addition, the structure of the memory cell M21～M33 that is connected in series by word line WL2～WL3 is identical with memory cell M11～M13, does not repeat them here.
In above-mentioned non-volatility memorizer because between memory cell M11～M13, do not have the gap, therefore can promote the integrated level of column of memory cells.And, can store one data respectively at the electric charge storage layer 106a～106e of the two side of each groove 112a～112d (in abutting connection with two electric charge storage layers of selecting grid structure), that is the single memory cell of non-volatility memorizer of the present invention can store two data.And, by the degree of depth of control groove 112a～112e, passage length that also can the control store unit, and avoid the abnormal electrical perforation of memory cell.
In the above-described embodiments, so that being serially connected, 3 memory cell M11～M13 do explanation for example.Certainly, the number of Chuan Jie memory cell can be looked the suitable number of actual needs serial connection in the present invention, and for instance, same word line can be connected in series 32 to 64 memory cell.
Fig. 2 illustrate is the electrical schematic diagram of the memory array of a preferred embodiment of the present invention.At this, be example to contain 9 memory cell in the memory array, so that the operator scheme of memory array of the present invention to be described.Fig. 3 A is the schematic diagram of an example of the programming operations of non-volatility memorizer of the present invention.Fig. 3 B is the schematic diagram of another example of the programming operations of non-volatility memorizer of the present invention.Fig. 3 C is the schematic diagram of an example of the read operation of non-volatility memorizer of the present invention.Fig. 3 D is the schematic diagram of another example of the read operation of non-volatility memorizer of the present invention.Fig. 3 E is the schematic diagram of an example of erase operation for use of the present invention.Fig. 3 F is the schematic diagram of another example of erase operation for use of the present invention.
Please refer to Fig. 2, column of memory cells comprises 9 memory cell M11～M33, selects gate line SG1～SG3, word line WL1～WL3, bit line BL1～BL4.
Each memory cell M11～M33 comprises selection grid, control grid and two electric charge storage layers, two source/drain regions respectively, and adjacent two memory cell can be shared a control grid and a source/drain regions.
Each column of memory cells for example is to be serially connected by 3 memory cell, and for instance, memory cell M11～M13 is serially connected; Memory cell M21～M23 is serially connected; Memory cell M31～M33 is serially connected.
Word line WL1～WL3 connects the control grid of same array storage unit respectively, and for instance, word line WL1 connects the control grid of memory cell M11～M13; Word line WL2 connects the control grid of memory cell M21～M23; Word line WL3 connects the control grid of memory cell M31～M33.
Select gate line SG1～SG3 to connect the selection grid of same line storage unit respectively.For instance, select gate line SG1 to connect the selection grid of memory cell M11～M31; Select gate line SG2 to connect the selection grid of memory cell M12～M32; Select gate line SG3 to connect the selection grid of memory cell M13～M33.
With regard to the method for operation of non-volatility memorizer of the present invention, below only provide a preferred embodiment as an illustration.But the method for operation of non-volatility memorizer of the present invention is not limited to these methods.In following explanation, all be to be that example is done explanation with memory cell M22.
Please be simultaneously with reference to Fig. 2 and Fig. 3 A, when programming operations, depositing electronics in the electric charge storage layer A (right position) in memory cell M22 is that example is done explanation, and the selected word line WL2 that is connected in selected memory cell M22 applies voltage Vp1, and this voltage Vp1 for example is about 8 volts.In being positioned at electric charge storage layer A (right position) side and the selected bit line BL3 adjacent with electric charge storage layer A (right position) applies voltage Vp2, this voltage Vp2 for example is about 5 volts.In being positioned at electric charge storage layer B (left side position) side and the selected bit line BL2 adjacent with electric charge storage layer B (position, a left side) applies voltage Vp3, this voltage Vp3 for example is about 0 volt.Apply voltage Vp4 in the selected gate line SG2 that selects, this voltage Vp4 for example is about 2 volts.(Source-Side Injection, SSI) effect make the electronics iunjected charge store a layer A (right position), and the right position of sequencing memory cell M22 to utilize source side.In this operation, voltage Vp4 is near the start voltage of selecting grid, and voltage Vp2 is greater than voltage Vp3, and voltage Vp1 is greater than voltage Vp2, and (Source-Side Injection, SSI) effect is carried out programming operations so that utilize source side.And other selected selection gate line SG1, SG3 etc. also can apply voltage Vp5, and this voltage Vp5 for example is the voltage of 0 volt or negative voltage (1 volt), make the pathway closure of not selected selection grid below.
In the said procedure operation, because the control grid of non-volatility memorizer of the present invention is inserted in the groove of substrate, when electronics moves from bit line BL2 toward bit line BL3, therefore electronics can obtain higher injection efficiency through can directly injecting the electric charge storage layer A (right position) of trenched side-wall after quickening.
Please deposit electronics in the electric charge storage layer B (position, a left side) that is illustrated in memory cell M22 simultaneously with reference to Fig. 2 and Fig. 3 B, and the position, a left side of sequencing memory cell M22.The selected word line WL2 that is connected in selected memory cell M22 applies voltage Vp1, and this voltage Vp1 for example is about 8 volts.In being positioned at electric charge storage layer B (left side position) side and the selected bit line BL2 adjacent with electric charge storage layer B (position, a left side) applies voltage Vp2, this voltage Vp2 for example is about 5 volts.In being positioned at electric charge storage layer A (right position) side and the selected bit line BL3 adjacent with electric charge storage layer A (right position) applies voltage Vp3, this voltage Vp3 for example is about 0 volt.Apply voltage Vp4 in the selected gate line SG2 that selects, this voltage Vp4 for example is about 2 volts.(Source-Side Injection, SSI) effect make the electronics iunjected charge store a layer A (right position), and the right position of sequencing memory cell M22 to utilize source side.In this operation, voltage Vp4 is near the start voltage of selecting grid, and voltage Vp2 is greater than voltage Vp3, and voltage Vp1 is greater than voltage Vp2, and (Source-Side Injection, SSI) effect is carried out programming operations so that utilize source side.And other selected selection gate line SG1, SG3 etc. also can apply voltage Vp5, and this voltage Vp5 for example is the voltage of 0 volt or negative voltage (1 volt), make the pathway closure of not selected selection grid below.Same, because the control grid of non-volatility memorizer of the present invention is inserted in the groove of substrate, when electronics moved from bit line BL3 toward bit line BL2, therefore electronics can obtain higher efficient through can directly injecting the electric charge storage layer B (position, a left side) of trenched side-wall after quickening.
Please be simultaneously with reference to Fig. 2 and Fig. 3 C, when the electric charge storage layer A (right position) of reading cells M22, the selected word line that is connected in selected memory cell M22 applies voltage Vr1, and this voltage Vr1 for example is about 5 volts～7 volts.In being positioned at electric charge storage layer A (right position) side and the selected bit line BL3 adjacent with electric charge storage layer A (right position) applies voltage Vr2, this voltage Vr2 for example is about 1.5 volts.In being positioned at electric charge storage layer B (left side position) side and the selected bit line BL2 adjacent with electric charge storage layer B (position, a left side) applies voltage Vr3, this voltage Vr3 for example is about 0 volt.Apply voltage Vr4 in the selected gate line SG2 that selects, this voltage Vr4 for example is about 4 volts.Right position with reading cells M22.In this operation, voltage Vr2 is greater than voltage Vr3, and voltage Vr1 should be greater than the start voltage of the memory cell of not depositing electronics and less than the start voltage of the memory cell that has electronics.
Please be simultaneously with reference to Fig. 2 and Fig. 3 D, when the electric charge storage layer B (position, a left side) of reading cells M22, the selected word line that is connected in selected memory cell M22 applies voltage Vr1, and this voltage Vr1 for example is about 3 volts～7 volts.In being positioned at electric charge storage layer B (left side position) side and the selected bit line BL3 adjacent with electric charge storage layer B (position, a left side) applies voltage Vr2, this voltage Vr2 for example is about 1.5 volts.In being positioned at electric charge storage layer A (right position) side and the selected bit line BL2 adjacent with electric charge storage layer A (right position) applies voltage Vr3, this voltage Vr3 for example is about 0 volt.Apply voltage Vr4 in the selected gate line SG2 that selects, this voltage Vr4 for example is about 4 volts.Right position with reading cells M22.In this operation, voltage Vr2 is greater than voltage Vr3, and voltage Vr1 should be greater than the start voltage of the memory cell of not depositing electronics and less than the start voltage of the memory cell that has electronics.
When carrying out read operation, because total charge dosage is very little for the pathway closure and the electric current of negative memory cell in the electric charge storage layer at this moment, and in the electric charge storage layer passage of the slightly positive memory cell of total charge dosage open and electric current big, so can judge that the digital information that is stored in this memory cell is " 1 " or " 0 " by the channel switch/channel current size of memory cell.
Please be simultaneously with reference to Fig. 2 and Fig. 3 E, when erasing, selected word line applies voltage Ve1, apply voltage Ve2 in this substrate, make and select gate line SG1～SG3 for floating, so that be stored in the electronics importing word line in the electric charge storage layer, and the data in the memory cell are erased.The voltage difference of voltage Ve1 and voltage Ve2 can cause passage FN tunneling effect.The voltage difference of voltage Ve1 and voltage Ve2 for example is to be about 12 to 20 volts.For instance, voltage Ve1 is 15 volts, and voltage Ve2 is 0 volt of voltage; Ve1 is 10 volts, and voltage Ve2 is-5 volts.
In above-mentioned example, so that electronics removes via word line to example explains, the present invention can also adopt the mode that electronics is removed via selecting gate line certainly.Please be simultaneously with reference to Fig. 2 and Fig. 3 F, when erasing, the selected gate line of selecting applies voltage Ve1, apply voltage Ve2 in this substrate, make word line WL1～WL3 for floating, import and select in the gate line so that be stored in electronics in the electric charge storage layer, and the data in the memory cell are erased.The voltage difference of voltage Ve1 and voltage Ve2 can cause passage FN tunneling effect.The voltage difference of voltage Ve1 and voltage Ve2 for example is to be about 12 to 20 volts.For instance, voltage Ve1 is 15 volts, and voltage Ve2 is 0 volt of voltage; Ve1 is 10 volts, and voltage Ve2 is-5 volts.When employing makes the erasing method that electronics removes via selecting gate line, at electric charge storage layer in abutting connection with selecting the grid structure part preferably to have wedge angle.This wedge angle 122 helps the erase operation for use of memory cell.
In the method for operation of non-volatility memorizer of the present invention, it utilizes source side injection effect (Source-Side Injection, SSI) the single position with single memory cell is that unit carries out sequencing, and utilizes the FN tunneling effect to carry out erasing of memory cell.Therefore, its electron injection efficiency is higher, thus can reduce the memory cell current when operating, and can improve service speed simultaneously.Therefore, current drain is little, can effectively reduce the power loss of entire chip.
And, because the control grid of non-volatility memorizer of the present invention is inserted in the groove of substrate, after electronics is through acceleration, can directly inject the electric charge storage layer of trenched side-wall, therefore can obtain higher electron injection efficiency.
The manufacture method of non-volatility memorizer of the present invention then is described, Fig. 4 A to Fig. 4 E is the manufacturing process profile that illustrates the preferred embodiment of non-volatility memorizer of the present invention.Fig. 4 A to Fig. 4 E is for to illustrate along the profile of A-A ' line among Figure 1A.
At first, please refer to Fig. 4 A, substrate 200 is provided, this substrate 200 for example is a silicon base.Then in substrate 200, form component isolation structure (not illustrating).The formation method of component isolation structure for example is the shallow trench isolation method.Afterwards, in substrate 200, form one dielectric layer 202, one deck conductor material layer 204 and one deck cap layer 206 in regular turn.The material of dielectric layer 202 for example is a silica, and its formation method for example is a thermal oxidation method.The material of conductor material layer 204 for example is the polysilicon that mixes, the formation method of this conductor material layer 204 for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carries out the ion implantation step and utilizes chemical vapour deposition technique and form it in mode formations or that alloy is injected in employing when participating in the cintest.The material of cap layer 206 for example is a silicon nitride, and the formation method of cap layer 206 for example is a chemical vapour deposition technique.
Then, please refer to Fig. 4 B, pattern dielectric layer 202, conductor material layer 204 and cap layer 206 are to form a plurality of selection grid structures 208 in substrate 200.Select grid structure 208 to be constituted by dielectric layer 202a, conductor layer 204a and cap layer 206a.Conductor layer 204a is as selecting grid, and dielectric layer 202a is as selecting gate dielectric.With cap layer 206a is mask, removes part substrate 200, and forms a plurality of grooves 210 in substrate 200.The method that removes part substrate 200 comprises dry ecthing method, for example is reactive ion-etching.
Then, please refer to Fig. 4 C, form tunneling dielectric layer 212 in groove 210 surfaces.The material of tunneling dielectric layer 212 for example is a silica, and its formation method for example is a thermal oxidation method.Owing to adopt thermal oxidation method to form tunneling dielectric layer 212, therefore also can be formed with silicon oxide layer at conductor layer 204a.Then, in groove 210, form charge storage material layer 214.The material of charge storage material layer 214 comprises conductor material, for example is doped polycrystalline silicon, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carries out the ion implantation step and forms it.Then, carry out the etch-back step, remove the charge storage material layer 214 of part, so that the top of charge storage material layer 214 is lower than substrate 200 surfaces.
Then, please refer to Fig. 4 D, form clearance wall 216, and cover the upper surface of the charge storage material layer 214 of part in the sidewall of groove 210.Wherein, the material of clearance wall 216 for example is to have different etching selectivity persons with charge storage material layer 214.The formation method of clearance wall 216 for example is to form one deck insulation material layer (not illustrating) earlier, utilizes anisotropic etch process to remove the SI semi-insulation material layer then, and forms it.
Afterwards, be etching mask with cap layer 206a and clearance wall 216, remove the charge storage material layer 214 of part once more, form electric charge storage layer 214a and electric charge storage layer 214b with sidewall in groove 210.Electric charge storage layer 214a and electric charge storage layer 214b for example are as floating grid.
Then, in the substrate 200 of groove 210 bottoms, form source/drain regions 218.The formation method of source/drain regions 218 for example is an ion implantation technology.
Then, please refer to Fig. 4 E, in forming dielectric layer 220 between grid in the substrate 200.The material of dielectric layer 220 for example is a silicon oxide/silicon nitride/silicon oxide between grid.The formation method of dielectric layer 220 for example can utilize chemical vapour deposition technique to form silicon oxide layer, silicon nitride layer and silicon oxide layer in regular turn between grid.Certainly, the formation method of dielectric layer 220 also can be after forming silicon oxide layer with thermal oxidation method earlier, to form silicon nitride layer and another layer silicon oxide layer with chemical vapour deposition technique again between grid.And the material of dielectric layer 220 also can for example be silica or silica/silicon nitride between grid.
Then, form a plurality of conductor layers 222 in substrate 200, this conductor layer 222 fills up the groove 210 in the substrate 200.And these conductor layers 222 are arranged in parallel, and the bearing of trend of bearing of trend and conductor layer 204a (selection grid) is staggered.Conductor layer 222 for example is as word line.The formation step of conductor layer 222 (word line) for example is prior to forming one deck conductor material layer in the substrate 200, then utilize chemical mechanical milling method or etch-back method to carry out planarization, afterwards this conductor material layer of patterning and form many conductor layers 222 (word line).The material of this conductor layer for example is the polysilicon that mixes, and its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carries out the ion implantation step and forms it; Perhaps also can inject the mode of alloy when participating in the cintest, utilize chemical vapour deposition technique and form it.
Afterwards, form resistance in the substrate between the source/drain regions 218 200 and wear doped region 224.The formation method that doped region 224 is worn in resistance for example is an ion implantation technology.The follow-up technology of finishing memory array is known by those skilled in the art, does not repeat them here.
In the above-described embodiments, the formation step of electric charge storage layer 214a and electric charge storage layer 214b is with after forming clearance wall 216, is that to remove charge storage material layer 214 partly be that example is done explanation to etching mask with cap layer 206a and clearance wall 216.Certainly, the present invention can also not form clearance wall 216, and directly utilizes photoengraving carving technology patterning electric charge storage material layer 214 and formation electric charge storage layer 214a and electric charge storage layer 214b.
In the above-described embodiments, the material of charge storage material layer 214 is to be that example is done explanation with conductor material (doped polycrystalline silicon).Certainly, if electric charge storage layer 214 is that material is that electric charge is absorbed in material (for example silicon nitride) etc., have the characteristic of catching electronics because electric charge is absorbed in material (for example silicon nitride), the electronics among the iunjected charge storage material layer 214 can concentrate on the regional area of charge storage material layer 214.Therefore, just do not need to form component isolation structure and the technology that charge storage material layer 214 is divided into two.
In the above-described embodiments, because electric charge storage layer of the present invention (floating grid) is formed in the groove of substrate with the control grid, so its memory cell size can dwindle, and can increase the integrated level of element.Electric charge storage layer (in abutting connection with two electric charge storage layers of selecting grid structure) in the two side of each groove can store one data respectively, that is the single memory cell of non-volatility memorizer of the present invention can store two data.And, by the degree of depth of control groove, passage length that also can the control store unit, and avoid the abnormal electrical perforation of memory cell.In addition, the technology of non-volatility memorizer of the present invention is comparatively simple, and can promote the integrated level of memory array.
In addition, in the above-described embodiments, be that example is done explanation to form three memory cell structures.Certainly, use non-volatility memorizer manufacture method of the present invention, can look actual needs and form suitable number storage unit, for instance, same word line can be connected in series 32 to 64 memory cell structures.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (37)
1. non-volatility memorizer comprises:
One substrate is provided with at least two grooves in this substrate;
One selects gate dielectric and to select grid, is arranged in regular turn on this substrate surface between this two groove;
Two clearance walls and two electric charge storage layers are arranged at this two groove respectively on the sidewall of this selection grid, and wherein respectively this electric charge storage layer lays respectively at respectively this clearance wall below;
Two source/drain regions are arranged at respectively in this substrate of this two channel bottom; And
One control grid is arranged in this substrate, and fills up this two groove.
2. non-volatility memorizer as claimed in claim 1, wherein the material of this two electric charge storage layer comprises doped polycrystalline silicon.
3. non-volatility memorizer as claimed in claim 1, wherein the material of this two electric charge storage layer comprises silicon nitride.
4. non-volatility memorizer as claimed in claim 1, wherein this two electric charge storage layer has a wedge angle respectively in abutting connection with this selection grid part.
5. non-volatility memorizer as claimed in claim 1, wherein the material of this selection grid comprises doped polycrystalline silicon.
6. non-volatility memorizer as claimed in claim 1 wherein respectively is provided with a tunneling dielectric layer between this electric charge storage layer and this substrate.
7. non-volatility memorizer as claimed in claim 1 wherein is provided with dielectric layer between grid between this two electric charge storage layer and this control grid.
8. non-volatility memorizer comprises:
One substrate is provided with a plurality of grooves in this substrate, described a plurality of grooves extend toward a first direction;
A plurality of selection grids are arranged at respectively in this substrate between described a plurality of groove, and described a plurality of selection grids extend toward this first direction, and wherein respectively this substrate surface of this selection grid below is formed with a selection gate dielectric;
A plurality of clearance walls and a plurality of electric charge storage layer are arranged at the sidewall of described a plurality of grooves respectively, and wherein respectively this electric charge storage layer lays respectively at respectively this clearance wall below;
Multiple bit lines is arranged in this substrate of described a plurality of channel bottoms; And
Many word lines are set in parallel in this substrate, and fill up described a plurality of groove, and described many word lines extend toward a second direction, and this second direction and this first direction are staggered.
9. non-volatility memorizer as claimed in claim 8, the material of wherein said a plurality of electric charge storage layers comprises doped polycrystalline silicon.
10. non-volatility memorizer as claimed in claim 8, the material of wherein said a plurality of electric charge storage layers comprises silicon nitride.
11. non-volatility memorizer as claimed in claim 8, wherein respectively this electric charge storage layer has a wedge angle in abutting connection with this selection grid part respectively.
12. non-volatility memorizer as claimed in claim 8 wherein is provided with in this substrate between described multiple bit lines to resist and wears doped region.
13. non-volatility memorizer as claimed in claim 8 wherein respectively is provided with a tunneling dielectric layer between this electric charge storage layer and this substrate.
14. non-volatility memorizer as claimed in claim 8, wherein this electric charge storage layer and respectively be provided with dielectric layer between grid between this word line respectively.
15. non-volatility memorizer as claimed in claim 8, the described a plurality of electric charge storage layers that wherein are arranged at described a plurality of trenched side-walls are separated from each other.
16. the manufacture method of a non-volatility memorizer comprises:
One substrate is provided;
Form a plurality of first conductor layers in this substrate, described a plurality of first conductor layers extend toward a first direction, and wherein respectively this substrate surface of this first conductor layer below is formed with a gate dielectric layer;
With described a plurality of first conductor layers is mask, removes this substrate of part to form a plurality of grooves in this substrate;
Form one first dielectric layer and be covered in this substrate;
Form a clearance wall, one first electric charge storage layer and one second electric charge storage layer respectively in the two side of described a plurality of grooves, and this first electric charge storage layer and this second electric charge storage layer lay respectively at this clearance wall below;
In this substrate of described a plurality of channel bottoms, form a plurality of doped regions;
In this substrate, form one second dielectric layer; And
Form a plurality of second conductor layers in this substrate, described a plurality of second conductor layers extend toward a second direction, and fill up described a plurality of groove, and this second direction and this first direction are staggered.
17. the manufacture method of non-volatility memorizer as claimed in claim 16 is wherein in described many. the method that the two side of individual groove forms this clearance wall, this first electric charge storage layer and this second electric charge storage layer respectively comprises:
In this groove, insert a charge storage material layer;
Carry out an etch-back step, so that the top of this charge storage material layer is lower than this substrate surface;
Sidewall in described a plurality of grooves forms a clearance wall, and covers this charge storage material layer of part; And
With this clearance wall and described a plurality of first conductor layer is etching mask, removes this charge storage material layer of part, and forms this first electric charge storage layer and this second electric charge storage layer in the sidewall of this groove.
18. the manufacture method of non-volatility memorizer as claimed in claim 16, the method that wherein forms described a plurality of first conductor layers in this substrate comprises:
In this substrate, form a gate dielectric layer;
On this gate dielectric layer, form a conductor material layer;
On this conductor material layer, form a cap layer; And
This cap layer of patterning, this conductor material layer and this gate dielectric layer.
19. the manufacture method of non-volatility memorizer as claimed in claim 16, wherein the material of this first electric charge storage layer and this second electric charge storage layer comprises doped polycrystalline silicon.
20. the manufacture method of non-volatility memorizer as claimed in claim 16, wherein the material of this first electric charge storage layer and this second electric charge storage layer comprises silicon nitride.
21. the method for operation of a non-volatility memorizer is applicable to a memory array, this memory array comprises: a plurality of selection grids are arranged in the substrate, and have a groove respectively in adjacent two these substrates of selecting between the grid; A plurality of electric charge storage layers are arranged at this groove respectively on the sidewall of described a plurality of selection grids; A plurality of control grids are inserted in adjacent two these grooves of selecting between the grid; Many word lines, being arranged in parallel on column direction connects described a plurality of control grids of same row; Select gate line for many, the described a plurality of selection grids of connection with delegation are arranged in parallel on line direction; Multiple bit lines is arranged in parallel on line direction, is arranged in this substrate of this beneath trenches; Wherein at adjacent two control grids on the column direction, select grid and two electric charge storage layers to constitute a memory cell respectively in abutting connection with this selection grid at adjacent two controls one between grids; Respectively in this memory cell, this electric charge storage layer of one first side of this selection grid is one first, and this electric charge storage layer of one second side of this selection grid is one second: this method comprises:
When carrying out programming operations, a selected word line that is connected in a selected memory cell applies one first voltage; One first selected bit line in this left side of car that is positioned at this selected memory cell applies one second voltage; One second selected bit line in this right side of car that is positioned at this selected memory cell applies a tertiary voltage; Selected gate line of selecting in this selected memory cell applies one the 4th voltage, wherein the 4th voltage is selected the start voltage of grid near this, this second voltage is greater than this tertiary voltage, and this first voltage is greater than this second voltage, to utilize this first of source side injection effect sequencing.
22. the method for operation of non-volatility memorizer as claimed in claim 21, wherein this first voltage is 8 volts, and this second voltage is 5 volts, and this tertiary voltage is 0 volt, and the 4th voltage is 2 volts.
23. the method for operation of non-volatility memorizer as claimed in claim 21 also comprises applying this first voltage in this selected word line that this selected memory cell connected when carrying out programming operations; This first selected bit line in this left side of car that is positioned at this selected memory cell applies this tertiary voltage; This second selected bit line in this right side of car that is positioned at this selected memory cell applies this second voltage; Selected gate line apply the 4th voltage in should selecting of this selected memory cell, wherein the 4th voltage is selected the start voltage of grid near this, this second voltage is greater than this tertiary voltage, and this first voltage is greater than this second voltage, to utilize this second of source side injection effect sequencing.
24. the method for operation of non-volatility memorizer as claimed in claim 23, wherein this first voltage is 8 volts, and this second voltage is 5 volts, and this tertiary voltage is 0 volt, and the 4th voltage is 2 volts.
25. the method for operation of non-volatility memorizer as claimed in claim 21 when wherein carrying out programming operations, is included in not selected described a plurality of selection gate lines for applying one the 5th voltage, makes the pathway closure of not selected described a plurality of selection grids below.
26. the method for operation of non-volatility memorizer as claimed in claim 25, wherein the 5th voltage is-1 volt.
27. the method for operation of non-volatility memorizer as claimed in claim 21, also be included in when carrying out erase operation for use, apply one the 6th voltage in described many word lines, apply one the 7th voltage in this substrate, so that the electronics that is stored in described a plurality of electric charge storage layer imports in described many word lines, wherein a voltage difference of the 6th voltage and the 7th voltage can cause the FN tunneling effect.
28. the method for operation of non-volatility memorizer as claimed in claim 27, wherein this voltage difference is 12 to 20 volts.
29. the method for operation of non-volatility memorizer as claimed in claim 27, wherein the 6th voltage is 15 volts, and the 7th voltage is 0 volt.
30. the method for operation of non-volatility memorizer as claimed in claim 27, wherein the 6th voltage is 10 volts, and the 7th voltage is-5 volts.
31. the method for operation of non-volatility memorizer as claimed in claim 21, also be included in when carrying out erase operation for use, select gate line to apply one the 8th voltage in described many, apply one the 9th voltage in this substrate, so that the electronics that is stored in described a plurality of electric charge storage layer imports in described many selection gate lines, wherein a voltage difference of the 8th voltage and the 9th voltage can cause the FN tunneling effect.
32. the method for operation of non-volatility memorizer as claimed in claim 31, wherein this voltage difference is 12 to 20 volts.
33. the method for operation of non-volatility memorizer as claimed in claim 31, wherein the 8th voltage is 15 volts, and the 9th voltage is 0 volt.
34. the method for operation of non-volatility memorizer as claimed in claim 21, wherein when carrying out read operation, a selected word line that is connected in a selected memory cell applies 1 the tenth voltage; This first selected bit line in this left side of car that is positioned at this selected memory cell applies 1 the 11 voltage; This second selected bit line in this right side of car that is positioned at this selected memory cell applies 1 the 12 voltage; Selected gate line apply the 13 voltage in should selecting of this selected memory cell, to read this first, the 11 voltage is greater than the 12 voltage, and the tenth voltage is greater than the start voltage of described a plurality of memory cell of not depositing electronics and less than the start voltage of the described a plurality of memory cell that have electronics.
35. the method for operation of non-volatility memorizer as claimed in claim 34, wherein the tenth voltage is 5 volts～7 volts, and the 11 voltage is 1.5 volts, and the 12 voltage is 0 volt, and the 13 voltage is 4 volts.
36. the method for operation of non-volatility memorizer as claimed in claim 21 wherein when carrying out read operation, applies the tenth voltage in this selected word line that this selected memory cell connected; This first selected bit line in this left side of car that is positioned at this selected memory cell applies the 12 voltage; This second selected bit line in this right side of car that is positioned at this selected memory cell applies the 11 voltage; Selected gate line apply the 13 voltage in should selecting of this selected memory cell, to read this second, the 11 voltage is greater than the 12 voltage, and the tenth voltage is greater than the start voltage of described a plurality of memory cell of not depositing electronics and less than the start voltage of the described a plurality of memory cell that have electronics.
37. the method for operation of non-volatility memorizer as claimed in claim 36, wherein the tenth voltage is 5 volts～7 volts, and the 11 voltage is 1.5 volts, and the 12 voltage is 0 volt, and the 13 voltage is 4 volts.
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| TWI594247B (en) * | 2015-03-10 | 2017-08-01 | 物聯記憶體科技股份有限公司 | Non-volatile memory and erasing method thereof |
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Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5382534A (en) * | 1994-06-06 | 1995-01-17 | United Microelectronics Corporation | Field effect transistor with recessed buried source and drain regions |
| US5739567A (en) * | 1992-11-02 | 1998-04-14 | Wong; Chun Chiu D. | Highly compact memory device with nonvolatile vertical transistor memory cell |
| US20030080356A1 (en) * | 2001-11-01 | 2003-05-01 | Takashi Miida | Semiconductor memory having storage cells storing multiple bits and a method of manufacturing the same |
| US6812120B1 (en) * | 2004-02-26 | 2004-11-02 | Powerchip Semiconductor Corp. | Method of forming floating gate of memory device |
| US20040232473A1 (en) * | 2003-05-22 | 2004-11-25 | Cheng-Yuan Hsu | [flash memory cell, flash memory cell array and manufacturing method thereof] |
-
2005
- 2005-08-19 CN CNB200510092106XA patent/CN100461374C/en not_active Expired - Fee Related
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5739567A (en) * | 1992-11-02 | 1998-04-14 | Wong; Chun Chiu D. | Highly compact memory device with nonvolatile vertical transistor memory cell |
| US5382534A (en) * | 1994-06-06 | 1995-01-17 | United Microelectronics Corporation | Field effect transistor with recessed buried source and drain regions |
| US20030080356A1 (en) * | 2001-11-01 | 2003-05-01 | Takashi Miida | Semiconductor memory having storage cells storing multiple bits and a method of manufacturing the same |
| US20040232473A1 (en) * | 2003-05-22 | 2004-11-25 | Cheng-Yuan Hsu | [flash memory cell, flash memory cell array and manufacturing method thereof] |
| US6812120B1 (en) * | 2004-02-26 | 2004-11-02 | Powerchip Semiconductor Corp. | Method of forming floating gate of memory device |
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