CN100463209C - 具有真空夹层的相变存储器元件 - Google Patents

具有真空夹层的相变存储器元件 Download PDF

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CN100463209C
CN100463209C CNB200610144786XA CN200610144786A CN100463209C CN 100463209 C CN100463209 C CN 100463209C CN B200610144786X A CNB200610144786X A CN B200610144786XA CN 200610144786 A CN200610144786 A CN 200610144786A CN 100463209 C CN100463209 C CN 100463209C
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CN1971931A (zh
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龙翔澜
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Macronix International Co Ltd
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H10N70/063—Patterning of the switching material by etching of pre-deposited switching material layers, e.g. lithography
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe
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    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/884—Other compounds of groups 13-15, e.g. elemental or compound semiconductors
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
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    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/90—Bulk effect device making

Abstract

一种存储器器件，包含相变元件及真空夹层。所述器件包括第一电极元件；相变元件，与该第一电极元件接触；上电极元件，与该相变元件接触；位线电极，与该上电极元件接触；以及电介质填充层，环绕于该相变元件与该上电极元件之间，与两者分离且由该位线电极所封闭以定义环绕于该相变元件与该上电极元件之间的真空夹层。

Description

具有真空夹层的相变存储器元件
相关申请信息
本发明主张于2005年11月21日的美国临时专利申请的优先权，该申请案的申请号为60/738,956，发明名称为“VACUUM JACKETFOR PHASE CHANGE MEMORY ELEMENT”。
联合研究合约的当事人
纽约国际商业机械公司、台湾旺宏国际股份有限公司以及德国英飞凌技术公司(Infineon Technologies A.G.)为联合研究合约的当事人。
发明领域
本发明涉及非易失性存储器器件，特别是使用相变材料为基础的存储器器件。
背景技术
以相变为基础的存储器材料被广泛地应用于读写光盘中。这些材料包括有至少两种固相，包括例如通常为非晶固相，以及通常为结晶固相。激光脉冲用于读写光盘中，以在二种相之间进行切换，并读取该材料在相变之后的光学性质。
例如硫属化物及类似材料的这些相变存储器材料，可通过对其施加其幅度合适于于集成电路中的电流，而致使其晶相变。一般而言，非晶态的特征是其电阻高于结晶态，此电阻值可轻易测量得到而用来作为指示。这种特性则引发了使用可编程电阻材料来形成非易失性存储器电路等的兴趣，此电路可用于随机存取读写。
从非晶态转变至结晶态一般是低电流步骤。从结晶态转变至非晶态(以下称为重置(reset))一般是高电流步骤，其包括短暂的高电流密度脉冲以融化或破坏结晶结构，其后此相变材料会快速冷却，抑制相变的过程，使得至少部份相变结构得以维持在非晶态。在理想状态下，致使相变材料从结晶态转变至非晶态的重置电流幅度应该是越低越好。可以通过减小在存储器单元中的相变材料元件的尺寸、以及减少电极与此相变材料的接触面积来实现降低重置所需的重置电流幅度的目的，因此可针对此相变材料元件施加较小的绝对电流值来实现较高的电流密度。
该领域发展的一种方法是致力于在集成电路结构上形成微小孔洞，并使用微量可编程的电阻材料填充这些微小孔洞。致力于这种微小孔洞的专利包括：于1997年11月11日公告的美国专利No.5,687,112“Multibit Single Cell Memory Element Having TaperedContact”、发明人为Ovshinky；于1998年8月4日公告的美国专利No.5,789,277“Method of Making Chalogenide[sic]Memory Device”、发明人为Zahorik等；于2000年11月21日公告的美国专利No.6,150,253“Controllable Ovonic Phase-Change SemiconductorMemory Device and Methods of Fabricating the Same”、发明人为Doan等；以及于1999年7月6日公告的美国专利No.5,920,788“Chalcogenide Memory Cell with a Plurality of ChalcogenideElectrodes”、发明人为Reinbergs。
已知的相变存储器与结构的一个特别问题是已知技术中的热槽效应(heat sink effect)。一般而言，现有技术中指出了在相变存储器元件的双面上使用金属电极的方式，且此电极的尺寸大约与相变元件相同。这种电极用作为热槽，此金属的高导热性快速地将热量抽离此相变材料。由于相变现象是加热作用的结果，因此该热槽效应则导致其需要较高的电流方能产生理想的相变。
一种解决该热流问题的方法见于美国专利第6,815,704号“SelfAligned Air-Gap Thermal Insulation for Nano-scale InsulatedChalcogenide Eletronics(NICE)RAM(用于纳米级绝缘硫属化物电子(NICE)RAM的自动对准空气间隙热绝缘的)”，其中尝试将存储器单元绝缘。此结构及其对应的制造过程，却是十分复杂，且仍无法在该存储器器件中提供较小的电流。
因此，需要提供一种存储器单元结构，其具有小尺寸以及低重置电流，以及一种用于解决上述热传导问题的结构，以及用于制造该结构的方法，其可满足大规模生产存储器器件时的严格的制造过程变量规格。因此还希望提供一种制造程序以及一种结构，其与同一集成电路的周边电路的制造程序兼容。
发明内容
本发明的目的是提供一种存储器器件，包含相变元件及真空夹层(jacket)。此器件包括第一电极元件；相变元件，与该第一电极元件接触；上电极元件，与该相变元件接触；位线电极，与该上电极元件接触；以及电介质填充层，环绕于该相变元件与该上电极元件之间，与两者分离且由该位线电极所封闭以定义环绕于该相变元件与该上电极元件之间的真空夹层。
附图说明
图1示出了本发明的存储器元件的简单示意图；
图2a到图2c示出了本发明的相变存储器元件的一些可替换实施例的示意图；以及
图3a到3k示出了根据图1所示的本发明实施例的制造过程流程示意图。
【主要组件符号说明】
10，10a，10b   相变随机存取存储器
12             衬底
14             栓塞
15a，15b       字线
17             公共源极线
18             阻挡层
20，20a，20b   相变元件
22            中央部份
24，24a，24b  真空夹层
26            绝缘电介质层
28，28a，28b  上电极元件
30            位线
50a，50b      光阻图案
120           相变材料
128           电极材料
具体实施方式
本发明关于各实施例的讨论是参考图1-3。可以了解的是，在实施例中所示的各项特征仅用于举例目的、并用于说明其本质，而并非用于限制本发明的范畴。本发明的范畴仅由权利要求的范围所界定。本领域技术人员根据以下描述将能够了解很多等效的变换形式。
本发明涉及存储器元件以及存储器单元。本领域技术人员能够轻易了解，存储器单元是用于维持电荷或状态以指示单一数据位的逻辑电平的电路器件。举例而言，存储器单元排列成阵列以提供计算机使用的随机存取存储器。在某些存储器单元中，存储器元件执行了实际维持电荷或状态的功能。举例而言，在已知的动态随机存取存储器单元中，电容器指示该单元的逻辑电平，完全充电状态指示逻辑“l”(或高状态)，而完全放电状态则指示逻辑“0”(或低状态)。
图1示出了本发明的存储器元件10的简单示意图。为了清晰起见，图中的存储器元件10仅显示了单一单元。现实中，每一个元件都是存储器单元的一部份，而单元则是较大的存储器阵列中的一部份，以下将会详加描述。这种存储器元件的结构会先行描述，接着会叙述如何制造此器件。
该存储器元件形成在衬底12上，衬底12优选地为电介质填充材料，如二氧化硅。其它合适的材料包括聚酰亚胺(polyimide)、氮化硅、或其它已知的电介质填充材料等替代物。
延伸至外部电路(图中未显示)的栓塞元件14优选地由耐热金属如钨等形成在衬底中。其它耐热金属包括钛(Ti)、钼(Mo)、铝(Al)、钽(Ta)、铜(Cu)、铂(Pt)、铱(Ir)、镧(La)、镍(Ni)、以及钌(Ru)。此栓塞元件可用作电极，在此被称为下电极元件。
自栓塞元件向上延伸则是相变元件20以及上电极元件28。其上则是位线30，其会与外部电路(图中未显示)接触。
此相变元件20可以是以硫属化物为基础的材料以及其它材料。硫属化物包括下列形成元素周期表上第VI族的部分的四种元素之中任意一种：氧(O)、硫(S)、硒(Se)、以及碲(Te)。硫属化物是将硫属元素与更为正电性的元素或自由基结合而得到。硫属化合物合金是将硫属化合物与其它物质例如过渡金属等结合。硫属化合物合金通常包括一个以上的选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫属化合物合金包括下列元素中一个以上的复合物：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变为基础的存储器材料已经在技术文件中进行了描述，包括下列合金：镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金族中，可以尝试大范围的合金成分。此成分可以下列特征式表示：TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为：在沉积材料中所包含的平均碲浓度远低于70％，典型地低于60％，并且在一般型态合金中的碲含量范围从最低23％至最高58％，且最佳地是介于48％至58％的碲含量。锗的浓度高于约5％，且其在材料中的平均范围从最低8％至最高30％，一般为低于50％。最佳地，锗的浓度范围介于8％至40％。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比，其为所有组成元素相加总和为100％。(Ovshinky‘112专利，栏10～11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada，“Potentialof Ge-Sb-Te Phase-change Optical Disks for High-Data-Rate Recording”，SPIE v.3109，pp.28-37(1997))更一般地，过渡金属例如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成相变合金，其具有可编程电阻属性。可使用的存储器材料的特殊示例如Ovshinsky‘112专利中栏11-13所述，在此引入该示例作为参考。
在存储单元的活性通道区域中，相变合金能按照其位置顺序，在第一结构态与第二结构态之间进行切换，其中第一结构态一般为非晶固态，第二结构态一般为结晶固态。这些材料至少为双稳态。术语“非晶”用于指示相对较无次序的结构，其与单晶相比更加无次序性，而具有可检测的特征，例如与结晶态相比具有更高的电阻值。术语“结晶态”用于指示相对较有次序的结构，其与非晶态相比更有次序，因此包括可检测的特征，例如比非晶态更低的电阻值。典型地，相变材料可以在完全结晶态与完全非晶态之间的所有可检测的不同状态之间进行电切换。其它受到非晶态与结晶态之间的改变的影响的材料特征包括：原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态，或者可切换成为由两种以上固态所形成的混合物，提供从非晶态至结晶态之间的灰度级部分。此材料中的电属性也可能随之改变。
相变合金可通过施加电脉冲而从一种相态切换至另一种相态。先前观察指出，较短、较大幅度的脉冲倾向于将相变材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量足够大，因此足以破坏结晶结构的键，同时其足够短，因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下，可以确定特别适用于特定相变合金的适当的脉冲量变曲线。在本文的后续部分，此相变材料称为GST，同时应该理解的是，也可以使用其它类型的相变材料。在本文中所描述的一种适用于PCRAM中的材料为Ge2Sb2Te5。
可用于本发明其它实施例中的其它可编程存储器材料包括：掺杂N2的GST、GexSby、掺杂银的SbxTey、或其它以不同结晶态转换来决定电阻的物质；PrxCayMnO3、PrSrMnO3、ZrOx、AlOx、TiOx、NiOx、ZnOx、以铬掺杂的SrZrO3、以铌掺杂的SrZrO3、或其它使用电脉冲来改变电阻状态的物质；TCNQ、PCBM、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何包括采用电脉冲进行控制的双稳定或多稳定电阻态的其它聚合物材料。
以上电极元件有限地由氮化钛或类似材料所构成，例如选自下列群组中的一个个以上元素：硅、钛、铝、钽、氮、氧与碳。需要注意的是，在附图中由下往上的方向称为“垂直”，而侧向方向则称为“横向”或“水平”，是仅做为参考目的。这种表示方式无论是在制造或使用上，对于器件的实际物理设置方向并无影响。位线30优选地由铝或是其它本领域技术人员所熟知的适合作为金属化材料的导电材料所构成。
此相变元件20的尺寸如下所述，其厚度(即平行于页面长轴方向)介于约30nm至约100nm之间，优选地为70nm。上电极元件28厚度介于约30nm至约120nm之间，优选地为100nm。上电极元件28宽度(即平行于页面短轴方向)介于约20nm至约100nm之间，优选地为50nm。而真空夹层厚度介于约5nm至约50nm之间，优选地为10nm。如此，相变元件的整体宽度介于约30nm至约100nm之间，优选地为70nm。
电极元件与相变元件由上绝缘层26所环绕，该上绝缘层优选地由与衬底12相同或类似的材料所构成。在两个绝缘层之间则是阻挡层18，其由氮化硅或类似的材料所构成。
该上绝缘层与位线和阻挡层接触，但是并没有与相变元件和上电极元件接触。而是与这些元件彼此分离，因此位线与阻挡层的一部份，加上分离的上绝缘层与相变元件和上电极元件共同定义了环绕于相变元件与上电极元件之间的真空夹层24。该真空夹层由位线所封闭，以下将会详细描述。因为真空夹层是在真空环境中进行封闭的，所以在其内部保持真空。
操作本发明的存储器单元时，电流在存储器元件中自栓塞14经过相变元件20，然后向上电极28至位线30流出。当然，本领域技术人员都知道，电流的方向可通过改变元件的几何形状而改变。在任何情况下，相变材料会因电流的经过而加热，如先前所描述的，这会导致该相变材料中央部份22的温度上升。当温度超过相变的临界值后，一部分的相变材料会改变状态。而相变材料的温度改变并不是均匀的，电流密度的改变会造成显著的变化。相变材料的温度会决定其所产生的效果，所以必须小心地选择通过相变材料的电流，以使其能达到所预期的功效—非晶或是结晶状态。假如是想要读取此元件的状态，使用低电流作为感测用途。该读取操作是非破坏性的，因为元件的温度被保持在相变临界之下。
真空夹层24作用为在相变与上电极元件之间保持热量，这可以提供许多优点。首先，通过防止热量从相变与上电极元件流逝，此种设计可以减少相变所需的电流，即降低设置(SET)状态或是重置(RESET)状态所需的电流。在此同时，将热量维持在相变元件与上电极元件之间也可以减少传导到存储器阵列其余部分的热量，这也可以直接增加此器件的寿命。因为完整的集成电路器件内具有相当多的存储器元件，例如，在一千兆字节(GB)的存储器器件中有至少八十亿个元件，因此可以了解到这种热量减少的好处是十分重要的。因此，本发明的设计可以减少存储器器件的电流消耗。
图2a到图2c显示了本发明的相变存储器元件一些可替代实施例的示意图。这些实施例基本上均依据本发明的特征所形成，然而其特定结构各自之间稍有不同。例如，在图2a中所显示的上电极元件28具有超越相变元件20以及真空夹层24的宽度，以封闭该真空夹层。此外，此实施例完全不需要任何阻挡层。在图2b中所显示的上电极元件28的宽度及作用皆与第2a图相同，但是其中包含阻挡层18。在图2c中的实施例基本上类似于图2b，除了上电极元件28是T型的之外，其直立部分裸露出真空夹层，其横杆部分超越真空夹层而将其封闭。本领域技术人员都知道这些实施例仅是一些示例，显示出了本发明的一些可能的变化。
参照图3a-3k而详细说明制造本发明的存储器器件的制造过程实施例。本领域技术人员应该可以了解，存储器阵列通常由一组存储器单元所构成，其结构如图中所示。此制造过程充图3a所示的已有基本结构开始，图3a描述了可作为多个存储器单元基础的结构。栓塞元件14a和14b延伸通过衬底12材料，以作为分离的存储器元件。所述元件的材料如先前所述。字线15a和15b在垂直于附图方向上延伸，以本技术领域熟知的方式连接多个存储器元件。字线最好是由多晶硅所形成。公共源极线17在两个存储器元件中间以平行于字线的方向延伸。
图3b显示了两个阶段的沉积步骤，其中在电介质材料上形成相变材料120，其后再沉积电极材料(最好是氮化钛)128。这些元件的材料如先前所述，在此不再赘述。在后续两个附图图3c和图3d显示，此结构在所预定的地点先沉积并对其进行光刻以形成光阻图案50a和50b。然后进行蚀刻步骤，其结果如图3d所示，其中定义出了两个相变存储器元件10a和10b。如图中所示，形成了两个相变元件20a和20b连同上电极元件28a和28b，最好是利用反应性离子蚀刻(RIE)，搭配氯系等离子化学成分。可以使用光学发射工具(opticalemission tool)来监测及控制蚀刻反应时间，直到遇到其下的衬底层次为止。
此处需注意的是，传统的光刻工艺并无法达成所需的较小尺寸，相变元件和上电极元件所需的尺寸小于传统的光刻工艺所能达到的最小特征尺寸。因此，图3c所生成最小可能尺寸的光阻图案，必须再经过如图3e所示的修剪(trimming)步骤以使光阻图案50a和50b达到所需的尺寸。关于达到所需效果的制造过程，请参见美国专利申请No.11/338,285“Self-Aligned Manufacturing Method，andManufacturing Method For Thin Film Fuse Phase Change RAM”，申请日为2006年1月24日。此相变存储器元件10a和10b可以在光阻图案被缩减的情况下进一步被蚀刻，然后再移除光阻图案，如图3f所示。
在蚀刻之后，如先前所描述地沉积包含氮化硅的阻挡层18。该沉积阻挡层的步骤最好是利用等离子增强化学气相沉积法(PECVD)，在衬底与相变存储器元件上产生共形(conformal)层，如图3g所示。之后，沉积包含与衬底相同或类似材质的上绝缘层26，如图3h所示。该沉积上绝缘层的步骤必须完全覆盖阻挡层与相变存储器元件，如图3h所示。之后，对该上绝缘层进行平坦化，最好是利用化学机械研磨(CMP)实现，以裸露上电极元件28a和28b，如图3i所示。
真空夹层则通过以下两个步骤形成。第一，将在相变元件和上电极元件旁边的阻挡层18蚀刻去掉，如图3j所示。采用湿式蚀刻来选择性地除去阻挡层材料。最好是利用磷酸来蚀刻去掉氮化硅。需要精确地控制此蚀刻工艺以避免伤害相变元件、上电极元件或是电介质材料。
蚀刻步骤之后，金属化步骤将位线30沉积在整个图3j的结构之上，如图3k所示。此沉积必须足以封闭先前蚀刻步骤所产生的空洞，以形成真空夹层24a和24b。此步骤最好是利用溅镀，可以使金属位线(最好是铝)延伸且封闭此单元。此制造过程参数必须细心地选择，要使此沉积并不会完全填满孔洞，本领域技术人员都应该明白。位线30连接存储器元件10a和10b，同时向两侧延伸连接其它存储器元件，如本领域所熟知的。此步骤必须在真空的环境下进行以确保可以在真空夹层中维持真空状态。
虽然已经参考优选实施例对本发明进行了描述，但是应该理解的是，本发明并非限制于所述内容。先前描述中已经建议了可替换方案及修改方式，并且其它可替换方案及修改方式是本领域技术人员能够想到的。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件组合从而实现与本发明实质上相同的结果的技术都不脱离本发明的精神范畴。因此，所有这些可替换方案及修改方式都会落在本发明的附带的权利要求以及等价物所界定的范围中。在前文中所提及的专利申请以及公开出版物都是作为本发明的参考。

Claims (16)

1.一种存储器器件，包含：
第一电极元件；
相变元件，其与所述第一电极元件接触；
上电极元件，其与所述相变元件接触；
位线电极，其与所述上电极元件接触；以及
电介质填充层，环绕于所述相变元件与所述上电极元件且与两者分离，其中环绕于所述相变元件与所述上电极元件的一真空夹层(jacket)由所述位线电极所封闭及定义。
2.如权利要求1所述的存储器器件，其中，所述相变元件包含锗(Ge)、锑(Sb)、碲(Te)的组合。
3.如权利要求1所述的存储器器件，其中，所述相变元件包括由下列群组中的至少两种材料的组合：锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)及金(Au)。
4.如权利要求1所述的存储器器件，其中，所述相变元件宽度为70纳米，厚度为70纳米。
5.如权利要求1所述的存储器器件，其中，所述真空夹层厚度为10纳米。
6.一种存储器器件，包含：
第一电极元件；
相变元件，其与所述第一电极元件接触；
上电极元件，其与所述相变元件接触；以及
电介质填充层，其环绕于所述相变元件与所述上电极元件且与所述相变元件分离，且环绕于所述相变元件的一真空夹层由所述上电极元件所封闭及定义。
7.如权利要求6所述的存储器器件，其中，所述相变元件包含锗(Ge)、锑(Sb)、碲(Te)的组合。
8.如权利要求6所述的存储器器件，其中，所述相变元件包括由下列群组中的至少两种材料的组合：锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)及金(Au)。
9.如权利要求6所述的存储器器件，其中，所述相变元件宽度为70纳米，厚度为70纳米。
10.如权利要求6所述的存储器器件，其中，所述真空夹层厚度为10纳米。
11.如权利要求6所述的存储器器件，其中，所述上电极元件为T型，具有一直柱位于所述真空夹层中，及一横杆部分封闭所述真空夹层。
12.一种存储器器件的制造方法，包含下列步骤：
在第一电极元件上形成相变元件与上电极元件；
在所述相变元件与上电极元件上沉积垫层(liner layer)；
形成电介质填充层以环绕所述相变元件与所述上电极元件，所述电介质填充层的上表面被调整成为使得环绕于所述相变元件与所述上电极元件之间的所述垫层裸露出来；
选择性地蚀刻所述垫层以在所述相变元件和所述上电极元件与所述电介质填充层之间开启孔洞；以及
沉积位线以封闭所述孔洞，且与所述上电极元件电性接触，以定义环绕于所述相变元件与所述上电极元件的一真空夹层。
13.如权利要求12所述的方法，其中，所述相变元件包含锗(Ge)、锑(Sb)、碲(Te)的组合。
14.如权利要求12所述的方法，其中，所述相变元件包括由下列群组中的至少两种材料的组合：锗(Ge)、锑(Sb)、碲(Te)、硒(Se)、铟(In)、钛(Ti)、镓(Ga)、铋(Bi)、锡(Sn)、铜(Cu)、钯(Pd)、铅(Pb)、银(Ag)、硫(S)及金(Au)。
15.如权利要求12所述的方法，其中，所述相变元件宽度为70纳米，厚度为70纳米。
16.如权利要求12所述的方法，其中，所述真空夹层厚度为10纳米。
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