CN100468644C - 划线期间的保护层 - Google Patents

划线期间的保护层 Download PDF

Info

Publication number
CN100468644C
CN100468644C CNB2004800271794A CN200480027179A CN100468644C CN 100468644 C CN100468644 C CN 100468644C CN B2004800271794 A CNB2004800271794 A CN B2004800271794A CN 200480027179 A CN200480027179 A CN 200480027179A CN 100468644 C CN100468644 C CN 100468644C
Authority
CN
China
Prior art keywords
coating
substrate
contact
exposures
line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2004800271794A
Other languages
English (en)
Other versions
CN1856866A (zh
Inventor
S·沙兰
T·德邦尼斯
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of CN1856866A publication Critical patent/CN1856866A/zh
Application granted granted Critical
Publication of CN100468644C publication Critical patent/CN100468644C/zh
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0017Etching of the substrate by chemical or physical means
    • H05K3/0026Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0029Etching of the substrate by chemical or physical means by laser ablation of inorganic insulating material
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/304Mechanical treatment, e.g. grinding, polishing, cutting
    • H01L21/3043Making grooves, e.g. cutting
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10613Details of electrical connections of non-printed components, e.g. special leads
    • H05K2201/10954Other details of electrical connections
    • H05K2201/10977Encapsulated connections
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/07Treatments involving liquids, e.g. plating, rinsing
    • H05K2203/0756Uses of liquids, e.g. rinsing, coating, dissolving
    • H05K2203/0769Dissolving insulating materials, e.g. coatings, not used for developing resist after exposure
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/13Moulding and encapsulation; Deposition techniques; Protective layers
    • H05K2203/1377Protective layers
    • H05K2203/1383Temporary protective insulating layer
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/0011Working of insulating substrates or insulating layers
    • H05K3/0044Mechanical working of the substrate, e.g. drilling or punching
    • H05K3/0052Depaneling, i.e. dividing a panel into circuit boards; Working of the edges of circuit boards

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Optics & Photonics (AREA)
  • Dicing (AREA)

Abstract

一种方法包括在电路基片表面上的多个暴露接触件上形成化学可溶涂层;沿着划线区将基片表面划线;以及在划线后,去除所述涂层的一部分。一种方法包括形成表面上包括多个暴露接触件的电路结构,所述暴露接触件的位置由多个划线道限定;形成包括暴露接触件上的化学可溶材料的涂层;沿着划线道对基片表面划线;以及在划线后去除该涂层。一种方法包括用化学可溶材料涂布包括多个暴露接触件的电路基片表面;沿着划线区将基片表面划线;去除涂层以及将划线区中的基片锯开。

Description

划线期间的保护层
技术领域
本发明涉及电路制造技术,尤其涉及划线工艺。
背景技术
划线工艺用于在将基片锯成个别芯片或管芯前将电路基片(例如,晶片)划线。根据当前的技术,划线工艺常将紫外线激光器(通常钇铝石榴石(YAG)激光器)用于在锯开操作前划线基片。通过在锯开前划线基片,锯开或切割通过划线区以划分或单个化该基片的锯开过程通常可以这样做而不破坏基片上的膜(通常是电介质膜)。在划线过程期间,通过侵蚀基片(例如硅基片)的任何金属层或电介质层(例如,低介电常数电介质层)在指定区域或道中形成划线。激光划线工艺通常产生侵蚀材料(多数是具有一些碳的硅),作为碎屑。该碎屑易于落在基片表面上。基片表面通常具有许多暴露的接触件(例如,凸起接触件)。因此,碎屑易于落在接触件上并会粘附到接触件表面上。接触件表面的这种污染在封装期间阻碍了接触件结合后续的接触件,导致被称作非湿缺陷的特性。
发明内容
本发明旨在解决上述问题。
根据本发明的一种方法,包括:在电路基片表面上的多个暴露的接触件上形成化学可溶涂层,其厚度大于所述多个接触件的其中一部分的表面突出距离;沿着划线区将基片表面划线;以及在划线后,用溶化工序去除所述涂层的一部分以暴露出多个接触件。
根据本发明的一种方法,包括:形成电路结构,它包括一表面上的多个暴露的接触件,所暴露的接触件的位置由多个划线道定义;在所暴露的接触件上形成包含化学可溶材料的涂层,其厚度大于所述多个接触件的其中一部分的表面突出距离;沿着所述划线道将所述基片的表面划线;以及在划线后,用溶化工序去除所述涂层以暴露出多个接触件。
根据本发明的一种方法,包括:用化学可溶材料涂布包含多个暴露的接触件的电路基片的表面;沿着划线区将基片表面划线;用溶化工序去除所述涂层以暴露出多个接触件;以及将划线区中的基片锯开,其中锯开和去除是同时进行的。
附图说明
通过以下的详细描述、所附权利要求以及附图,实施例的各特点、方面和优点将变得显而易见,其中:
图1示出了具有通过划线道在其上形成的多个分离电路结构的一部分晶片的顶部侧视图。
图2示出了通过线A-A’的图1结构的截面侧部分。
图3A示出了根据一个实施例在引入结构表面上的化学可溶涂层后图2的结构。
图3B示出了根据另一实施例在引入结构表面上的化学可溶涂层后图2的结构。
图4示出了图3A的结构和划线过程。
图5示出了湿法锯开过程期间图4A的结构。
图6示出了湿法锯开过程后图5的结构。
图7示出了与封装连接的管芯或芯片的侧视图。
具体实施方式
图1是其中和其上形成了许多分离的电路结构的诸如晶片的基片的一部分的示意性顶部侧视图。图2是通过线A-A’的图1结构的截面侧视图。参考图1和图2,结构100例如包括诸如硅的半导体材料或诸如玻璃的绝缘体上的半导体层的基片105。结构100是晶片级的一部分结构,它具有在这点上小心地连接和表示的许多电路结构(管芯或芯片)。每个电路结构(例如,管芯或芯片110A,...110I)在基片105上通过划线道120分开,它们被用作单个化区域以使电路结构与基片分离成分离的管芯或芯片。图1示出了管芯或芯片110A、110B、110C、110D、110E、110F、110G、110H和110I(参见图1)。每个电路结构(例如,管芯或芯片110A、...110I)可具有基片105中和其上形成的许多电路装置以及基片105上形成并与各管芯或芯片上的装置连接的一个或多个互连层。每个电路结构的顶表面可具有许多触点,在该实施例中包括焊料或类似的导电材料凸起,以便发送或接收管芯或芯片外部的信号。凸起115从各管芯或芯片的表面突出,且如图2所示暴露于各管芯或芯片的表面上。如图2所示,每个凸起都从基片表面突出约75微米的高度T1。每个凸起115可由电介质材料包围,这些电介质材料另外覆盖基片100的表面。
图3A示出了在结构100表面上引入化学可溶涂层后图2的结构。在一个实施例中,将化学可溶涂层130沉积到大于从基片表面起的凸起115的突出高度T1的厚度T2。按此方式,化学可溶涂层130覆盖于凸起115上(如图所示)。在另一实施例中,如图3B所示,化学可溶涂层130被沉积为与结构100的表面和在上面的凸起115相符的相对保形涂层。化学可溶涂层130的典型厚度约5到35微米(μm),且在该实施例中足够厚以覆盖在凸起115上但不厚到随后在合理时间内不能去除该化学可溶涂层130。如图所示,化学可溶涂层130覆盖在结构110的每个电路结构以及划线道120上。
在一个实施例中,化学可溶涂层130的材料是随后可以从基片表面上去除的材料。在将紫外线激光器划线工艺用于划线结构100的情况下,用于化学可溶涂层130的材料还应对紫外光透明,以使它不阻碍后续划线过程(例如,YAG激光器划线过程)。最后,在一个实施例中,用于化学可溶涂层130的材料是环境上无毒或无害的,因此在去除期间不需要采取附加的注意手段。用于化学可溶涂层130的合适材料包括有机涂层,包括亲水涂层,诸如甲基纤维素、聚乙烯醇和流脂(resinflux)。这些材料是对紫外光透明的,可以用水去除,并且是环境上无毒无害的。在一个实施例中,诸如甲基纤维素、聚乙烯乙醇或树脂流的材料的化学可溶涂层130可通过各种涂布技术施涂于基片表面,这些技术包括,但不限于,旋涂、静电喷射或其它技术。
图4示出了图3A的结构并示出了划线道120中的划线过程。在一个实施例中,采用激光划线工艺,其中使用YAG激光器对基片105划线。划线过程易于生成碎屑,多数是硅和碳,且在侵蚀基片时,它们落在化学可溶涂层130上。
图5示出了图4的结构并示出了锯开过程。在一个实施例中,锯开过程采用锯140和水145(湿法锯开过程)。锯140切割通过基片105以使电路结构(例如,管芯或芯片110A、...110I)单个化。在化学可溶涂层是水可溶的情况下,在一个实施例中,锯开过程内所使用的水也可用于去除化学可溶涂层130的材料。或者,可在锯开过程之前或之后通过用水或其它溶剂进行清洗来去除化学可溶涂层130。
图6示出了在个别电路结构的单个化之后图5的结构。图6所示的是管芯或芯片110A、管芯或芯片110B和管芯或芯片110C。图6还示出去除化学可溶涂层130之后的每个电路结构。按此方式,暴露接触件(凸起)115。通过化学可溶涂层130的去除来去除划线过程期间产生的任何碎屑。
图7示出了封装150上安装的管芯或芯片110A。在该实施例中,安装方法包括使管芯或芯片110A的凸起115与封装150的相应触点或凸起155相接触。一旦形成触点之间的接触,回流过程可用于将管芯或芯片110A结合到封装150。通过在划线过程期间使用划线可溶涂层130,使得侵蚀材料落在触点或凸起115上的本领最小化。因此,使得例如在将管芯或芯片连接到封装时出现缺陷的可能性最小化。(例如,最小化非湿数)。
在以上段落中,描述了特定的实施例。但显然,可以对其进行各种修改和改变而不背离权利要求书的较宽精神和范围。因此,说明书和附图被认为是说明性而非限制性的。

Claims (16)

1.一种方法,包括:
在电路基片表面上的多个暴露的接触件上形成化学可溶涂层,其厚度大于所述多个暴露的接触件的其中一部分的表面突出距离;
沿着划线区将基片表面划线;以及
在划线后,用溶化工序去除所述涂层的至少一部分以暴露出多个接触件。
2.如权利要求1所述的方法,其特征在于,所述多个暴露的接触件的所述一部分中的每一个都包括表面上的突出凸起。
3.如权利要求2所述的方法,其特征在于,所述涂层的厚度为5到35微米。
4.如权利要求2所述的方法,其特征在于,还包括沿着所述划线区锯开所述基片。
5.如权利要求4所述的方法,其特征在于,锯开和去除一部分涂层被同时进行。
6.如权利要求1所述的方法,其特征在于,去除所述涂层的至少一部分包括去除整个所述涂层。
7.如权利要求1所述的方法,其特征在于,化学可溶涂层的材料选自甲基纤维素、聚乙烯醇和流脂。
8.如权利要求1所述的方法,其特征在于,所述涂层是有机涂层。
9.如权利要求1所述的方法,其特征在于,还包括,在划线后,移除涂层之前,用锯沿着划线区域完全锯穿基片。
10.一种方法,包括:
形成电路结构,它包括一电路基片表面上的多个暴露的接触件,所暴露的接触件的位置由多个划线道定义;
在所暴露的接触件上形成包含化学可溶材料的涂层,其厚度大于所述多个暴露的接触件的其中一部分的表面突出距离;
沿着所述划线道将所述基片的表面划线;以及
在划线后,用溶化工序去除所述涂层以暴露出多个接触件。
11.如权利要求10所述的方法,其特征在于,还包括,在划线后,沿着所述划线道锯开所述基片。
12.如权利要求11所述的方法,其特征在于,锯开和去除所述涂层同时进行。
13.如权利要求11所述的方法,其特征在于,去除所述涂层包括去除整个涂层。
14.如权利要求11所述的方法,其特征在于,涂层的材料选自甲基纤维素、聚乙烯醇和流脂。
15.一种方法,包括:
用化学可溶材料涂布包含多个暴露的接触件的电路基片的表面以形成涂层;
沿着划线区将基片表面划线;
用溶化工序去除所述涂层以暴露出多个接触件;以及
将划线区中的基片锯开,其中锯开和去除是同时进行的。
16.如权利要求15所述的方法,其特征在于,涂布材料选自甲基纤维素、聚乙烯醇和流脂。
CNB2004800271794A 2003-09-30 2004-09-29 划线期间的保护层 Expired - Fee Related CN100468644C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US10/676,303 2003-09-30
US10/676,303 US7265032B2 (en) 2003-09-30 2003-09-30 Protective layer during scribing

Publications (2)

Publication Number Publication Date
CN1856866A CN1856866A (zh) 2006-11-01
CN100468644C true CN100468644C (zh) 2009-03-11

Family

ID=34377352

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800271794A Expired - Fee Related CN100468644C (zh) 2003-09-30 2004-09-29 划线期间的保护层

Country Status (6)

Country Link
US (1) US7265032B2 (zh)
KR (1) KR100847933B1 (zh)
CN (1) CN100468644C (zh)
DE (1) DE112004001787T5 (zh)
TW (1) TWI277374B (zh)
WO (1) WO2005034214A2 (zh)

Families Citing this family (22)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6974726B2 (en) * 2003-12-30 2005-12-13 Intel Corporation Silicon wafer with soluble protective coating
US7135385B1 (en) 2004-04-23 2006-11-14 National Semiconductor Corporation Semiconductor devices having a back surface protective coating
US6972244B1 (en) * 2004-04-23 2005-12-06 National Semiconductor Corporation Marking semiconductor devices through a mount tape
US7015064B1 (en) 2004-04-23 2006-03-21 National Semiconductor Corporation Marking wafers using pigmentation in a mounting tape
US7101620B1 (en) 2004-09-07 2006-09-05 National Semiconductor Corporation Thermal release wafer mount tape with B-stage adhesive
US20060289966A1 (en) * 2005-06-22 2006-12-28 Dani Ashay A Silicon wafer with non-soluble protective coating
KR100841359B1 (ko) 2005-10-19 2008-06-26 삼성에스디아이 주식회사 유기전계발광표시장치의 제조방법
US7682937B2 (en) * 2005-11-25 2010-03-23 Advanced Laser Separation International B.V. Method of treating a substrate, method of processing a substrate using a laser beam, and arrangement
US8030138B1 (en) 2006-07-10 2011-10-04 National Semiconductor Corporation Methods and systems of packaging integrated circuits
KR101262386B1 (ko) * 2006-09-25 2013-05-08 엘지이노텍 주식회사 질화물 반도체 발광소자의 제조 방법
JP4933233B2 (ja) * 2006-11-30 2012-05-16 株式会社ディスコ ウエーハの加工方法
US8236592B2 (en) * 2007-01-12 2012-08-07 Globalfoundries Inc. Method of forming semiconductor device
US7858493B2 (en) * 2007-02-23 2010-12-28 Finisar Corporation Cleaving edge-emitting lasers from a wafer cell
US7749809B2 (en) * 2007-12-17 2010-07-06 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US8048781B2 (en) * 2008-01-24 2011-11-01 National Semiconductor Corporation Methods and systems for packaging integrated circuits
US20100015329A1 (en) * 2008-07-16 2010-01-21 National Semiconductor Corporation Methods and systems for packaging integrated circuits with thin metal contacts
US8609512B2 (en) * 2009-03-27 2013-12-17 Electro Scientific Industries, Inc. Method for laser singulation of chip scale packages on glass substrates
US8524537B2 (en) * 2010-04-30 2013-09-03 Stats Chippac, Ltd. Semiconductor device and method of forming protective coating material over semiconductor wafer to reduce lamination tape residue
JP5589576B2 (ja) * 2010-06-10 2014-09-17 富士通セミコンダクター株式会社 半導体装置の製造方法及び半導体基板
US9082633B2 (en) * 2011-10-13 2015-07-14 Xilinx, Inc. Multi-die integrated circuit structure with heat sink
US20150037915A1 (en) * 2013-07-31 2015-02-05 Wei-Sheng Lei Method and system for laser focus plane determination in a laser scribing process
US9917011B2 (en) * 2014-05-19 2018-03-13 Sharp Kabushiki Kaisha Semiconductor wafer, semiconductor device diced from semiconductor wafer, and method for manufacturing semiconductor device

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3615951A (en) * 1969-06-20 1971-10-26 Ibm Method for etching copper
US4842662A (en) * 1988-06-01 1989-06-27 Hewlett-Packard Company Process for bonding integrated circuit components
JP2644069B2 (ja) 1990-07-09 1997-08-25 九州日本電気株式会社 半導体装置の製造方法
JPH05211381A (ja) 1991-11-12 1993-08-20 Nec Corp 混成集積回路の製造方法
US5286343A (en) 1992-07-24 1994-02-15 Regents Of The University Of California Method for protecting chip corners in wet chemical etching of wafers
US5543365A (en) 1994-12-02 1996-08-06 Texas Instruments Incorporated Wafer scribe technique using laser by forming polysilicon
US5597767A (en) * 1995-01-06 1997-01-28 Texas Instruments Incorporated Separation of wafer into die with wafer-level processing
US5641416A (en) 1995-10-25 1997-06-24 Micron Display Technology, Inc. Method for particulate-free energy beam cutting of a wafer of die assemblies
JPH1027971A (ja) 1996-07-10 1998-01-27 Nec Corp 有機薄膜多層配線基板の切断方法
US6465329B1 (en) * 1999-01-20 2002-10-15 Amkor Technology, Inc. Microcircuit die-sawing protector and method
US6420245B1 (en) * 1999-06-08 2002-07-16 Kulicke & Soffa Investments, Inc. Method for singulating semiconductor wafers
JP3610887B2 (ja) * 2000-07-03 2005-01-19 富士通株式会社 ウエハレベル半導体装置の製造方法及び半導体装置
JP2002055219A (ja) 2000-08-10 2002-02-20 Toray Ind Inc カラーフィルター基板の製造方法
US6506681B2 (en) * 2000-12-06 2003-01-14 Micron Technology, Inc. Thin flip—chip method
JP4856328B2 (ja) * 2001-07-13 2012-01-18 ローム株式会社 半導体装置の製造方法
SG139508A1 (en) * 2001-09-10 2008-02-29 Micron Technology Inc Wafer dicing device and method
US6838299B2 (en) * 2001-11-28 2005-01-04 Intel Corporation Forming defect prevention trenches in dicing streets
US6746890B2 (en) * 2002-07-17 2004-06-08 Tini Alloy Company Three dimensional thin film devices and methods of fabrication
US6919420B2 (en) * 2002-12-05 2005-07-19 International Business Machines Corporation Acid-cleavable acetal and ketal based epoxy oligomers
JP2004188475A (ja) 2002-12-13 2004-07-08 Disco Abrasive Syst Ltd レーザー加工方法
KR100486290B1 (ko) * 2002-12-23 2005-04-29 삼성전자주식회사 반도체 패키지 조립방법 및 반도체 패키지 공정의보호테이프 제거장치

Also Published As

Publication number Publication date
WO2005034214A3 (en) 2005-06-16
US7265032B2 (en) 2007-09-04
US20050070095A1 (en) 2005-03-31
KR100847933B1 (ko) 2008-07-22
KR20060055554A (ko) 2006-05-23
DE112004001787T5 (de) 2006-09-07
WO2005034214A2 (en) 2005-04-14
TWI277374B (en) 2007-03-21
CN1856866A (zh) 2006-11-01
TW200514483A (en) 2005-04-16

Similar Documents

Publication Publication Date Title
CN100468644C (zh) 划线期间的保护层
TWI552215B (zh) 使用可物理性移除的遮罩之雷射及電漿蝕刻晶圓切割
US20080048299A1 (en) Electronic Component with Semiconductor Chips, Electronic Assembly Composed of Stacked Semiconductor Chips, and Methods for Producing an Electronic Component and an Electronic Assembly
CN105514038A (zh) 切割半导体晶片的方法
JP2004363478A (ja) 半導体装置の製造方法
EP0453787B1 (en) Semiconductor device having an insulating film
JP2006108664A (ja) 段差被覆性を向上させた半導体ウェハー及びその製造方法
TWI246446B (en) Methods and apparatus for laser dicing
US20070057349A1 (en) Wafer having scribe lanes suitable for sawing process, reticle used in manufacturing the same, and method of manufacturing the same
CN102792432B (zh) 半导体器件及其制造方法
CN114446876B (zh) 晶圆切割方法
US20040169258A1 (en) Semiconductor wafer having separation groove on insulating film on dicing line region and its manufacturing method
CN101569010B (zh) 具有低介电性绝缘膜的半导体器件及其制造方法
CN105895572A (zh) 晶片封装体及其制造方法
US20200203263A1 (en) Low cost reliable fan-out chip scale packages
CN108290732B (zh) 用于封装至少一个半导体构件的方法和半导体装置
JP2008166414A (ja) 半導体装置及びその製造方法
JP2004363548A (ja) 集積回路ダイ製作方法
US20070013034A1 (en) Semiconductor device and method for manufacturing the same
CN111627857A (zh) 封装方法及封装结构
JP2005101181A (ja) 半導体装置のおよびその製造方法
TWI313875B (zh)
KR100575618B1 (ko) 구리막의 연마 방법 및 이를 이용한 구리막 배선의 형성방법
KR100713903B1 (ko) 반도체소자의 가드링 형성방법
KR100285757B1 (ko) 반도체장치및그제조방법

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090311

Termination date: 20130929