CN100468743C - Non-volatile memory and mfg. method - Google Patents
Non-volatile memory and mfg. method Download PDFInfo
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- CN100468743C CN100468743C CNB2005101297459A CN200510129745A CN100468743C CN 100468743 C CN100468743 C CN 100468743C CN B2005101297459 A CNB2005101297459 A CN B2005101297459A CN 200510129745 A CN200510129745 A CN 200510129745A CN 100468743 C CN100468743 C CN 100468743C
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Abstract
The non-volatile memory is composed of substrate, isolation layers, active layers, floating grids, control grids, and doping areas. Being setup on substrate, active layer is positioned between isolation layers. Top surface of active layer is higher than top surface of isolation layer. Being arranged in parallel to isolation layers, active layers are extended to first direction. Being setup on substrate, the parallel floating grids are extended to second direction. The said first direction and the second direction are staggered. Floating grids are setup between each active layer and control grid. Doping areas are setup in active layers between control grids respectively.
Description
Technical field
The present invention relates to a kind of semiconductor element and manufacture method thereof, particularly relate to a kind of non-volatility memorizer and manufacture method thereof.
Background technology
Flash memory in the non-volatility memorizer (Flash) relies on the advantage on its quick timesaving operator scheme and the cost, has become one of main flow of industry research.Typical flash element is made of floating grid (Floating Gate) and control grid (Control Gate), the control grid is set directly on the floating grid, be separated by with dielectric layer between floating grid and the control grid, and be separated by with tunnel oxide (Tunnel Oxide) between floating grid and the substrate.
The flash array that present industry is more often used comprises NOR gate (NOR) type array structure and NAND gate (NAND) type array structure.The flash memory structure of NAND gate (NAND) type array is that each memory cell is serially connected, and its integrated level is better than the flash memory of NOR gate (NOR) type array with area utilization, has been widely used in the multiple electronic product.
Yet, along with the development of integrated circuit technique,, must promote the element integrated level (Integrity) of product inside continuously for electronic product is microminiaturized step by step, this makes that the size of memory cell is more and more littler, and the distance between each memory cell is also shorter and shorter.Thus, to cause the influence of short-channel effect (Short Channel Effect) more remarkable, not only can change opening of memory and make voltage (Vt), make grid voltage (Vg) control the switch generation problem of raceway groove, also can cause thermoelectronic effect and puncture (Punch Through) effect, in passage, produce leakage current, or electricity collapse (ElectricalBreakdown) phenomenon takes place.These situations are all very unfavorable for the stability and the reliability of memory.
In addition, because the size of memory cell is dwindled, make simultaneously that also the area of electric capacity dwindles between control grid and the floating grid, thereby cause controlling the coupling coefficient decline of grid that in the operation store unit, it is just enough to apply bigger voltage.The raising of operating voltage is easy to generate problems such as heat radiation and noise, also can increase power consumption simultaneously.
Summary of the invention
In view of this, an object of the present invention is to provide a kind of non-volatility memorizer, can avoid the influence of short-channel effect, increase the reliability and the stability of memory, and can reduce operating voltage, reduce power consumption.
Another object of the present invention provides a kind of manufacture method of non-volatility memorizer, not only can simplify manufacturing process, can also improve process margin, produces the better memory of usefulness.
The present invention proposes a kind of non-volatility memorizer, comprises substrate, a plurality of separator, a plurality of active layer, a plurality of floating grid, a plurality of control grid and a plurality of doped region at least.A plurality of separators are arranged in the substrate.A plurality of active layers are arranged in the substrate, and between separator, the end face of these active layers is higher than the end face of separator, and active layer and separator arrangement parallel to each other, extend toward first direction.A plurality of control grids are arranged in the substrate, and these control grids are arranged in parallel, and extend toward second direction, and second direction and first direction are staggered.A plurality of floating grids are arranged at respectively between each active layer and the control grid.A plurality of doped regions are arranged in the active layer of controlling between the grid.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned non-volatility memorizer more can be to comprise a plurality of tunneling dielectric layers, is arranged between floating grid and the active layer, is inverted u-shaped and coats the active layer that protrudes in insulation surface.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned non-volatility memorizer also comprises dielectric layer between a plurality of grid, is inverted u-shaped and is arranged between control grid and the floating grid.The material of dielectric layer comprises silicon oxide/silicon nitride/silicon oxide between above-mentioned grid.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned floating grid is inverted u-shaped and is arranged at active layer top and sidewall.Above-mentioned floating grid is arranged at the active layer two side.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned substrate comprises silicon on the insulating barrier (Silicon On Insulator) substrate.
According to the described non-volatility memorizer of embodiments of the invention, above-mentioned non-volatility memorizer is a NAND gate (NAND) type flash memory.
The present invention proposes a kind of manufacture method of non-volatility memorizer, and substrate at first is provided, and forms a plurality of separators afterwards in substrate, defines a plurality of active layers, and active layer and separator are arranged in parallel, and extend toward first direction.Then, form a plurality of grooves in separator, these grooves are arranged along second direction, are come out in the top of active layer, and second direction and first direction are staggered.Form a plurality of floating grids then, be covered in the active layer that comes out on the second direction.The a plurality of control grids of the formation that continues, the control grid covers floating grid and fills up groove, and the control grid is arranged in parallel and extends toward second direction.Next, form a plurality of doped regions in the active layer between the control grid.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, on be set forth in and form between separator and the step that forms floating grid, also be included in formation one deck tunneling dielectric layer in the substrate.On be set forth in and form between floating grid and the step that forms the control grid, also be included in the substrate dielectric layer between formation one deck grid.
Manufacture method according to the described non-volatility memorizer of embodiments of the invention, on be set forth in and form a plurality of grooves in these a plurality of separators on the second direction, the method that is come out in the top of active layer for example is, form a plurality of mask layers prior to insulation surface, these mask layers are arranged in parallel, and extend toward second direction, be mask afterwards with the mask layer, remove the top that separator comes out, and in separator, form groove, come out in the top of part active layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the formation method of above-mentioned floating grid for example is prior to forming first conductor layer in the substrate.Then, on first conductor layer, form one deck sacrifice layer.Afterwards, remove the sacrifice layer on the mask layer, expose first conductor layer on the mask layer.Then, remove first conductor layer that the mask layer both sides are exposed.Then, remove the sacrifice layer on the active layer, expose first conductor layer on the active layer.Afterwards, remove the interior sacrifice layer of groove and part first conductor layer of bottom portion of groove.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, above-mentioned sacrifice layer has different etching selectivities with first conductor layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes part first conductor layer of interior sacrifice layer of groove and bottom portion of groove for example is to form a dielectric layer prior to first conductor layer surface that exposes on the active layer.Then, remove the interior sacrifice layer of groove.Then, be mask with the dielectric layer, remove first conductor layer that exposes.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the manufacture method of above-mentioned non-volatility memorizer also comprises first conductor layer that removes on the active layer end face, makes first conductor layer be separated in the active layer two side.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the method for above-mentioned formation control grid for example is prior to forming one second conductor layer in the substrate, form one deck patterning photoresist layer afterwards in substrate, covering floating grid.Patterning photoresist layer is arranged in parallel, and extends toward second direction.Be mask then, remove part second conductor layer with patterning photoresist layer.And then remove patterning photoresist layer.Wherein, more can be to be etch stop layer with the mask layer, remove part second conductor layer.On be set forth in and remove after part second conductor layer, also comprise removing mask layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, above-mentioned substrate comprises silicon on the insulating barrier (Silicon On Insulator) substrate.
The present invention proposes the manufacture method of another kind of non-volatility memorizer.At first, provide a substrate, form a plurality of separators in substrate, define a plurality of active layers, active layer and separator are arranged in parallel, and extend toward first direction.Then, form a plurality of mask layers in substrate, these mask layers are arranged in parallel, and extend toward second direction, and second direction and first direction are staggered.Afterwards, be mask with the mask layer, remove the top that separator exposes, and in separator, form a plurality of grooves, these grooves are arranged along second direction, are come out in the top of active layer.Then, on active layer, form tunneling dielectric layer.Next, in substrate, form one deck first conductor layer and one deck sacrifice layer in regular turn.
Then, remove the sacrifice layer on the mask layer, expose first conductor layer on the mask layer.Remove first conductor layer that mask layer both sides exposed thereafter.Then, remove the sacrifice layer on the active layer, expose first conductor layer on the active layer, and the surface of first conductor layer that is exposed on active layer forms a dielectric layer.Continue it, remove the sacrifice layer that exposes.Then, be mask with the dielectric layer, remove part first conductor layer of bottom portion of groove.
Next, in forming dielectric layer and one second conductor layer between grid in the substrate in regular turn.Thereafter, patterning second conductor layer makes second conductor layer be strip and covers first conductor layer, and second conductor layer is arranged in parallel, and extends toward second direction.Afterwards, remove mask layer, and form a plurality of doped regions in the active layer between second conductor layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, on be set forth in after the sacrifice layer that removes on the active layer, and form before the dielectric layer, also comprise first conductor layer that removes on the active layer.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes first conductor layer that exposes for example is the etch-back method.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes the sacrifice layer on the active layer for example is to insert photoresist prior to the recess of sacrifice layer, carries out the sacrifice layer that the etch-back method removes active layer then.Remove photoresist afterwards again to finish it.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes the sacrifice layer on the active layer can also be a chemical mechanical milling method.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes the sacrifice layer that exposes for example is a wet etching.The above-mentioned method that removes part first conductor layer of bottom portion of groove comprises the etch-back method.
Manufacture method according to the described non-volatility memorizer of embodiments of the invention, the method of above-mentioned patterning second conductor layer for example is prior to forming one deck patterning photoresist layer in the substrate, cover first conductor layer, patterning photoresist layer is arranged in parallel, and extends toward second direction.Then, be mask with patterning photoresist layer, remove part second conductor layer.Remove patterning photoresist layer then.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes mask layer for example is a wet etching.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the formation method of dielectric layer or dielectric layer for example is a thermal oxidation method between above-mentioned tunneling dielectric layer, grid.
According to the manufacture method of the described non-volatility memorizer of embodiments of the invention, the above-mentioned method that removes the sacrifice layer on the mask layer for example is a chemical mechanical milling method.
Therefore the present invention can avoid the influence of short-channel effect because of adopting fin-shaped active layer and floating grid that envelopes active layer and control grid, increases the reliability and the stability of memory, and can reduce operating voltage, reduces power consumption.
The manufacture method of non-volatility memorizer proposed by the invention not only can be simplified manufacturing process, saves manufacturing cost, can also improve process margin, produces the better memory of usefulness.
For above and other objects of the present invention, feature and advantage can be become apparent, following conjunction with figs. and preferred embodiment are to illustrate in greater detail the present invention.
Description of drawings
Figure 1A to Fig. 1 F illustrates the manufacturing process top view of a kind of non-volatility memorizer of one embodiment of the invention.
Fig. 2 A to Fig. 2 F illustrates among Figure 1A to Fig. 1 F the generalized section along-I ' line respectively.
Fig. 3 E and Fig. 3 F illustrate among Fig. 1 E and Fig. 1 F generalized section along II-II ' line respectively.
Fig. 1 G illustrates the manufacturing process top view of the non-volatility memorizer of another embodiment of the present invention.
Fig. 2 G, Fig. 3 G and Fig. 4 G illustrate among Fig. 1 G the generalized section along I-I ' line, II-II ' line and III-III ' line respectively.
The simple symbol explanation
100: substrate 101: separator
103: active layer 105: mask layer
107: groove 110: tunneling dielectric layer
120,120a, 120b: conductor layer (floating grid)
125: sacrifice layer 127: dielectric layer
130: dielectric layer between grid
140: conductor layer (control grid)
150: doped region
Embodiment
Figure 1A to Fig. 1 F illustrates the manufacturing process stereogram of a kind of non-volatility memorizer of one embodiment of the invention.Fig. 2 A to Fig. 2 F illustrates among Figure 1A to Fig. 1 F the section of structure along I-I ' line respectively.Fig. 3 E and Fig. 3 F illustrate among Fig. 1 E and Fig. 1 F section of structure along II-II ' line respectively.
Please refer to Figure 1A and Fig. 2 A, the manufacture method of a kind of non-volatility memorizer that the present invention proposes can be used for forming NAND gate type flash memory.Substrate 100 at first is provided, forms a plurality of separators 101 in substrate 100, define a plurality of active layers 103 between each separator 101, active layer 103 is arranged in parallel with separator 101, and extends toward directions X.Substrate 100 for example is a silicon base, or silicon (Silicon On Insulator) on the insulating barrier.The formation method of separator 101 for example is prior to forming a plurality of grooves (not illustrating) in the substrate 100, inserting suitable dielectric material again to form in groove.
Then, please refer to Figure 1B and Fig. 2 B, form a plurality of mask layers 105 in substrate 100, these mask layers 105 are arranged in parallel, and extend toward the Y direction.The formation method of mask layer 105 for example is prior to forming one deck layer of mask material (not illustrating) in the substrate 100, form one deck patterning photoresist layer (not illustrating) afterwards, then be mask with this patterning photoresist layer, remove the part layer of mask material to form it.The material of mask layer 105 (layer of mask material) for example is a silicon nitride, or other has the suitable material of different etching selectivities with separator 101, and its formation method for example is a chemical vapour deposition technique.The method that removes the part layer of mask material for example is an anisotropic etch process.
Then, remove the separator 101 of part, form a plurality of grooves 107 in separator 101, these grooves 107 are arranged along the Y direction, and expose the top of active layer 103 on the Y direction.The formation method of groove 107 for example be select can etch isolates layer 101 but can etching active layer 103 reacting gas, be etching mask with mask layer 105, utilize anisotropic etch process to form it.
Afterwards, please refer to Fig. 1 C and Fig. 2 C, in substrate 100, form tunneling dielectric layer 110, conductor layer 120 and sacrifice layer 125 in regular turn.The material of tunneling dielectric layer 110 for example is a silica, and its formation method for example is a thermal oxidation method.The material of conductor layer 120 for example is a doped polycrystalline silicon, its formation method for example is after utilizing chemical vapour deposition technique to form one deck undoped polycrystalline silicon layer, carry out the ion implantation step to form it, perhaps also can adopt the mode of injecting alloy when participating in the cintest, form it with chemical vapour deposition technique.The formation of sacrifice layer 125 is in order in follow-up technology conductor layer 120 definition to be become floating grid, and therefore, sacrifice layer 125 should select to have with conductor layer 120 material of different etching selectivities, as silicon nitride.The formation method of sacrifice layer 125 for example is a chemical vapour deposition technique.
Continue it, please refer to Fig. 1 D and Fig. 2 D, remove the partial sacrifice layer 125 on the mask layer 105, to expose conductor layer 120 top surfaces on the mask layer 105.The method that removes sacrifice layer 125 for example is to utilize chemical mechanical milling method to carry out.Then, remove the conductor layer 120 that above-mentioned steps exposes, the method that removes for example is to utilize the etch-back method of dry-etching method or wet etching.Because other structure is all sacrifice layer 125 and covers, above-mentioned etching step is removed the conductor layer 120 between mask layer 105 tops and mask layer 105 sidewalls and the sacrifice layer 125, thus, after etch process carries out, just the conductor layer 120 of a whole layer can be separated into strip, on the Y direction, be arranged in parallel.
Then, remove the sacrifice layer 125 on the active layer 103, up to the end face of the conductor layer 120 that exposes active layer 103 tops.The method that removes sacrifice layer 125 for example is a chemical mechanical milling method, and the sacrifice layer 125 of worn part mask layer 105 of while and both sides thereof, makes the XY plane contour; Or polymer or photoresist (not illustrating) are filled up in the space between sacrifice layer 125 earlier, again with Wet-type etching or dry-etching method etch-back sacrifice layer 125, for example be to have removed the mask layer 105 of part and the sacrifice layer 125 of mask layer 105 both sides in the time of etch-back sacrifice layer 125.Then, on the conductor layer 120 that exposes, form one dielectric layer 127.The material of dielectric layer 127 should select to have with sacrifice layer 125, conductor layer 120 material of different etching selectivities.The formation method of dielectric layer 127 for example is a thermal oxidation method, and exposed portions conductor layer 120 is oxidized to silica.Certainly, dielectric layer 127 also can be other suitable dielectric material, as long as be suitable as the etching mask layer of etch sacrificial layer 125 and conductor layer 120.
Afterwards, please refer to Fig. 1 E, Fig. 2 E and Fig. 3 E, remove the sacrifice layer 125 on the conductor layer 120, the method that removes for example is a wet etching, has for example removed the mask layer 105 of part and the sacrifice layer 125 of mask layer 105 both sides when removing.Then, remove the segment conductor layer 120 of groove 107 bottoms, the method that removes for example is to be mask with dielectric layer 127, utilizes the etch-back method to finish it.In such event, the conductor layer 120 of strip just can be cut and come, and makes that the conductor layer 120 that is positioned on adjacent two active layers 103 is separated from one another, and forms the floating grid (conductor layer 120) of inverted u-shaped, covers the top of the active layer 103 that comes out on the Y direction.
Continue it, in dielectric layer 130 and another layer conductor layer 140 between one deck grid in regular turn in the substrate 100.The material of dielectric layer 130 for example is a silicon oxide/silicon nitride/silicon oxide between grid, and its formation method for example is to utilize chemical vapour deposition technique, forms silicon oxide layer, silicon nitride layer and silicon oxide layer in regular turn with different reacting gass.Certainly, dielectric layer 130 also can be selected suitable dielectric materials such as silica, silicon nitride or silica/silicon nitride for use between grid.The material of conductor layer 140 for example is conductor materials such as doped polycrystalline silicon, metal or metal silicide, and its formation method for example is with chemical vapour deposition technique or physical vaporous deposition is to form according to the difference of material.
Then, please refer to Fig. 1 F, Fig. 2 F and Fig. 3 F, patterning conductor layer 140 is to form the control grid of strip.The method of patterning conductor layer 140 for example is prior to forming one deck patterning photoresist layer (not illustrating) on the conductor layer 140, patterning photoresist layer covers conductor layer 120, for example be to utilize dry etch process afterwards, remove conductor layer 140 between the patterning photoresist layer with for it.By seeing among Fig. 3 E, the left next mask layer 105 of the step before also keeping between the conductor layer 120.These mask layers 105 can be used as the etch stop layer of definition conductor layer 140, in such event, though the position deviation of patterning photoresist layer some, still can define the control grid (conductor layer 140) of strip, and then the raising process margin, the complexity of reduction technology.
Then, remove mask layer 105, the method that removes for example is a wet etching.Afterwards, form a plurality of doped regions 150 in the active layer between conductor layer 140.The formation method of doped region 150 for example is to be mask with conductor layer 140, carries out the alloy injection technology.The alloy that injects can be N type or P type alloy, looks closely circuit elements design and decides.Be noted that, in follow-up technology, also may on conductor layer 140, form protective layer (not illustrating), fill up the interval of control between the grid, so mask layer 105 also can select not remove, and directly as the protective layer of isolating usefulness., do not repeat them here when known as for the follow-up technology of finishing non-volatility memorizer by those skilled in the art.
The manufacture method of above-mentioned non-volatility memorizer is utilized different etching selectivity between active layer 103, the separator 101, forms a plurality of grooves 105 on the Y direction, and is come out in the top of active layer 103.This kind method can form the active layer 103 that protrudes in separator 101 more accurately.Formation for the active layer 103 of this kind fin-shaped (Fin) can obtain better control, reduces the degree of difficulty of technology.
In addition, the formation of floating grid (conductor layer 120) utilizes sacrifice layer 125 to finish with dielectric layer 127, and it need not can reduce manufacturing cost in the etched mode of photoetching for it, shortens manufacturing process.In addition, control grid (conductor layer 140) though formation can use photomask one, yet, because the usefulness of mask layer 105 as etch stop layer is arranged, can allow that photoetching process has bigger error, and improve process margin.
Fig. 1 G illustrates the stereogram of a kind of non-volatility memorizer of another embodiment of the present invention.Fig. 2 G, Fig. 3 G and Fig. 4 G illustrate the section of structure of I-I ' line, II-II ' line and III-III ' line along Fig. 1 G respectively.
Please referring again to Fig. 2 D, before dielectric layer 127 forms, or after defining the conductor layer 120 that is inverted U in active layer 103 both sides, can also remove the conductor layer 120 on the active layer 103, conductor layer 120 is separated into conductor layer 120a and conductor layer 120b, to form two independent floating grids in the active layer both sides.The method that removes segment conductor layer 120 for example is etch-back method or chemical mechanical milling method.Just as shown in Fig. 1 G, Fig. 2 G, Fig. 3 G and Fig. 4 G, conductor layer 120a and conductor layer 120b lay respectively at the both sides of active layer 103 to formed non-volatility memorizer.
The formed non-volatility memorizer of above-mentioned manufacture method below is described.Fig. 1 F illustrates the stereogram of a kind of nonvolatile memory of one embodiment of the invention.Fig. 2 F and Fig. 3 F illustrate among Fig. 1 F the section of structure along I-I ' line and II-II ' line respectively.
Please refer to Fig. 1 F, Fig. 2 F and Fig. 3 F, this non-volatility memorizer can right and wrong door type flash memory, and it is made of with a plurality of doped regions 150 substrate 100, a plurality of separator 101, a plurality of active layer 103, a plurality of floating grid 120, a plurality of control grid 140.Separator 101 is arranged in the substrate 100, defines a plurality of active layers 103, and the end face of active layer 103 is higher than the surface of separator 101, and active layer 103 and separator 101 arrangements parallel to each other, extends toward directions X.Floating grid 120 is inverted u-shaped and envelopes active layer 103.Control grid 140 covers floating grid 120, and control grid 140 is arranged in parallel, and extends toward the Y direction.Doped region 150 is arranged in the active layer of controlling between the grid 140 103.
Wherein, for example be to be provided with tunneling dielectric layer 110 between floating grid 120 and the active layer 103, the material of tunneling dielectric layer 110 for example is a silica.And for example be to be provided with dielectric layer 130 between grid between control grid 140 and the floating grid 120, the material of dielectric layer 130 for example is composite dielectric layers such as silica nitrogenize silicon/oxidative silicon between grid, or the combination of silica, silicon nitride or other dielectric material.
Above-mentioned non-volatility memorizer owing to adopt thickness fin-shaped active layer 103 as thin as a wafer and the floating grid 120 that envelopes active layer 103, can be eliminated the leakage current in the passage, avoids the problem of short-channel effect.
Moreover, because above-mentioned non-volatility memorizer forms double gate (Double Gate) structure, across tunneling dielectric layer 110 active layer 103 double teams are got up, make the two side of whole active layer 103 all can respond to the electric field that grid causes, and the firing current of the element that is increased (On-current), and the problem of minimizing leakage current.
In addition, because floating grid 120 is inverted u-shaped and envelopes active layer 103, control grid 140 then double team is lived whole floating grid 120, and the area of therefore controlling electric capacity between grid 140 and the floating grid 120 increases significantly.So, can promote the coupling coefficient of control grid 140, and then reduce the operating voltage of memory, and reduce power consumption.
Fig. 1 G illustrates the stereogram of a kind of non-volatility memorizer of another embodiment of the present invention.Fig. 2 G, Fig. 3 G and Fig. 4 G illustrate among Fig. 1 G the section of structure along I-I ' line, II-II ' line and III-III ' line respectively.In the present embodiment, floating grid 120a, 120b illustrate as Fig. 1 G, Fig. 2 G, Fig. 3 G and Fig. 4 G, are the left and right sides that the block shape is arranged at active layer 103 respectively.The configuration of all the other elements is then identical with a last embodiment.
Non-volatility memorizer in the foregoing description has equally and can eliminate leakage current in the passage, avoids short-channel effect, and increases capacity area between grid, reduces the effect of storage operation voltage.In addition, also may have the effect of two of single memory cells, make the layout of non-volatility memorizer can have more elasticity, meet the demand on the industry.
In sum, the manufacture method of non-volatility memorizer proposed by the invention not only can reduce manufacturing cost, shorten manufacturing process, and can obtain to control preferably for the formation of fin-shaped active layer, even also have the advantage that improves process margin.
In addition, the non-volatility memorizer that manufacturing is come out can be avoided short-channel effect because of the shape and the thickness of its active layer, floating grid and control grid, prevents the problem of leakage current, and the firing current of the memory that is increased, fall ground memory operating voltage.It is better that these effects all will help to form electrical performance, the non-volatility memorizer that reliability, stability and service speed are more superior.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with claim the person of being defined be as the criterion.
Claims (25)
1. the manufacture method of a non-volatility memorizer comprises:
Substrate is provided;
Form a plurality of separators in this substrate, define a plurality of active layers, these a plurality of active layers are arranged in parallel with these a plurality of separators, and extend toward first direction;
Form a plurality of grooves in these a plurality of separators, these a plurality of grooves are arranged along second direction, are come out in the top of these a plurality of active layers, and this second direction and this first direction are staggered;
Form a plurality of floating grids, be covered in these a plurality of active layers that come out on this second direction;
Form a plurality of control grids, these a plurality of control grids cover these a plurality of floating grids, and fill up this a plurality of grooves, and these a plurality of control grids are arranged in parallel and extend toward this second direction; And
Form a plurality of doped regions in this active layer between these a plurality of control grids.
2. the manufacture method of non-volatility memorizer as claimed in claim 1 wherein in forming these a plurality of separators and forming between the step of these a plurality of floating grids, also is included in this substrate and forms tunneling dielectric layer.
3. the manufacture method of non-volatility memorizer as claimed in claim 1 wherein forms dielectric layer between grid in forming these a plurality of floating grids and form between the step of these a plurality of control grids, also being included in this substrate.
4. the manufacture method of non-volatility memorizer as claimed in claim 1 wherein forms these a plurality of grooves in a plurality of separators of this on this second direction, the method that is come out in the top of these a plurality of active layers comprises:
Form a plurality of mask layers in these a plurality of insulation surface, these a plurality of mask layers are arranged in parallel, and extend toward this second direction; And
With these a plurality of mask layers is mask, removes the top that these a plurality of separators come out, and forms these a plurality of grooves in these a plurality of separators, is come out in the top of these a plurality of active layers.
5. the manufacture method of non-volatility memorizer as claimed in claim 4, wherein the formation method of these a plurality of floating grids comprises:
In this substrate, form first conductor layer;
On this first conductor layer, form sacrifice layer;
Remove this sacrifice layer on this mask layer, to expose this first conductor layer on this mask layer;
Remove this first conductor layer that these mask layer both sides are exposed;
Remove this sacrifice layer on this active layer, expose this first conductor layer on this active layer; And
Remove this first conductor layer of part of this interior sacrifice layer of these a plurality of grooves and these a plurality of bottom portion of groove.
6. the manufacture method of non-volatility memorizer as claimed in claim 5, wherein this sacrifice layer has different etching selectivities with this first conductor layer.
7. the manufacture method of non-volatility memorizer as claimed in claim 6, the method that wherein removes this sacrifice layer and this first conductor layer of part of these a plurality of bottom portion of groove in these a plurality of grooves comprises:
This first conductor layer surface that is exposed on this active layer forms a dielectric layer;
Remove this sacrifice layer in this groove; And
With this dielectric layer is mask, removes this first conductor layer that exposes.
8. the manufacture method of non-volatility memorizer as claimed in claim 7 also comprises this first conductor layer that removes on this active layer end face, makes this first conductor layer be separated in this active layer two side.
9. the manufacture method of non-volatility memorizer as claimed in claim 4, the method that wherein forms these a plurality of control grids comprises:
In this substrate, form second conductor layer;
Form patterning photoresist layer in this substrate, cover this a plurality of floating grids, this patterning photoresist layer is arranged in parallel, and extends toward this second direction;
With this patterning photoresist layer is mask, removes this second conductor layer of part; And
Remove this patterning photoresist layer.
10. the manufacture method of non-volatility memorizer as claimed in claim 9 comprises that also with this mask layer be etch stop layer, removes this second conductor layer of part.
11. the manufacture method of non-volatility memorizer as claimed in claim 10 wherein after removing this second conductor layer of part, also comprises removing this mask layer.
12. the manufacture method of non-volatility memorizer as claimed in claim 1, wherein this substrate comprises silicon base on the insulating barrier.
13. the manufacture method of a non-volatility memorizer comprises:
Substrate is provided;
Form a plurality of separators in this substrate, define a plurality of active layers, these a plurality of active layers are arranged in parallel with these a plurality of separators, and extend toward first direction;
Form a plurality of mask layers in this substrate, these a plurality of mask layers are arranged in parallel, and extend toward second direction, and this second direction and this first direction are staggered;
With these a plurality of mask layers is mask, removes the top that these a plurality of separators expose, and forms a plurality of grooves in these a plurality of separators, and these a plurality of grooves are arranged along this second direction, are come out in the top of these a plurality of active layers;
On these a plurality of active layers, form tunneling dielectric layer;
In this substrate, form first conductor layer and a sacrifice layer in regular turn;
Remove this sacrifice layer on this mask layer, expose this first conductor layer on this mask layer;
Remove this first conductor layer that these mask layer both sides are exposed;
Remove this sacrifice layer on this active layer, expose this first conductor layer on this active layer;
This first conductor layer surface that is exposed on this active layer forms dielectric layer;
Remove this sacrifice layer that exposes;
With this dielectric layer is mask, removes this first conductor layer of part of these a plurality of bottom portion of groove;
In this substrate, form the dielectric layer and second conductor layer between grid in regular turn;
This second conductor layer of patterning makes this second conductor layer be strip and covers this first conductor layer, and these a plurality of second conductor layers are arranged in parallel, and extends toward this second direction;
Remove this mask layer; And
Form a plurality of doped regions in this active layer between this second conductor layer.
14. the manufacture method of non-volatility memorizer as claimed in claim 13 wherein after this sacrifice layer on removing this active layer, before this dielectric layer of formation, also comprises this first conductor layer that removes on this active layer.
15. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this first conductor layer that exposes comprises the etch-back method.
16. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this sacrifice layer on this active layer comprises:
Recess in this sacrifice layer is inserted photoresist;
Carry out the etch-back method and remove this sacrifice layer of this active layer; And
Remove this photoresist.
17. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this sacrifice layer on this active layer comprises chemical mechanical milling method.
18. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this sacrifice layer that exposes comprises wet etching.
19. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this first conductor layer of part of these a plurality of bottom portion of groove comprises the etch-back method.
20. the manufacture method of non-volatility memorizer as claimed in claim 13, wherein the method for this second conductor layer of patterning comprises:
Form patterning photoresist layer in this substrate, cover this first conductor layer, this patterning photoresist layer is arranged in parallel, and extends toward this second direction;
With this patterning photoresist layer is mask, removes this second conductor layer of part; And
Remove this patterning photoresist layer.
21. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this mask layer comprises wet etching.
22. the manufacture method of non-volatility memorizer as claimed in claim 13, wherein the formation method of this tunneling dielectric layer comprises thermal oxidation method.
23. the manufacture method of non-volatility memorizer as claimed in claim 13, wherein the formation method of dielectric layer comprises thermal oxidation method between these grid.
24. the manufacture method of non-volatility memorizer as claimed in claim 13, wherein the formation method of this dielectric layer comprises thermal oxidation method.
25. the manufacture method of non-volatility memorizer as claimed in claim 13, the method that wherein removes this sacrifice layer on this mask layer comprises chemical mechanical milling method.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101297459A CN100468743C (en) | 2005-12-06 | 2005-12-06 | Non-volatile memory and mfg. method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2005101297459A CN100468743C (en) | 2005-12-06 | 2005-12-06 | Non-volatile memory and mfg. method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1979863A CN1979863A (en) | 2007-06-13 |
| CN100468743C true CN100468743C (en) | 2009-03-11 |
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| Application Number | Title | Priority Date | Filing Date |
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| CNB2005101297459A Expired - Fee Related CN100468743C (en) | 2005-12-06 | 2005-12-06 | Non-volatile memory and mfg. method |
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| Country | Link |
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| CN (1) | CN100468743C (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124249A (en) * | 2013-04-25 | 2014-10-29 | 苏州东微半导体有限公司 | Fin-type semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5053839A (en) * | 1990-01-23 | 1991-10-01 | Texas Instruments Incorporated | Floating gate memory cell and device |
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2005
- 2005-12-06 CN CNB2005101297459A patent/CN100468743C/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5053839A (en) * | 1990-01-23 | 1991-10-01 | Texas Instruments Incorporated | Floating gate memory cell and device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN104124249A (en) * | 2013-04-25 | 2014-10-29 | 苏州东微半导体有限公司 | Fin-type semiconductor device |
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| Publication number | Publication date |
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| CN1979863A (en) | 2007-06-13 |
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