CN100470869C - Multiple layer phase-change memory - Google Patents

Multiple layer phase-change memory Download PDF

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Publication number
CN100470869C
CN100470869C CN02816937.9A CN02816937A CN100470869C CN 100470869 C CN100470869 C CN 100470869C CN 02816937 A CN02816937 A CN 02816937A CN 100470869 C CN100470869 C CN 100470869C
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China
Prior art keywords
phase
change material
ground floor
layer
unit
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Expired - Fee Related
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CN02816937.9A
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Chinese (zh)
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CN1568551A (en
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S·J·赫金斯
T·A·劳里
P·J·克莱尔斯
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Intel Corp
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Intel Corp
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/20—Multistable switching devices, e.g. memristors
    • H10N70/231—Multistable switching devices, e.g. memristors based on solid-state phase change, e.g. between amorphous and crystalline phases, Ovshinsky effect
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/86—Types of semiconductor device ; Multistep manufacturing processes therefor controllable only by variation of the electric current supplied, or only the electric potential applied, to one or more of the electrodes carrying the current to be rectified, amplified, oscillated or switched
    • H01L29/861—Diodes
    • H01L29/8615—Hi-lo semiconductor devices, e.g. memory devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/011—Manufacture or treatment of multistable switching devices
    • H10N70/061—Patterning of the switching material
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/821—Device geometry
    • H10N70/826—Device geometry adapted for essentially vertical current flow, e.g. sandwich or pillar type devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/861—Thermal details
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N—ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10N70/00—Solid-state devices without a potential-jump barrier or surface barrier, and specially adapted for rectifying, amplifying, oscillating or switching
    • H10N70/801—Constructional details of multistable switching devices
    • H10N70/881—Switching materials
    • H10N70/882—Compounds of sulfur, selenium or tellurium, e.g. chalcogenides
    • H10N70/8828—Tellurides, e.g. GeSbTe

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)

Abstract

A phase-change memory may be formed with at least two phase-change material layers separated by a barrier layer. The use of more than one phase-change layer enables a reduction in the programming volume while still providing adequate thermal insulation.

Description

Be used to form the method and the memory cell of multilayered phase change memory
Technical field
The present invention relates generally to the memory that uses phase-change material.
Background technology
Phase-change material can present at least two kinds of different conditions.These states can be called amorphous state and crystalline state.For example, can select to be enabled in conversion between these states by variations in temperature.These states can be distinguished, and are because amorphous state demonstrates the resistivity higher than crystalline state usually.Amorphous state comprises more unordered atomic structure, and crystalline state comprises more orderly atomic structure.Usually, can use any phase-change material; Yet in certain embodiments, thin-film chalcogenide alloy materials is particularly suitable for.
Can reversibly cause phase transformation.Therefore, memory can change to crystalline state and can be returned to amorphous state subsequently from amorphous state, and vice versa.In fact, each memory cell can be considered to programmable resistance, and it is according to variations in temperature reversible variation between high resistance and low resistance.Can cause variations in temperature by resistance heating.
In some cases, the unit can have a large amount of states.That is to say that because each state can be distinguished by its resistance, the state that a plurality of resistance are determined is possible, allow in a single unit, to preserve long numeric data.
Various phase-change alloys are known.Usually, chalcogenide alloy comprises one or more elements of the VI family of periodic table.It is the GeSbTe alloy that of alloy is particularly suitable for group.
Phase-change material can form in passage that defines by dielectric substance or pore.Phase-change material can be on a wherein end of passage connection electrode.Contact can make electric current by this passage so that by resistance heating to the programming of this unit or read the programming state of this unit.
Current phase transition storage carries out thermal insulation according to the lower thermal conductivity of chalcogenide phase change storage material self with programmable volume and top electrode thermal losses.Therefore, in order to obtain better thermal insulation, and more effective energies programmings of programmable volume thus, have to increase the thickness of chalcogenide layer.Yet the increase of layer thickness has also increased the material volume that can experience phase transformation during programming.The volume of the material of increase experience phase transformation all has a negative impact to reliability, stability and the cycle life of memory.
Therefore, need have the phase transition storage that improves feature and performance.
Summary of the invention
According to an aspect of the present invention, provide a kind of method that is used to form multilayered phase change memory, comprising:
On Semiconductor substrate, form pore;
On described pore, form sidewall spacers;
On described sidewall spacers, form the ground floor phase-change material;
On described ground floor, form non-phase-change material; With
On described non-phase-change material, form second layer phase-change material,
Wherein said non-phase-change material be conduction to allow electric current by the described non-phase-change material between described first and second layers.
According to a further aspect in the invention, provide a kind of method that is used to form multilayered phase change memory, comprising:
Formation has the ground floor phase-change material of first thickness;
Form non-phase-change material on described ground floor, described non-phase-change material has second thickness less than described first thickness; With
On described non-phase-change material, form second layer phase-change material so that the described ground floor and the second layer are isolated fully by described non-phase-change material,
Wherein said non-phase-change material be conduction to allow electric current by the described non-phase-change material between described first and second layers.
According to a further aspect in the invention, provide a kind of memory cell, comprising:
The ground floor phase-change material;
Second layer phase-change material; With
Non-phase-change material between the described ground floor and the second layer, described non-phase-change material make the described ground floor and the described second layer isolate fully and make electric current pass through described non-phase-change material simultaneously and flow between the described ground floor and the second layer.
According to a further aspect in the invention, provide a kind of memory cell, comprising:
The ground floor phase-change material; With
Second layer phase-change material, in described ground floor phase-change material and the second layer phase-change material only wherein one deck be programmable.
According to a further aspect in the invention, provide a kind of memory cell, comprising:
The ground floor phase-change material;
The second layer phase-change material that is different from the phase-change material of described ground floor; With
Non-phase-change material between the described ground floor and the second layer,
In the wherein said ground floor and the second layer one is that in the programmable and described ground floor and the second layer another is non-programmable.
According to a further aspect in the invention, provide a kind of memory cell, comprising:
The ground floor phase-change material;
Second layer phase-change material; With
At the non-phase-change material of conduction to allow to conduct electricity between described first and second layers between the described ground floor and the second layer.
Description of drawings
Fig. 1 is the amplification profile of one embodiment of the present of invention;
Fig. 2 is an early stage amplification profile of making device shown in Figure 1 in conjunction with one embodiment of the present of invention;
Fig. 3 is the amplification profile at the embodiment shown in Figure 2 in the later stage of making in conjunction with one embodiment of the present of invention;
Fig. 4 is the amplification profile at the embodiment shown in Figure 3 in the more later stage of making in conjunction with one embodiment of the present of invention;
Fig. 5 is the amplification profile at the embodiment shown in Figure 4 in the more later stage of making in conjunction with one embodiment of the present of invention;
Fig. 6 is the amplification profile at the embodiment shown in Figure 5 in the more later stage of making in conjunction with one embodiment of the present of invention.
Embodiment
With reference to figure 1, phase transition storage 10 can form on integrated circuit substrate 12.Phase transition storage 10 can comprise bottom electrode 14, and it is formed by the silicide that contains cobalt in one embodiment.Top electrode 28 is clipped between following programmable phase-change layer 22 and the top phase change layer 26.It between phase change layer 22 and 26 chemical barrier 24.
The pore of phase transition storage 10 can be limited by sidewall spacers 20.That is to say that the contact area between bottom electrode 14 and phase change layer 22 can be by covering cylindrical side wall partition 20 determined sizes.In one embodiment, comprise that the pore of phase change layer 22 and 26 can be limited in the opening that forms with paired insulator layer, for example go up insulating barrier 18 and low insulation layer 16.Going up insulating barrier 28 in one embodiment can be silicon dioxide, and low insulation layer 16 can be a silicon nitride in one embodiment.
Although show the structure of wherein having used two-layer phase-change material, can use more multi-layered in other embodiments.The thickness of first phase change layer 22 can be in the scope of 300-500 dust.The thickness that can select this layer is to reduce the vertical dimension of programmable volume.Can be in the opening of the cup-shape that forms by sidewall spacers 20 deposit phase change layer 22, produce the phase change layer 22 of cup-shape.Therefore barrier layer 24 and top phase change layer 26 have been defined analogous shape.In one embodiment, can use vapour deposition to form phase change layer 22 and 26.
Barrier layer 24 provide below programmable phase-change layer 22 and the chemical barrier between the top phase change layer 26.In certain embodiments, can thermal insulation be provided primarily for top phase change layer 26.Barrier layer 24 can have enough conductivity, makes program current lateral flow around any resistance area of thermally insulated phase change layer 26 by programmable phase-change layer 22, and can contact the conducting region away from this layer of program regions.
The typical thickness on barrier layer 24 can be in the scope of 50-200 dust.Thermally insulated phase change material layer 26 also can be in situ by vapour deposition above barrier layer 24.Thermally insulated phase change material layer 26 can form or it also can be selected from the scope of obtained chalcogenide material with lower thermal conductivity with the compositions identical with programmable phase-change layer 22.In one embodiment, layer 26 has less than the thermal conductivity of 1E-2W/cm.K with for example greater than 40 Ω -1Cm -1Excellent electrical conductivity be advantageous.Layer 26 thickness can from 100 to scope more than 1000 dusts.
With reference to figure 2, can be on the lamination that comprises substrate 12 definition mask 30, this substrate 12 is coated with bottom electrode 14, first insulating barrier 16, second insulating barrier 18.
Below with reference to Fig. 3, can be by insulating barrier 16 and 18 corrosion openings 32, this corrosion terminates in bottom electrode 14.In one embodiment, can use a kind of etchant, it is selected at layer 16 and 18, and to electrode 14 nearly unavailables.Subsequently, as shown in Figure 4, insulating material 20 can be deposited in the pore and layer 18 on.Can use multiple insulating barrier, comprise oxide.In one embodiment, can use tetraethyl orthosilicate (TEOS) oxide deposition technology.Then illuvium 20 is carried out anisotropic etch so that form cylindrical side wall partition 20, as shown in Figure 5.
Can cover sidewall spacers 20 and insulating barrier 18 with programmable phase-change layer 22 then.Can use barrier layer 24 and thermally insulated phase change layer 26 cover layer 22 then.At last, can deposit top electrode 28.Because the covering of sidewall spacers 20, to a certain extent, each layer of layer 22,24,26 and 28 all is restricted to the configuration of cup-shape.In certain embodiments, can carry out composition and corrosion so that form the structure shown in Fig. 1 to structure shown in Figure 6 then.
By using the chalcogenide layer of multilayer, memory cell 10 is benefited from the thermal insulation of enhancing.Simultaneously, the material volume of experience phase transformation can be limited relatively during programming.In other words, the insulation effect of the layer 22 and 26 of combination can reduce the thermal loss from memory 10, improves program performance.Simultaneously, to insulating barrier 26 programmings not necessarily, reduced the material volume that during programming, must experience phase transformation like this.In certain embodiments, this can improve reliability, stability and the cycle life of memory 10.
Although described the present invention in conjunction with limited a plurality of embodiment, those skilled in the art will appreciate that a plurality of modifications and modification according to it.Its intention of the appended claims is to cover all modifications and the modification that falls in true spirit of the present invention and the scope.

Claims (41)

1. method that is used to form multilayered phase change memory comprises:
On Semiconductor substrate, form pore;
On described pore, form sidewall spacers;
On described sidewall spacers, form the ground floor phase-change material;
On described ground floor, form non-phase-change material; With
On described non-phase-change material, form second layer phase-change material,
Wherein said non-phase-change material be conduction to allow electric current by the described non-phase-change material between described first and second layers.
2. according to the method for claim 1, comprise the ground floor and the second layer that form same material.
3. according to the method for claim 1, comprise the ground floor and the second layer that form different materials.
4. according to the method for claim 1, be included in and form contact on the described substrate and the described sidewall spacers of formation in described contact.
5. according to the method for claim 4, comprise described contact is contacted with described ground floor.
6. according to the method for claim 1, comprise forming to have the described ground floor of thickness between 300 to 500 dusts.
7. according to the method for claim 6, comprise forming to have the described non-phase-change material of thickness between 50 to 200 dusts.
8. method that is used to form multilayered phase change memory comprises:
Formation has the ground floor phase-change material of first thickness;
Form non-phase-change material on described ground floor, described non-phase-change material has second thickness less than described first thickness; With
On described non-phase-change material, form second layer phase-change material so that the described ground floor and the second layer are isolated fully by described non-phase-change material,
Wherein said non-phase-change material be conduction to allow electric current by the described non-phase-change material between described first and second layers.
9. method according to Claim 8 comprises the ground floor and the second layer that form same material.
10. method according to Claim 8 comprises the ground floor and the second layer that form different materials.
11. method according to Claim 8 is included in and forms pore on the substrate.
12., be included on the described pore and form sidewall spacers according to the method for claim 11.
13., be included in and form described ground floor and the second layer and described non-phase-change material on the described sidewall spacers according to the method for claim 12.
14. method according to Claim 8 is included on the substrate and forms contact and form sidewall spacers in described contact.
15., comprise described contact is contacted with described ground floor according to the method for claim 14.
16. a memory cell comprises:
The ground floor phase-change material;
Second layer phase-change material; With
Non-phase-change material between the described ground floor and the second layer, described non-phase-change material make the described ground floor and the described second layer isolate fully and make electric current pass through described non-phase-change material simultaneously and flow between the described ground floor and the second layer.
17. according to the unit of claim 16, wherein said ground floor phase-change material is formed by chalcogenide material.
18. according to the unit of claim 16, wherein said ground floor is different phase-change materials with the second layer.
19. according to the unit of claim 16, wherein said ground floor and second layer phase-change material are same materials.
20., comprise Semiconductor substrate and electrically contacting of in described substrate, forming according to the unit of claim 16.
21., be included in insulating barrier that forms on the described substrate and the passage that forms by described insulating barrier according to the unit of claim 20.
22. according to the unit of claim 21, the wherein said ground floor and the second layer form in described passage at least in part.
23., be included in the sidewall spacers that forms in the described passage in the described contact according to the unit of claim 22.
24. according to the unit of claim 16, the wherein said ground floor and the second layer are cup-shape.
25., wherein dispose described second layer phase-change material so that thermal insulation to be provided according to the unit of claim 16.
26. a memory cell comprises:
The ground floor phase-change material; With
Second layer phase-change material, in described ground floor phase-change material and the second layer phase-change material only wherein one deck be programmable.
27., be included in the non-phase-change material between the described ground floor and the second layer according to the unit of claim 26.
28. according to the unit of claim 26, wherein the ground floor phase-change material is programmable, second layer phase-change material is configured to provide thermal insulation.
29. according to the unit of claim 26, wherein said ground floor phase-change material is formed by chalcogenide material.
30. according to the unit of claim 26, wherein said ground floor is different phase-change materials with the second layer.
31. according to the unit of claim 26, wherein said ground floor and second layer phase-change material are same materials.
32. according to the unit of claim 27, wherein said non-phase-change material is a conductor.
33., comprise Semiconductor substrate and electrically contacting of on described substrate, forming according to the unit of claim 26.
34., comprise insulating barrier that forms on the described substrate and the passage that forms by described insulating barrier according to the unit of claim 33.
35. according to the unit of claim 34, the wherein said ground floor and the second layer form in described passage at least in part.
36. a memory cell comprises:
The ground floor phase-change material;
The second layer phase-change material that is different from the phase-change material of described ground floor; With
Non-phase-change material between the described ground floor and the second layer,
In the wherein said ground floor and the second layer one is that in the programmable and described ground floor and the second layer another is non-programmable.
37. according to the unit of claim 36, wherein said non-phase-change material is an electric conductor.
38., wherein dispose described second layer phase-change material so that thermal insulation to be provided according to the unit of claim 36.
39. a memory cell comprises:
The ground floor phase-change material;
Second layer phase-change material; With
At the non-phase-change material of conduction to allow to conduct electricity between described first and second layers between the described ground floor and the second layer.
40. according to the unit of claim 39, wherein said ground floor is different phase-change materials with the second layer.
41. according to the unit of claim 39, the wherein said ground floor and the second layer are same materials.
CN02816937.9A 2001-08-31 2002-08-20 Multiple layer phase-change memory Expired - Fee Related CN100470869C (en)

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WO (1) WO2003021692A2 (en)

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