CN100477168C - 用于改善6t cmos sram单元稳定性的方法和装置 - Google Patents
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Abstract
本发明是一种CMOS SRAM单元,包括:两个存取器件,每一个存取器件由具有单个鳍(410)的三栅晶体管(400)构成;两个上拉器件,每一个上拉器件由具有单个鳍(410)的三栅晶体管(400)构成;以及,两个下拉器件,每一个下拉器件由具有多个鳍(410)的三栅晶体管(500)构成。还提供了一种用于制造所述CMOS SRAM单元,包括双鳍三栅晶体管的方法。由于鳍,栅极长度相对于具有相同面积的平面晶体管被增加了。因此,增加了单元比率和静态噪声容限,提供了改善的稳定性而不增加单元面积或电源电压。
Description
发明背景
1.发明领域
本发明涉及半导体集成电路设计和制造领域,并特别涉及使用三栅全耗尽型衬底晶体管(tri-gate fully depleted substrate transistor)的6T CMOS SRAM单元及其制造方法。
2.相关领域讨论
随着硅技术不断从一代升级到下一代,最小几何尺寸的体平面晶体管的本征阈值电压(Vt)变化的影响减小了CMOS SRAM单元静态噪声容限(SNM)。由日益变小的晶体管几何形状所导致的SNM减小是不期望的。当Vcc被缩小到更低的电压时,SNM被进一步减小。
平面晶体管阈值电压(Vt)变化主要源自于晶体管耗尽区中掺杂物质原子的数量和/或位置的统计波动。Vt变化给电源电压、晶体管尺寸的缩小造成了障碍,因而给最小的6晶体管(6T)CMOS SRAM单元尺寸的缩小造成了障碍。由于管芯(die)尺寸和成本约束,这限制了以常规6T SRAM为主导的高性能CMOS ASIC和微处理器的总晶体管数。
目前,通过以下(a)或(b)手段,在电路/布图(layout)层面(level)解决由SRAM单元晶体管的Vt不稳定性导致的减小的SNM问题:(a)增加使单元工作所需要的最小电源电压(Vccmin),并保持最小几何尺寸晶体管,或者(b)增加单元晶体管的沟道(channel)长度和宽度,以便以最小单元尺寸为代价,使得更低的最小工作电压成为可能。在器件层面上,以额外的制造工艺复杂性为代价,利用箱形阱(box-shaped well)或超陡倒掺杂阱(super-steep retrograde well),可以最小化平面器件中源自随机掺杂物质波动(RDF)的Vt失配。
图1中示出了一种使用平面晶体管的6T CMOS SRAM单元电路图。该SRAM单元由两个N型存取器件102,两个N型下拉器件104,以及两个P型上拉器件106组成。
图2示出了使用平面晶体管的6T CMOS SRAM单元的布图。每一个存取器件的栅极位于区域202中。每一个下拉器件的栅极位于区域204中。每一个上拉器件的栅极位于区域206中。栅极区域由P型扩散212或N型扩散210之上的多晶硅区域214指示。金属层218提供电源(Vcc)和地(Vss)。金属层218也可以将单元中的一个平面晶体管的栅极/源极/漏极连接到单元中另一个晶体管的栅极/源极/漏极,并且可以将一个单元互连到另一个。接触体(contact)216指示可以连接到金属层的区域。对于给定的Vcc,通过定出每一个存取晶体管宽度和每一个下拉晶体管宽度的大小来定制单元比率(cell ratio),以便获得最大的SNM值。
图3是说明电源电压缩小对使用平面晶体管的典型6T CMOS SRAM单元的影响的图300。这些噪声容限值假定为标称阈值电压、标称Vcc,以及标称器件尺寸。虚线310指示SNM的最小期望值240毫伏。该图示出,当Vcc从2伏缩小到小于1伏时,单元比率必定增加,以便保持期望的SNM值。对于1.5的单元比率(302),在保持240毫伏的标称SNM的同时能够获得的最小电压略低于2.0伏。当单元比率增加到2.0(304)时,在保持标称SNM的同时能够获得的最小电压小于1.5伏。如果单元比率增加到3.5(306),则最小电压可以被减小到小于1.0伏。但是,增加单元比率对应以增加单元尺寸为形式的面积损失。
附图简要说明
图1图示使用平面晶体管的现有技术6T CMOS SRAM单元电路图。
图2图示使用平面晶体管的现有技术6T CMOS SRAM单元布图。
图3为针对不同单元比率的6T SRAM单元图示作为电源电压的函数的静态噪声容限的图。
图4是单鳍三栅晶体管的剖视图。
图5是双鳍三栅晶体管的剖视图。
图6图示具有根据本发明的一个实施方案的三栅晶体管的6T CMOS SRAM单元电路图。
图7图示使用根据本发明的一个实施方案的单鳍和双鳍三栅晶体管的6T CMOSSRAM单元布图。
图8是根据本发明的一个实施方案的双鳍三栅晶体管与平面晶体管的栅极宽度的比较。
图9是将根据本发明一个实施方案的三栅SRAM的SNM(作为电源电压的函数)和平面SRAM的SNM(作为电源电压的函数)进行比较的图,其中两种SRAM单元具有相同的布图面积。
图10是描述形成根据本发明的一个实施方案的双鳍三栅晶体管的流程图。
图11A到11J示出了根据本发明的一个实施方案的双鳍三栅晶体管的形成。
具体实施方式
本发明是使用非平面三栅晶体管的6T CMOS SRAM单元及其制造方法。在下面的描述中,为了提供对本发明透彻的理解,给出了许多具体细节。在其他的实例中,为了不要不必要地模糊本发明,未详细地描述公知的半导体工艺以及制造技术。
本发明利用非平面三栅晶体管更高的驱动电流性能来改善6T CMOS SRAM单元的稳定性,从而能够实现(enable)低电源电压工作和减小的单元布图尺寸。对于给定的布图宽度,多鳍结构的三栅晶体管能够比平面晶体管输送更多的驱动电流。
图4示出了典型的单鳍三栅晶体管400的剖面图。单鳍三栅晶体管是具有单个半导体主体(semiconductor body)410的三栅晶体管。半导体主体也将被称为“半导体鳍(fin)”。半导体主体在绝缘衬底402上形成。绝缘衬底由硅或其他在半导体衬底404之上的掩埋氧化物或其他的绝缘层406构成。在半导体鳍410之上以及侧面上形成栅极电介质416。在栅极电介质之上以及侧面上形成栅极电极420。栅极电极具有栅极宽度GL。在栅极电极两侧上的半导体鳍中形成源极S和漏极D区域。
半导体鳍具有上表面412和在横向相对的侧壁414。半导体鳍具有等于Tsi的高度或厚度。半导体鳍具有等于Wsi的宽度。单鳍三栅晶体管的栅极宽度等于在半导体主体上形成的三个栅极中的每一个的栅极宽度之和,或者说Tsi+Wsi+Tsi。
图5示出了根据本发明的一个实施方案的典型双鳍三栅晶体管500的剖面图。双鳍三栅晶体管是在绝缘衬底402之上具有两个半导体主体或鳍的三栅晶体管,所述两个鳍每一个均具有在上表面和在横向相对的侧壁上形成的栅极电介质,并共享在栅极电介质之上以及周围形成的单个栅极电极。每一个半导体鳍均具有上表面412和在侧面上相对的侧壁414。这些半导体鳍被隔开距离Ds。利用常规光刻技术的图形化允许大约240nm的最小Ds。双鳍三栅晶体管的栅极宽度等于这两个半导体主体中的每一个的栅极宽度之和,或者说[2(Tsi1)+(Wsil)]+[2(Tsi2)+(Wsi2)]。如果以使得每一个半导体主体均具有基本类似的尺度的方式来形成这些半导体主体,则双鳍三栅晶体管的栅极宽度实际上是单鳍三栅晶体管栅极宽度的两倍。通过给三栅晶体管增加额外的鳍,能够进一步增加三栅晶体管的栅极宽度。对于给定的布图宽度,多鳍结构的三栅晶体管能够比平面三极管输送更多的驱动电流,因为具有和平面晶体管相同尺寸的三栅晶体管将具有更大的栅极宽度。
图6示出了使用根据本发明的一个实施方案的三栅晶体管的6T CMOS SRAM单元电路图。SRAM单元由两个N型存取器件602,两个N型下拉器件604,以及两个P型上拉器件606组成。每一个N型存取器件602均为单鳍三栅晶体管。每一个P型上拉器件606均为单鳍三栅晶体管。每一个N型下列器件604均为双鳍三栅晶体管。使用双鳍三栅晶体管作为下拉器件允许电路设计者获得SRAM单元的更高的单元比率。双鳍三栅晶体管将比单鳍三栅晶体管输送更多的电流,因而增加了单元比率却不增加单元布图尺寸。
SRAM单元的单元比率被定义为下拉N型晶体管的跨导因子与存取N型晶体管的跨导因子的比率。晶体管的跨导因子等于栅极宽度与栅极长度乘上迁移率(mobility)及栅极电容的比例。其中迁移率及栅极电容从存取晶体管到下拉晶体管是不变的,跨导因子变成晶体管栅极宽度与晶体管栅极长度的比例。双鳍三栅晶体管的跨导因子将大于平面晶体管的跨导因子,因为在相同的布图面积内,双鳍三栅晶体管的晶体管栅极宽度大于平面晶体管的晶体管栅极宽度。此外,双鳍三栅晶体管的跨导因子将大于单鳍三栅晶体管的跨导因子,因为双鳍器件的栅极宽度与栅极长度的比率将大于单鳍器件的这一比率。使用双鳍三栅晶体管作为下拉器件增加了下拉器件的跨导因子,因而增加了SRAM单元的单元比率。如上所述,通过增加单元比率,能够获得更高的因而更令人期望的静态噪声容限(SNM)水平。在SRAM单元设计中使用非平面三栅晶体管允许增加单元比率而不增加物理单元布图尺寸。下面的表1是使用平面晶体管的SRAM单元和使用三栅晶体管的SRAM单元的单元比率的比较,其中,每一个SRAM单元均具有相同的布图面积。
表1
图7示出了使用根据本发明的一个实施方案的三栅晶体管的6T CMOS SRAM单元布图。每一个存取器件的栅极均位于区域702中。每一个下拉器件的栅极均位于区域704中。每一个下拉器件均为双鳍器件。器件的每一个鳍由牺牲块(sacrificial block)709任一侧上的区域708指示。牺牲块709用于形成彼此非常邻近的鳍。使用牺牲块709允许鳍彼此被隔开小于100nm,这对于使用传统的光刻来讲是不可能的。每一个上拉器件的栅极均位于区域706中。栅极区域由P型扩散712或者N型扩散710区域之上的多晶硅区域714指示。金属层718提供电源(Vcc)和地(Vss)。金属层718也可以将单元中的一个平面晶体管的栅极/源极/漏极连接到单元中另一个晶体管的栅极/源极/漏极,并且可以将一个SRAM单元连接到另一个。接触体716指示可以进行到金属层的连接的区域。对于给定的Vcc,通过定出每一个存取晶体管宽度和每一个下拉晶体管宽度的大小来定制单元比率(cell ratio),以便获得最大的SNM值。如上所述,使用N型双鳍三栅器件作为下拉器件以及N型单鳍三栅器件作为存取器件,允许三栅SRAM单元被设计成在和平面SRAM单元相同的布图面积内具有更高的单元比率。
图8是根据本发明的一个实施方案的双鳍三栅晶体管的栅极宽度与相同布图面积内的平面晶体管的栅极宽度的比较。剖面图800示出了在绝缘衬底808上形成的双鳍三栅晶体管。三栅晶体管的鳍由半导体主体802形成。鳍被分开的距离为Ds,距离Ds由上面描述的牺牲块的宽度决定。距离Ds可以由可被图形化的最小光刻特征尺寸来限定。栅极电介质804覆盖了栅极区域中三栅晶体管的每一个鳍。在栅极电介质以及每一个半导体鳍之上以及周围形成栅极电极806。针对该双鳍三栅晶体管的每一个鳍,形成了三个栅极G1、G2和G3。被形成的每一个栅极均具有栅极宽度。G1的栅极宽度等于Z1,或者说鳍的高度。G2的栅极宽度等于Z2,或者说鳍的宽度。G3的栅极宽度等于Z3,或者说鳍的高度。。每一个鳍总的栅极宽度等于Z1+Z2+Z3。对于双鳍三栅晶体管,总的栅极宽度等于2(Z1+Z2+Z3)。具有N个鳍的三栅晶体管具有等于N(Z1+Z2+Z3)的总栅极宽度。在本发明的一个实施方案中,Z1=60nm,Z2=60nm,Z3=60nm,并且Ds=60nm。根据这个实施方案的三栅晶体管的栅极宽度是2(60nm+60nm+60nm),或者说360nm。所使用的总的布图宽度等于Z3+D+Z3,或者说(60nm+60nm+60nm)=180nm。
剖面图820示出了在半导体衬底828上形成的平面晶体管。该平面晶体管的栅极宽度等于晶体管822的宽度,或者说Zp。对于180nm的布图宽度,平面晶体管820的栅极宽度等于180nm。因为对于相同的布图面积,三栅晶体管的栅极宽度是平面晶体管的栅极宽度的两倍,所以有可能通过设计使用根据本发明的一个实施方案的单鳍和双鳍三栅晶体管的单元,来增加6T CMOS SRAM单元的单元比率。
图9为针对平面SRAM单元920和三栅SRAM单元910,示出作为Vcc的函数的静态噪声容限(SNM)的图900,其中,这些单元尺寸相同。三栅SRAM单元设计允许在超过240mv(930)的SNM下限之前将Vcc缩小得更低。因为当使用根据本发明的一个实施方案的三栅晶体管设计SRAM单元时单元比率更高,所以电源电压可以被缩小得更低而不将SNM减小到240毫伏以下。使用平面晶体管设计的SRAM单元能够在略小于2.0伏的电源电压下工作而不将SNM减小到240毫伏以下。尺寸相同但是使用根据本发明的一个实施方案的双鳍和单鳍三栅晶体管设计的SRAM单元在遭遇SNM限制之前可以在低得多的电源电压下工作。在SNM被减小到小于240毫伏之前,电源电压可以低至1.25伏。
图10为流程图1000,示出了根据本发明的一种过程,说明用于形成具有减小的布图宽度的多鳍三栅晶体管的一般方法。下面结合图11A到11J进一步详细地说明和描述流程图1000中的每一个框。
如框1002中所描述的那样,在绝缘衬底上形成硅或半导体膜。绝缘衬底包括底下的单晶硅衬底和顶部的绝缘层,例如二氧化硅膜或者氮化硅膜。绝缘层有时候被称为“掩埋氧化物”层。在本发明的一个实施方案中,半导体膜具有60nm的厚度。
然后,在半导体膜上形成具有上表面和横向相对的侧壁的牺牲块,如框1004中所描述的那样。在本发明的一个实施方案中,通过首先形成牺牲材料层并且使用光刻来图形化所述牺牲材料以便形成块,从而形成所述牺牲块。牺牲块可以由氮化物构成,但是不限于氮化物。牺牲块的宽度决定了鳍的间隔。在本发明的一个实施方案中,牺牲块横向相对的侧壁间隔60nm。在本发明的另一个实施方案中,牺牲块横向相对的侧壁间隔由使用光刻可形成的最小特征尺寸限定的距离。
形成牺牲块以后,在所述牺牲块和半导体膜之上以及周围形成绝缘层,如框1006中所描述的那样。绝缘层可以由氧化物或者另一种绝缘材料构成。沉积绝缘层使得该层的厚度大约等于期望的半导体鳍宽度。在本发明的一个实施方案中,绝缘层的厚度在40nm到80nm之间。在本发明的另一个实施方案中,绝缘层的厚度是60nm。
然后,通过在绝缘层上执行各向异性蚀刻,在牺牲块的任一侧面上均形成绝缘间隔物,如框1008中所描述的那样。各向异性蚀刻以后,绝缘间隔物将保持在牺牲块的任一侧面上。绝缘间隔物的宽度将等于原始绝缘层的厚度。在本发明的一个实施方案中,绝缘间隔物是60nm宽。
在本发明的另一个实施方案中,可以形成多个牺牲块,以便形成额外的间隔物。可以使用这种方法形成具有多于2个鳍的三栅晶体管。形成的鳍的数量将等于绝缘间隔物的数量。在本发明的一个实施方案中,可以形成偶数个鳍(2N)。为了形成具有2N个鳍的三栅晶体管,需要N个牺牲块和2N个绝缘间隔物。
形成绝缘间隔物以后,可以通过常规方法去除牺牲块,如框1010中所示。例如,可以使用选择性蚀刻工艺去除牺牲块,而绝缘间隔物保持不动。
接着,通过使用绝缘间隔物作为掩模蚀刻半导体膜形成两个半导体鳍,如框1012中所示。在未被绝缘间隔物覆盖的区域中的半导体膜被蚀刻掉,暴露出绝缘衬底。形成的每一个半导体鳍均具有上表面以及一对横向相对的侧壁。使用绝缘间隔物作为掩模允许鳍被分开比使用目前的光刻技术能够获得的距离更小的距离。目前的光刻允许印刷具有接近60nm的最小尺寸的特征以及特征之间接近240nm的最小间隔。使用根据本发明的方法的实施方案,可以形成间隔小于240nm的鳍。在本发明的一个实施方案中,鳍间隔60nm或者更小的距离。
图11A到图11J示出了根据本发明的一个实施方案的双鳍三栅晶体管的形成。双鳍三栅晶体管的制造以绝缘衬底1102开始,如图11A中所示。在绝缘衬底1102上形成了硅或半导体膜1108。绝缘衬底1102可以由底下的单晶硅衬底1104和顶部的绝缘层1106构成,绝缘层1106例如二氧化硅或氮化硅膜。绝缘层1106使半导体膜1108与衬底1104隔离,并且有时候被称为“掩埋氧化物”层。半导体膜1108可以由硅或另一种半导体构成,例如但不限于锗(Ge)、锗硅合金(SixGey)、砷化镓(GaAs)、InSb、GaP、GaSb或碳纳米管。半导体膜1108可以是本征或者说不掺杂的硅膜,或者,它可以被掺杂为p型或n型导电性。半导体膜1108被形成到厚度Tsi,厚度Tsi大约等于随后形成的三栅晶体管的半导体鳍的期望高度。在本发明的一个实施方案中,半导体膜1108具有60nm或更小的厚度。
图11B示出了在半导体膜1108上表面上形成牺牲块。牺牲块可以通过常规的半导体制造技术形成,包括但不限于沉积牺牲材料层1109,并随后用抗蚀剂1111图形化该层。未被抗蚀剂1111覆盖的牺牲材料可以被蚀刻,以便在期望位置形成一个或更多个牺牲块。在本发明的一个实施方案中,牺牲材料1109由氮化物构成。要形成的牺牲块的宽度Ws将限定三栅晶体管的半导体鳍以后的间隔。在本发明的一个实施方案中,Ws是60nm或者更小。使用牺牲块允许将半导体鳍分开60nm或者更小的距离,所述距离远远小于特征之间通过常规光刻技术能够获得的距离。
图11C示出了在绝缘块1110之上和周围,以及半导体膜1108的表面之上形成绝缘层1112。在本发明的一个实施方案中,绝缘层由氧化物构成。以允许绝缘层1112以具有均匀的厚度Tox的方式来沉积该层。在随后的处理步骤中,绝缘层的厚度将决定半导体鳍的宽度。在本发明的一个实施方案中,绝缘层具有60nm或者更小的厚度。
图11D示出了绝缘间隔物1114的形成。通过在图11C的绝缘层1112上执行各向异性蚀刻来形成绝缘间隔物1114。以允许绝缘层从牺牲块的上表面被完全去除,但是留下牺牲块的任一侧面上的绝缘间隔物的方式来执行各向异性蚀刻。绝缘层1114被形成为具有宽度Wox,宽度Wox等于图11C的绝缘膜的厚度Tox。在本发明的一个实施方案中,每一个绝缘间隔物的宽度Wox是60nm或者更小。
图11E示出了去除牺牲块以后形成的结构。通过常规方法可以去除牺牲块,包括使用选择性蚀刻工艺。例如,可以使用湿法蚀刻去除牺牲氮化物块,而氧化物将保持不受蚀刻工艺的影响。去除牺牲块以后,保持两个绝缘间隔物1114,每一个间隔物具有等于Wox的宽度。间隔物间隔等于牺牲块宽度Ws的距离。
图11F示出了半导体鳍1120的形成。通过使用绝缘间隔物1114作为掩模来蚀刻半导体膜1108,形成半导体鳍1120。在本发明的一个实施方案中,蚀刻是等离子干法蚀刻工艺。半导体膜被完全蚀刻,暴露出绝缘衬底1102的表面。半导体鳍被形成为具有宽度Wsi,宽度Wsi等于被用作掩模的绝缘间隔物的宽度。在本发明的一个实施方案中,Wsi是60nm或者更小。半导体鳍间隔等于先前形成的牺牲块宽度的距离Ds。在本发明的一个实施方案中,Ds是60nm或者更小。
形成半导体鳍1120以后,可以通过常规技术去除绝缘间隔物,如图11G中所示。在此刻,两个半导体鳍1120保留在绝缘衬底1102上。半导体鳍1120具有上表面1121,以及横向相对的侧壁1123。器件总的布图宽度将等于Wsi+Ds+Wsi。在本发明的一个实施方案中,器件总的布图宽度是180nm或者更小。
图11H示出了在每一个半导体鳍1120的上表面1121以及侧壁1123上形成栅极电介质层1122。通过仔细控制半导体鳍的拐角1125的几何形状,三栅晶体管可以被设计成固有地免受Vt不稳定性影响。半导体鳍的拐角由器件相邻的栅极G1、G2和G3(顶部和侧面)的相交部分形成。因为三栅晶体管的拐角1125首先导通,所以它决定了器件的阈值电压(Vt)。当Vt仅由掺杂物质注入来设定时,掺杂物质中可能存在波动,这反过来又可能引起Vt波动。当拐角的倒圆(rounding)受到控制时,三栅晶体管不依赖于掺杂来设定Vt,因此晶体管能够被设计成固有地免受Vt不稳定性影响。半导体鳍的拐角倒圆主要源自栅极电介质形成过程。可以在硅鳍的表面和侧壁上生长或者沉积栅极电介质1122。在本发明的一个实施方案中,使用原子层沉积(ALD)来沉积栅极电介质,这允许将拐角倒圆控制到原子尺度。在本发明的一个实施方案中,半导体鳍的每一个拐角的曲率半径R小于10nm。
接着,在每一个半导体鳍的上表面和侧壁之上以及绝缘衬底之上沉积栅极材料,如图11I中所示。图形化栅极材料以便在栅极电介质层上形成栅极电极1124。
形成栅极电极以后,在栅极电极的相对侧上的每一个半导体鳍中形成一对源极/漏极区域,如图11J中所示。在本发明的一个实施方案中,如箭头1130所示,通过将N型或者P型掺杂物质注入半导体主体形成源极和漏极区域。在本发明的实施方案中,可以在三栅器件上执行进一步的操作,包括但不限于:形成尖端或源极/漏极延伸区域、晕(halo)区域、重掺杂源极/漏极接触区域、沉积在源极/漏极和栅极电极区域上的硅,以及源极/漏极和栅极电极区域上的硅化物形成。
如图11J中所示,最终的双鳍三栅晶体管的每一个半导体鳍具有等于2Tsi+Wsi的栅极宽度。双鳍三栅晶体管的栅极宽度等于每一个鳍的栅极宽度之和,或者说2(2Tsi+Wsi)。可以在具有2Wsi+Ds的布图宽度的区域中制造该器件。在本发明的一个实施方案中,双鳍三栅晶体管的栅极宽度是360nm或者更少,并且器件在具有180nm或者更小的布图宽度的区域中形成。
在本发明其他的实施方案中,可以使用上面给出的方法形成具有多于2个的半导体鳍的三栅晶体管。
Claims (16)
1.一种电路,包括:
至少一个存取器件,所述至少一个存取器件由具有单个鳍的非平面晶体管构成;
至少一个上拉器件,所述至少一个上拉器件由具有单个鳍的非平面晶体管构成;以及
至少一个下拉器件,所述至少一个下拉器件由具有多个鳍的非平面晶体管构成。
2.如权利要求1所述的电路,其中,所述至少一个下拉器件由具有两个鳍的非平面三栅晶体管构成。
3.如权利要求2所述的电路,其中,所述非平面三栅晶体管的所述两个鳍被设置成彼此间隔小于60nm。
4.一种CMOS SRAM单元,包括:
两个存取器件,每一个存取器件由具有单个鳍的三栅晶体管构成;
两个上拉器件,每一个上拉器件由具有单个鳍的三栅晶体管构成;
两个下拉器件,每一个下拉器件由具有多个鳍的三栅晶体管构成,并且,
其中,所述CMOS SRAM单元具有单元比率,静态噪声容限(SNM),以及电源电压。
5.如权利要求4所述的CMOS SRAM单元,其中,每一个下拉器件由具有两个鳍的三栅晶体管构成,所述下拉器件的每一个鳍具有高度和宽度。
6.如权利要求5所述的CMOS SRAM单元,其中,所述下拉器件的所述鳍被设置成彼此间隔小于60nm。
7.如权利要求5所述的CMOS SRAM单元,其中,所述下拉器件的每一个鳍的所述高度是60nm。
8.如权利要求5所述的CMOS SRAM单元,其中,所述下拉器件的每一个鳍的所述宽度是60nm。
9.如权利要求4所述的CMOS SRAM单元,其中,每一个三栅晶体管包含至少一个拐角,每一个拐角具有小于10nm的曲率半径。
10.如权利要求4所述的CMOS SRAM单元,其中,所述单元比率大于2.0。
11.如权利要求4所述的CMOS SRAM单元,其中,所述静态噪声容限(SNM)大于240毫伏。
12.如权利要求11所述的CMOS SRAM单元,其中,所述电源电压小于1.5伏。
13.一种CMOS SRAM单元,包括:
两个N型存取器件,每一个N型存取器件由具有单个鳍的三栅晶体管构成;
两个P型上拉器件,每一个P型上拉器件由具有单个鳍的三栅晶体管构成;
两个N型下拉器件,每一个N型下拉器件由具有多个鳍的三栅晶体管构成。
14.如权利要求13所述的CMOS SRAM单元,其中,每一个N型下拉器件由具有两个鳍的三栅晶体管构成,所述N型下拉器件的每一个鳍具有高度和宽度。
15.如权利要求14所述的CMOS SRAM单元,其中,所述N型下拉器件的所述鳍被设置成彼此间隔小于60nm。
16.一种形成六晶体管(6T)CMOS SRAM单元的方法,包括:
形成两个N型存取器件,每一个N型存取器件由具有单个鳍的三栅晶体管构成;
形成两个P型上拉器件,每一个P型上拉器件由具有单个鳍的三栅晶体管构成;
形成两个N型下拉器件,每一个N型下拉器件由具有至少两个鳍的三栅晶体管构成。
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- 2004-05-21 TW TW093114516A patent/TWI267858B/zh not_active IP Right Cessation
- 2004-09-29 KR KR1020067007629A patent/KR100915398B1/ko active IP Right Grant
- 2004-09-29 CN CNB2004800356519A patent/CN100477168C/zh not_active Expired - Fee Related
- 2004-09-29 JP JP2006534164A patent/JP2007509490A/ja active Pending
- 2004-09-29 KR KR1020087025417A patent/KR20080106978A/ko not_active Application Discontinuation
- 2004-09-29 DE DE112004001864.1T patent/DE112004001864B4/de active Active
- 2004-09-29 WO PCT/US2004/032442 patent/WO2005034212A2/en active Application Filing
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2005
- 2005-06-24 US US11/165,724 patent/US7138305B2/en not_active Expired - Fee Related
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2006
- 2006-08-21 US US11/508,009 patent/US7445980B2/en not_active Expired - Lifetime
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US6391782B1 (en) * | 2000-06-20 | 2002-05-21 | Advanced Micro Devices, Inc. | Process for forming multiple active lines and gate-all-around MOSFET |
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Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN103022036A (zh) * | 2011-09-22 | 2013-04-03 | 南亚科技股份有限公司 | 单边存取器件及其制造方法 |
CN103022036B (zh) * | 2011-09-22 | 2015-10-28 | 南亚科技股份有限公司 | 单边存取器件 |
Also Published As
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US6970373B2 (en) | 2005-11-29 |
KR100915398B1 (ko) | 2009-09-03 |
DE112004001864B4 (de) | 2014-05-22 |
TWI267858B (en) | 2006-12-01 |
US20050237850A1 (en) | 2005-10-27 |
DE112004001864T5 (de) | 2006-08-03 |
TW200514082A (en) | 2005-04-16 |
US20060281236A1 (en) | 2006-12-14 |
KR20060071429A (ko) | 2006-06-26 |
WO2005034212A2 (en) | 2005-04-14 |
JP2007509490A (ja) | 2007-04-12 |
KR20080106978A (ko) | 2008-12-09 |
CN1890798A (zh) | 2007-01-03 |
US7445980B2 (en) | 2008-11-04 |
US20050073060A1 (en) | 2005-04-07 |
US7138305B2 (en) | 2006-11-21 |
WO2005034212A3 (en) | 2005-08-04 |
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