CN100481091C - Method, module and system for dynamically updating each memory in fast photographing device - Google Patents

Method, module and system for dynamically updating each memory in fast photographing device Download PDF

Info

Publication number
CN100481091C
CN100481091C CNB2005100301762A CN200510030176A CN100481091C CN 100481091 C CN100481091 C CN 100481091C CN B2005100301762 A CNB2005100301762 A CN B2005100301762A CN 200510030176 A CN200510030176 A CN 200510030176A CN 100481091 C CN100481091 C CN 100481091C
Authority
CN
China
Prior art keywords
memory
backup
primary memory
data
write
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
CNB2005100301762A
Other languages
Chinese (zh)
Other versions
CN1940943A (en
Inventor
刘彦
周振亚
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
QIMA DIGITAL INFORMATION CO Ltd SHANGHAI
Original Assignee
QIMA DIGITAL INFORMATION CO Ltd SHANGHAI
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by QIMA DIGITAL INFORMATION CO Ltd SHANGHAI filed Critical QIMA DIGITAL INFORMATION CO Ltd SHANGHAI
Priority to CNB2005100301762A priority Critical patent/CN100481091C/en
Publication of CN1940943A publication Critical patent/CN1940943A/en
Application granted granted Critical
Publication of CN100481091C publication Critical patent/CN100481091C/en
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Abstract

A method for dynamically updating back-up storage of snapshot device includes copying write operation to master storage simultaneously to back-up storage and copying content of master storage to back-up storage by utilizing idle time of master storage. The snapshot module of static random access storage and artificial system with said module used for realizing said method are also disclosed.

Description

The method that dynamically updates, module and the system of backup of memory in the fast photographing device
Technical field
The present invention relates to the method that dynamically updates of backup static RAM in a kind of fast photographing device, be to realize dynamically updating, snapshot and simulation hardware do not disturbed simultaneously mutually carry out in conjunction with dubbing system two measures of write operation and the content of duplicating primary memory to primary memory.
Background technology
(system on a chip: SOC (system on a chip)) technology has become the development trend of current VLSI (very large scale integrated circuit) to SoC, and the function that it finishes the many chips of former cause focuses in the chip piece to be finished.But SoC is not the simple superposition of each chip functions, but from the function and the performance of total system, design and verification method with the soft or hard combination utilize IP reuse and deep sub-micron technique, realizes complicated function on a chip.Though the SoC technology can be the complicated more product of design solution efficiently is provided, and shortens the Time To Market of microelectronic product and since the SoC chip larger, function is complicated, has increased the difficulty of the simulating, verifying work in the design process.Emulation generally has software emulation and simulation hardware, and software emulation has the complete visible characteristics of circuit state, and simulation hardware has fireballing advantage.Therefore, the present checking mode that generally adopts simulation hardware to combine with software emulation is carried out.At first, utilize hardware simulation system to derive to make a mistake before a certain moment circuit state and it is imported the software emulation system; Utilize the circuit state in this moment that software emulation system utilization imports to reappear this mistake then and it is made a concrete analysis of.In this simulation hardware and the proof scheme that software emulation combines, the major part of test event is moved on hardware simulation system, near the sub-fraction in the moment of only making a mistake is moved in the software emulation system, so it has the advantage of the completeness of the high efficiency of simulation hardware and software emulation concurrently.
The process that derives a certain moment circuit state from hardware simulation system is called snapshot (hereinafter to be referred as " snapshot ").Two kinds of modes that realize snapshots are arranged at present: a kind of is that hardware simulation system only carries out a snapshot (to call single snap shot (single-snapshot) in the following text) in the process of a test event of operation, another kind be hardware simulation system in the process of a test event of operation every just carry out a snapshot (to call repeatedly snapshot (multi-snapshot) in the following text) at regular intervals.The prerequisite of single snap shot is to learn the time point that makes a mistake, and a certain appropriate moment before making a mistake is carried out snapshot.In the single snap shot scheme, if repeatedly mistake takes place in hardware simulation system in the process of a certain test event of operation, in order in the software emulation system, to reappear these mistakes one by one, will carry out snapshot in a certain moment before each wrong generation, and so just require hardware simulation system to move this test event n+1 time (n is the number of times that makes a mistake).Only need move the snapshot that test event once just can obtain a plurality of intervals certain hour if adopt repeatedly snapshot scheme, hardware simulation system.In the time will in the software emulation system, reappearing a certain mistake, as long as the snapshot in a certain moment before selecting this mistake to take place.Often a plurality of mistakes take place in large scale integrated circuit probably in the simulation process of a test event, and therefore, repeatedly the snapshot scheme is more suitable for the simulating, verifying of large scale integrated circuit.
Yet existing repeatedly snapshot scheme is to suspend simulation hardware at preset time point, carries out snapshot at this interval, and snapshot finishes the back and continues simulation hardware.Owing to suspend, therefore emulation and snapshot can not carry out simultaneously in this repeatedly snapshot scheme, so efficiency ratio is lower.
Circuit state comprises the value of register and the content of static RAM (SRAM).Realize that repeatedly the optimal mode of snapshot is to adopt back-up registers and backup static RAM memory circuit state.When not carrying out snapshot, these back-up registers and backup static RAM and register and the static RAM corresponding with tested design are consistent, freeze described back-up registers and backup static RAM before the snapshot, by sweep circuit the data in back-up registers and the backup static RAM are derived then, so just can realize that snapshot and simulation hardware carry out synchronously, be independent of each other.Because circuit state is along with the carrying out of simulation hardware ceaselessly changes, after carrying out snapshot, the value of described back-up registers and backup static RAM may be with different with the value of corresponding register of tested design and static RAM, therefore we can make the value of back-up registers and the register corresponding with tested design be consistent once more (because of utilizing a clock-unit just can rewrite the value of register) in a clock-unit, but the value of backup static RAM and the static RAM corresponding with tested design is consistent again, and this is the technological difficulties that do not influence the maximum of simulation hardware efficient when carrying out snapshot.
The paper of the postgraduate Lv Dongrong of electrical engineering research institute of Taiwan Univ.---in " A Snapshot Method toProvide Full Visibility for Functional Debugging Using FPGA " the repeatedly idea of snapshot has been proposed, but do not propose to recover the solution of backup static RAM, therefore, still can't in the design that is provided with static RAM, realize simulation hardware and carrying out synchronously of snapshot repeatedly.
Summary of the invention
Therefore, need a kind of scheme that backup static RAM and the static RAM corresponding with tested design are consistent again in the art badly, realizing that simulation hardware and snapshot repeatedly carry out synchronously, thereby further improve the simulating, verifying efficient of large scale integrated circuit.
The invention provides the method that dynamically updates of backup static RAM in a kind of fast photographing device, said method comprising the steps of:
The step that the write operation of primary memory is copied to simultaneously backup of memory;
Utilize the idle period of time of primary memory, the step of the content replication of primary memory to backup of memory.
In the method, utilize the idle period of time of primary memory that the step of the content replication of primary memory to backup of memory be may further comprise the steps as mentioned above:
A) primary memory is carried out read operation;
B) judge whether and the main memory data that is read by described read operation can be write backup of memory;
C) if the judged result of step b) is for being, then the main memory data that described read operation is read writes backup of memory, gets back to step a) then, prepares to duplicate next data;
D) if if the judged result of step b) not, then temporarily is stored in these data in the additional buffer memory;
E) step d) temporarily store data during, judge whether the address of these data of main memory store is rewritten, if, then forward step a) to, prepare to duplicate next data, if not, then forward step c) to.
In aforesaid method, during the idle period of time system of described primary memory does not operate primary memory.
The present invention also provides a kind of static RAM snapshot module, comprise primary memory, backup of memory and output module, the output terminal of backup of memory is connected with an input end of output module, it is characterized in that, described static RAM snapshot module also comprises buffer memory and control module, the input end of described buffer memory is connected with the output terminal of primary memory, the output terminal of buffer memory is connected with an input end of output module, and described control module is controlled described data in buffer locking and controlled described primary memory and the following operation of backup of memory execution:
Write operation to primary memory is copied to backup of memory simultaneously;
In the idle period of time of primary memory, the content replication of primary memory is to backup of memory.
Aforesaid static RAM snapshot module, described control module comprises the renewal control module, when described primary memory carried out write operation, described renewal control module copied to backup of memory with described write operation,
In the idle period of time of described primary memory, described renewal control module is carried out read operation to primary memory, and the data of reading are write backup of memory,
If before the write operation next time of described primary memory, described renewal control module has little time the data that obtained by described read operation are write backup of memory, and described renewal control module just temporarily is kept at these data to be upgraded in the control module,
Between the temporary transient storage life of these data, if write operation has been carried out in the address of described data in described primary memory, then described renewal control module is cancelled the replicate run of described data.
The present invention also provides a kind of hardware simulation system that comprises aforesaid static RAM snapshot module.
Description of drawings
Fig. 1 is the hardware block diagram of static RAM snapshot module of the present invention;
Fig. 2 primary memory according to an aspect of the present invention or the corresponding relation of the bank bit in backup of memory output data and the scan register;
Fig. 3 be according to an aspect of the present invention primary memory or the corresponding relation of the bank bit in backup of memory output data and the scan register, the 8th of the scanning output of wherein last static RAM snapshot module and scan register is connected;
Fig. 4 example illustrates the work schedule of static RAM snapshot module of the present invention.
Embodiment
Please join Fig. 1, static RAM snapshot module of the present invention comprises memory snapshot state machine 1, primary memory 10, backup of memory 20, upgrades control module 30, snapshot control module 40, first Multiplexing module 50, second Multiplexing module 14, scan register 60 and scanning logic module 70.Wherein, described primary memory 10 and backup of memory 20 are the static RAM of two-port (Two Port).Primary memory 10 is used for tested design, and 20 of backup of memory are used for snapshot.
Take for reducing stitch, finish the snapshot of all storeies by a scan chain, thus the snapshot output i_sram_scan_in that current static RAM snapshot module need be introduced last static RAM snapshot module with as one road snapshot output select.In addition, because the value of primary memory 10 output ports also belongs to the part of circuit state, therefore need be provided with a buffer memory 12 preserve the beginning snapshots that time primary memory 10 output ports value, lose to prevent the read operation that this value is carried out primary memory 10 along with system.The another one effect of buffer memory 12 is in upgrading the process of backup of memory 20, and the content replication of reading primary memory 10 is during to backup of memory 20, and the value of preserving primary memory 10 output ports before reading is selected to read for system.The preservation of the value of 12 pairs of primary memory 10 output ports of buffer memory is by the control signal BUF CTRL control of snapshot control module 40.The output F_Data_Out of primary memory 10 and the output of buffer memory 12 all be input to second Multiplexing module, 14, the second Multiplexing modules 14 under the control of the control signal o_sram_data_out_select of snapshot control module 40 output, select both one of as the data output o_sram_data_out of current primary memory.Simultaneously, the output of buffer memory 12 also is input to first Multiplexing module 50, selects as the output of one road, in order to the value of the output port of primary memory 10 before the output snapshot.
Comprise the output Backup_Data_Out of backup of memory 20, the output of scanning logic module 70, the output and the aforesaid i_sram_scan_in of buffer memory 12, current static RAM snapshot module has 4 circuit-switched data and selects as scanning output for output interface, and this selection is to be realized under the control of the control signal Shift_Select of snapshot control module 40 by first Multiplexing module 50.Scan register 60 and scanning logic module 70 change into output data behind the form of serial the scanning output o_sram_scan_out as current static RAM snapshot module.Scan register 60 is similar to a first in first out buffer memory.
The bit wide of supposing the system storer is 8, and the degree of depth of scan register 60 also is 8.Primary memory 10 and backup of memory 20 are corresponding connected modes of one by first Multiplexing module 50 and the annexation of scan register 60.As shown in Figure 2, when the data of one 8 of primary memory 10 or backup of memory 20 outputs (behind the sram_in_0~sram_in_7), these data of 8 just as shown the ground of a correspondence that concerns are stored in the scan register 60, scanning logic module 70 becomes the form output of serial to this data conversion by ring shift in the mode of first in first out again, and the data that back scan register 60 could receive 8 of the next ones are finished in this data serial of 8 output.The scanning of static RAM snapshot module output is serial, that is to say that (or o_sram_scan_out output) of i_sram_scan_in input is the data of serial.Be to simplify sequential control, i_sram_scan_in directly is connected with the 8th of scan register 60 by first Multiplexing module 50, as shown in Figure 3.
The present invention is as follows to the process that storer carries out snapshot scanning: at first, and the data of output buffers 12; Secondly, the content of output backup of memory 20; At last, upgrading backup of memory 20 makes it to be consistent once more with primary memory 10.Of the present inventionly focus on how upgrading backup of memory 20 and make it to be consistent once more so that carry out snapshot next time with primary memory 10.In brief, the present invention finishes renewal to backup of memory 20 in conjunction with dubbing system to the write operation of primary memory 10 and two measures of content of duplicating primary memory 10, describe in detail as after.
After finishing the snapshot of primary memory, memory snapshot state machine 1 notice snapshot control module 40 stops backup of memory 20 is carried out read operation, and snapshot control module 40 makes first Multiplexing module 50 select i_sram_scan_in to be output by the Shift_Select signal.At this moment, need to upgrade backup of memory 20 and make it to be consistent once more, so that carry out snapshot next time with primary memory 10.The measure of upgrading backup of memory 20 has two, and must could guarantee that backup of memory 20 is final and primary memory 10 is in full accord in conjunction with these two measures: the one, system is copied to backup of memory 20 to the write operation of primary memory 10, the 2nd, utilize idle period of time that primary memory 10 is from first to last carried out a read operation, and corresponding data are copied to backup of memory 20.When need not carrying out read operation to primary memory 10 in system, the read operation of primary memory 10 being carried out for the content of duplicating primary memory 10 just can carry out; Be the write operation that the content of duplicating primary memory 10 is carried out backup of memory 20, the system of needing only just can not carry out when primary memory 10 not being carried out write operation.Adopt different static RAM (as the static RAM of single port (one port) and dual-port (dual port)), just may under different opportunitys, could operate accordingly, below summarize the opportunity that can operate on it with idle period of time it.
The input signal of primary memory 10 has the address F_Read_Address and the clock ClockA/ClockB that write data F_Write_Data, primary memory 10 is carried out the enable signal F_Write_Enable of write operation, primary memory 10 is carried out the address F_Write_Address of write operation, primary memory 10 is carried out the enable signal F_Read_Enable of read operation, primary memory 10 carried out read operation of the signal CEN that activates storer, primary memory.For backup of memory 20 and primary memory 10 are consistent constantly, need copy to backup of memory 20 to system to the write operation of primary memory 10, just described F_Write_Data, F_Write_Enable, three signals of F_Write_Address be introduced the input of backup of memory correspondence.
May have two to the object that primary memory 10 carries out read operation, be respectively system and renewal control module 30.Therefore, the 3rd Multiplexing module 100 need be set to be activated the signal S_CEN of storer with selective system or upgrades the signal CEN of the signal CEN_Select of control module 30 activation storeies as activation primary memory 10, CEN_Select controls the output of the 3rd Multiplexing module 100 simultaneously and selects, and so realizes the activation control to primary memory 10.If carrying out read operation to storer, to also have two signals be essential: therefore F_Read_Enable and F_Read_Address, also need to be provided with the 4th Multiplexing module 102 and the 5th Multiplexing module 104.Two inputs of the 4th Multiplexing module 102 are respectively system primary memory 10 are carried out the enable signal S_Read_Enable of read operation and upgrades the enable signal F_Read_Select that 30 pairs of primary memorys of control module 10 carry out read operation; Two inputs of the 5th Multiplexing module 104 are respectively system primary memory 10 are carried out the address S_Read_Address of read operation and upgrades control module 30 is carried out read operation to primary memory 10 for the content of duplicating primary memory 10 address Copy_Read_Address; F_Read_Select controls the output of the 4th Multiplexing module 102 and the 5th Multiplexing module 104 simultaneously and selects.
The present invention combines dubbing system to the write operation of primary memory 10 and two measures of content of duplicating primary memory 10 to the renewal of backup of memory 20, therefore, may also have two to the object that backup of memory 20 carries out write operation: one is system, and another is to upgrade control module 30.Therefore, just may need to be provided with the 6th Multiplexing module 202, the 7th Multiplexing module 204 and the 8th Multiplexing module 206.The 6th Multiplexing module 202 has two inputs: one is F_Write_Data, and another is the output F_Data_Out (being used to duplicate the content of primary memory 10 to backup of memory) of primary memory 10.The 7th Multiplexing module 204 has two inputs: one is F_Write_Enable, and another is to upgrade the Copy_Write_Enable (duplicating the write enable signal of the content of primary memory 10 to backup of memory 20) that control module 30 provides.The 8th Multiplexing module 206 has two inputs: one is the F_Write_Address of system, and another is to upgrade the Copy_Write_Address (duplicating the address of the content of primary memory 10 to backup of memory 20) that control module 30 provides.The output of B_Write_Select signal controlling the 6th Multiplexing module 202, the 7th Multiplexing module 204 and the 8th Multiplexing module 206 that renewal control module 30 provides is selected.
Signal trend and annexation between each assembly more than have been described, the more new technological process to snapshot and backup of memory 20 describes below.When notifications memory snapshot state machine 1 begins to carry out snapshot, it is invalid that snapshot update control module 30 is changed to Copy_Write_Enable, and to select Copy_Write_Enable by B_Write_Select be the output of the 7th Multiplexing module 204, shielding is to the write operation of backup of memory 20, the content of primary memory 10 that the content that makes backup of memory 20 and system begin to carry out that time of snapshot keeps identical, the content of primary memory when promptly having locked the beginning snapshot.Buffer memory 12 also locks its value at this hour, keeps the value of primary memory 10 output ports at the moment.
When 1 pair of storer of notifications memory snapshot state machine carries out snapshot, snapshot control module 40 is by the value of Buffer CTRL lock cache 12, then be output as the output of first Multiplexing module 50, the value of output primary memory 10 output ports by Shift_Select control selection buffer memory 12; After output finishes, snapshot control module 40 is selected the output of the output Backup_Data_Out of backup of memory 20 as first Multiplexing module 50 by Shift_Select control again, and produce Backup_Read_Enable signal (enable signal that backup of memory 20 is carried out read operation) and Backup_Read_Address signal (address that backup of memory 20 is carried out read operation) and deliver to and upgrade 30 pairs of backup of memory of control module 20 and carry out read operation, the output of the content of backup of memory 20, the snapshot of current storage finishes after the content output of backup of memory 20 finishes.
Will upgrade backup of memory 20 after the snapshot of current storage finished, and make it to be consistent once more with primary memory 10, so that snapshot next time, this is emphasis of the present invention place.Notice memory snapshot state machine 1 when snapshot control module 40 learns relatively that by the address snapshot finishes, memory snapshot state machine 1 update notifications control module 30 begins backup of memory 20 is upgraded.S_CEN gives the 3rd Multiplexing module 100 simultaneously and upgrades control module 30, upgrades control module 30 like this and just knows when when system operates primary memory 10, do not operate primary memory 10.When system carries out write operation to primary memory 10, upgrade control module 30 and duplicate this write operation to backup of memory 20 by B_Write_Select, in other words, backup of memory 20 changes along with the variation of primary memory 10, therefore, as long as in the process of this variation, to backup of memory 20 both are consistent at content.Only reading of an address of static RAM needed a clock period, upgrade control module 30 and can finish a read operation at least in the idle period of time of primary memory 10, system carries out next time write operation to primary memory 10 before, have little time the data that obtained by described read operation are write backup of memory 20 if upgrade control module 30, just earlier these data are kept at and upgrade control module 30.In between the storage life of these data, if system has carried out write operation to this address of primary memory 10, because backup of memory 20 duplicated the write operation of system to primary memory 10, the value of its this address is identical with primary memory 10, therefore just cancels the replicate run of these data.Upgrade control module 30 originally comparing the system that to judge and between data retention period, whether write operation has been carried out in this address in the address primary memory 10 from address that F_Write_Address obtains and the described data that are saved.
Below in conjunction with Fig. 4 the work schedule of static RAM snapshot module of the present invention is described, wherein, S_Write_Enable represents the enable signal of writing that system sends, and F_Write_Enable is the enable signal of writing of primary memory 10, have only system to carry out write operation in the present embodiment, so S_Write_Enable is identical with F_Write_Enable to primary memory 10.In the snapshot state of phase one shown in Fig. 4 (snapshot state is dark length), the static RAM snapshot module is not carried out snapshot and renewal.Upgrading control module 30 is the input of the 4th Multiplexing module 102 and the 5th Multiplexing module 104 by F_Read_Select selection S_Read_Enable and S_Read_Address, and promptly a permission system carries out read operation to primary memory 10.Upgrading control module 30 is the output of the 6th Multiplexing module 202, the 7th Multiplexing module 204 and the 8th Multiplexing module 206 by B_Write_Select selection F_Write_Data, F_Write_Enable, F_Write_Address, and soon system copies to backup of memory 20 to the write operation of primary memory 10.When S_Read_Enable (the read operation enable signal that system provides) was effective, F_Read_Enable was effective, and system carries out read operation to primary memory 10.When F_Write_Enable was effective, B_Write_Enable was effective, and system carries out write operation to primary memory 10 and backup of memory 20.
Subordinate phase is the snapshot stage, is designated as shift-state in the snapshot state of Fig. 4.Upgrading control module 30 is the output of the 4th Multiplexing module 102 and the 5th Multiplexing module 104 by F_Read_Select selection S_Read_Enable and S_Read_Address, has only system to carry out read operation to primary memory 10.It is invalid that renewal control module 30 is changed to Copy_Write_Enable, and to select F_Data_Out (output of primary memory 10), Copy_Write_Enable, Copy_Write_Address by B_Write_Select be the output of the 6th Multiplexing module 202, the 7th Multiplexing module 204 and the 8th Multiplexing module 206, because it is invalid that Copy_Write_Enable is changed to, therefore, this moment, backup of memory 20 was frozen.System is independent of each other to the operation and the snapshot of primary memory 10, and snapshot control module 40 can be carried out read operation by upgrading 30 pairs of backup of memory of control module 20 at any time.
Phase III is the stage that backup of memory 20 is upgraded, and the snapshot state among Fig. 4 is designated as update-back-up-sram-state.In renewal process, to backup of memory 20, should dubbing system to the write operation of primary memory 10, the content that also will duplicate primary memory 10, the latter's carrying out is prerequisite (as previously mentioned) not influence the former.When system need carry out write operation to primary memory 10, upgrading control module 30 is the output of the 6th Multiplexing module 202, the 7th Multiplexing module 204 and the 8th Multiplexing module 206 by B_Write_Select selection F_Write_Data, F_Write_Enable and F_Write_Address, and dubbing system is to the write operation of primary memory 10 on backup of memory 20.First significant level of this stage F _ Write_Enable write operation that to be exactly system carry out simultaneously to primary memory 10 and backup of memory 20 among Fig. 4.When primary memory 10 is in idle period of time, upgrade control module 30 and will duplicate the content of primary memory 10 backup of memory 20.Upgrade control module 30 and select F_Read_Select and Copy_Read_Address output as the 4th Multiplexing module 102 and the 5th Multiplexing module 104 by F_Read_Select, primary memory 10 is carried out read operation, and second of this stage F _ Read_Enable significant level is exactly to upgrade the read operation that 30 pairs of primary memorys of control module 10 carry out among Fig. 4.As if the idle period of time long enough, and then this read operation, upgrade control module 30 B_Write_Enable is changed to significant level, and by B_Write_Select selection F_Data_Out, Copy_Write_Enable, Copy_Write_Address is the 6th Multiplexing module 202, the output of the 7th Multiplexing module 204 and the 8th Multiplexing module 206, the data that obtained by described read operation are write backup of memory 20, and second of this stage B _ Write_Enable significant level is exactly to upgrade the write operation that control module 30 is carried out backup of memory 20 for the content of duplicating primary memory 10 among Fig. 4.The 3rd significant level that this stage F among Fig. 4 _ Read_Enable occurs is to upgrade the read operation that 30 pairs of primary memorys of control module 10 carry out, but follow hard on the end of this F_Read_Enable significant level, the significant level that S_Write_Enable occurred, this illustrative system will carry out write operation to primary memory 10, because this write operation will be copied to backup of memory 20 equally, so the data of being read from primary memory 10 by renewal control module 30 have little time to write backup of memory 20, these data temporarily are updated control module 30 preservations and (for example are stored in the additional memory module, not shown), in system primary memory 10 and backup of memory 20 are carried out in the process of write operation, upgrading control module 30 originally compared at the address in primary memory 10 address and the described data that are saved that F_Write_Address provides, if have in the address that provides of F_Write_Address one identical with this address, just represent that the data of primary memory 10 these addresses are rewritten by system, and backup of memory 20 is because duplicated the write operation of system to primary memory 10, the data of its this address are consistent with the data of primary memory 10 these addresses, for duplicating the write operation cancellation of these data.Otherwise, then should write backup of memory 20 to these data to the write operation of primary memory 10 back that finishes in system, the 4th significant level that this stage B among Fig. 4 _ Write_Enable occurs is exactly the operation that these data is write backup of memory 20.
Wherein, what deserves to be explained is, can be restricted to the content of duplicating primary memory 10 carries out when S_CEN is invalid the behaviour that writes of backup of memory 20, also can only limit its when F_Write_Enable is invalid (its scope is bigger than the former) and carry out, the embodiment of the invention adopts the latter to describe.But thought of the present invention can be applicable to the former equally simply.
In the present embodiment, though relation and the signal described between the various modules in the mode of separate module move towards, but, as known to those skilled in the art, for example can be incorporated in the functional module upgrading control module 30, snapshot control module 40 and memory snapshot state machine, memory control module for example is to the read-write of storer and duplicate with snapshot and control.Also can be incorporated into buffer memory 12, first Multiplexing module 50, second Multiplexing module 14, scan register 60 and scanning logic module 70 in the functional module and realize, for example the storer output module.It is the common technology means of this area that these equivalences are replaced, and all should be considered as within the scope of the present invention.

Claims (6)

1. the method that dynamically updates of backup static RAM in the fast photographing device said method comprising the steps of:
Write operation to primary memory is copied to simultaneously the step of backup static RAM;
Utilize the idle period of time of primary memory, the step of the content replication of primary memory to the backup static RAM.
2. method according to claim 1 is characterized in that, utilizes the idle period of time of primary memory that the step of the content replication of primary memory to the backup static RAM be may further comprise the steps:
A) primary memory is carried out read operation;
B) judge whether the main memory data that is read by described read operation has enough time to write the backup static RAM;
C) if the judged result of step b) is for being, then the main memory data that described read operation is read writes the backup static RAM, gets back to step a) then, prepares to duplicate next data;
D) if if the judged result of step b) not, then temporarily is stored in these data in the additional buffer memory;
E) step d) temporarily store data during, whether judgement has carried out write operation to the address of these data of main memory store, if, then forward step a) to, next data are duplicated in preparation, if not, then these data are write the backup static RAM, get back to step a) then, prepare to duplicate next data.
3. method as claimed in claim 1 or 2 is characterized in that, during the idle period of time system of described primary memory does not carry out any operation to primary memory.
4. static RAM snapshot module, comprise primary memory, backup of memory and output module, the output terminal of backup of memory is connected with an input end of output module, it is characterized in that, described static RAM snapshot module also comprises buffer memory and control module, the input end of described buffer memory is connected with the output terminal of primary memory, the output terminal of buffer memory is connected with an input end of output module, and described control module is controlled described data in buffer locking and controlled described primary memory and the following operation of backup of memory execution:
Write operation to primary memory is copied to backup of memory simultaneously;
In the idle period of time of primary memory, the content replication of primary memory is to backup of memory.
5. static RAM snapshot module as claimed in claim 4 is characterized in that described control module comprises the renewal control module, and when described primary memory carried out write operation, described renewal control module copied to backup of memory with described write operation,
In the idle period of time of described primary memory, described renewal control module is carried out read operation to primary memory, and the data of reading are write backup of memory,
If before the write operation next time of described primary memory, described renewal control module has little time the data that obtained by described read operation are write backup of memory, and described renewal control module just temporarily is kept at these data to be upgraded in the control module,
Between the temporary transient storage life of these data, if write operation has been carried out in the address of described data in described primary memory, then described renewal control module is cancelled the replicate run of described data.
6. hardware simulation system that comprises as claim 4 or 5 described static RAM snapshot module.
CNB2005100301762A 2005-09-29 2005-09-29 Method, module and system for dynamically updating each memory in fast photographing device Expired - Fee Related CN100481091C (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
CNB2005100301762A CN100481091C (en) 2005-09-29 2005-09-29 Method, module and system for dynamically updating each memory in fast photographing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
CNB2005100301762A CN100481091C (en) 2005-09-29 2005-09-29 Method, module and system for dynamically updating each memory in fast photographing device

Publications (2)

Publication Number Publication Date
CN1940943A CN1940943A (en) 2007-04-04
CN100481091C true CN100481091C (en) 2009-04-22

Family

ID=37959120

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2005100301762A Expired - Fee Related CN100481091C (en) 2005-09-29 2005-09-29 Method, module and system for dynamically updating each memory in fast photographing device

Country Status (1)

Country Link
CN (1) CN100481091C (en)

Also Published As

Publication number Publication date
CN1940943A (en) 2007-04-04

Similar Documents

Publication Publication Date Title
CN104166566B (en) A kind of FPGA configuration file upgrade method and system
CN101960430B (en) Hybrid non-volatile memory
US5781558A (en) Diagnostic memory access
CN100440155C (en) Method and apparatus for creating a virtual data copy
US5568380A (en) Shadow register file for instruction rollback
KR100204027B1 (en) Database recovery apparatus and method using nonvolatile memory
CN100418062C (en) Copy controller and method thereof
US7293146B1 (en) Method and apparatus for restoring a corrupted data volume
US7769577B2 (en) Hardware accelerator with a single partition for latches and combinational logic
US6216241B1 (en) Method and system for testing multiport memories
KR101044169B1 (en) Memory rewind and reconstruction for hardware emulator
CN105159818A (en) Log recovery method in memory data management and log recovery simulation system in memory data management
CN102360302A (en) On-line upgrading method and device of configuration file of field-programmable gate array (FPGA)
CN107562578B (en) Snapshot creating method, device, equipment and storage medium for stored data
JP3290548B2 (en) Logic simulator using hierarchical checkpoints
KR20060123460A (en) Maintaining consistency for remote copy using virtualization
CN111679794A (en) Method and device for data synchronization in multi-control storage system
CN110109682A (en) Electronic Accounting Machine Unit and method
CN100481091C (en) Method, module and system for dynamically updating each memory in fast photographing device
US5132973A (en) Testable embedded RAM arrays for bus transaction buffering
CN101114527A (en) Semiconductor device
US5339320A (en) Architecture of circuitry for generating test mode signals
CN113190241B (en) Method and device for expanding capacity of data partition, electronic equipment and storage medium
CN106339282B (en) A kind of information storage system and program burn writing and program start-up loading method
US7143322B2 (en) Arrangement and method of testing an integrated circuit

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
C14 Grant of patent or utility model
GR01 Patent grant
C17 Cessation of patent right
CF01 Termination of patent right due to non-payment of annual fee

Granted publication date: 20090422

Termination date: 20110929