CN100490123C - Making technology method for flash memory - Google Patents

Making technology method for flash memory Download PDF

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Publication number
CN100490123C
CN100490123C CNB2006101174311A CN200610117431A CN100490123C CN 100490123 C CN100490123 C CN 100490123C CN B2006101174311 A CNB2006101174311 A CN B2006101174311A CN 200610117431 A CN200610117431 A CN 200610117431A CN 100490123 C CN100490123 C CN 100490123C
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Prior art keywords
floating boom
flash memory
oxide
making technology
technology method
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CN101170082A (en
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杨斌
龚新军
李铭
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Shanghai IC R&D Center Co Ltd
Shanghai Huahong Grace Semiconductor Manufacturing Corp
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Shanghai Hua Hong NEC Electronics Co Ltd
Shanghai Integrated Circuit Research and Development Center Co Ltd
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Abstract

The invention discloses a flash memory manufacturing process method. In the prior flash memory process steps, after floating boom polycrystalline deposition, the floating boom surface generates a layer of a thin oxide film with the thickness of 20-50. The invention can effectively control the beak shape with partial oxidization, expand process window and is good for floating boom sharp corner control, stability, evenness and the whole chip erasing performance improvement.

Description

Making technology method for flash memory
Technical field
The present invention relates to a kind of semiconductor integrated circuit technique method, be meant a kind of making technology method for flash memory especially.
Background technology
Flash memory is as a kind of main non-volatility memorizer, it has purposes widely in fields such as smart card, microcontrollers, compare with another kind of non-volatility memorizer EEPORM, flash memory has the advantage on the tangible area, but the reliability of flash memory, especially erasable number of times simultaneously,, poorer than EEPROM, therefore in products such as bank card, the ID card, be not used yet.
SST type flash memory is by a kind of flash type (U.S. Patent number 5029130) of Bing Yeh in nineteen ninety invention, the structure of its memory cell as shown in Figure 1, wherein, polycrystalline one is a floating boom, is 80~90 below
Figure C200610117431D0003105133QIETU
Thick floating boom grid oxygen; The part of polycrystalline two is covered on floating boom, and the control gate when wiping between control gate and the floating boom for thickness is Tunnel oxide; A part is covered on active area, is below
Figure C200610117431D00032
Thick high-pressure gate oxide, a transistor of formation and floating boom transistor series, this part is called as the branch grid.
The main processes of this flash memory is as follows: 1. isolated area/active area forms; 2. high voltage transistor, the memory cell trap injects; 3. floating boom gate oxidation
Figure C200610117431D00033
The floating boom polycrystalline deposition (1000~
Figure C200610117431D00034
); 5. silicon nitride deposition. (Si3N4); 6. floating boom selective oxidation; 7. floating boom etching; 8. the residual oxide layer wet etching is clean; 9. high-pressure gate oxide/tunnel oxide forms
Figure C200610117431D00035
10. subsequent steps comprises that with conventional low pressure MOS technology the low voltage transistor trap injects, the low pressure gate oxidation, and polycrystalline two deposits, LDD injects, abutment wall forms, injection etc. is leaked in the source.
In the process of above-mentioned floating boom selective oxidation, the polycrystalline silicon surface is by local opening, oxidized subsequently, form selective oxidation (LOCOS) shape, utilize oxide-film to do mask again and carry out the autoregistration etching, being deformed into SST type flash memory floating gate edge point type structure thus. wiping of it is pressure drop by between control gate and floating boom, utilizes the Fowler-Nordheim tunneling effect, makes electronics see through tunnel oxide and flows to control gate from floating boom.And the angle of wedge angle is more little, and then the electric field strength at the tip is just big more, and it is also just easy more to wipe, thereby the performance of wiping of memory cell is improved.Because the formation of wedge angle realizes by a lot of processing steps, and the performance of wiping of entire chip is to be decided by the most weak memory cell.
Therefore, in this technical field, need a kind of making technology method for flash memory, can effectively control the beak shape of selective oxidation (Mini-LOCOS), enlarge process window, help the control and the stability, uniformity of floating boom wedge angle, help the simplification of subsequent technique, improve the wiping/writing performance of entire chip.
Summary of the invention
The technical problem to be solved in the present invention provides a kind of making technology method for flash memory, and it can effectively control the beak shape of selective oxidation, improves the wiping/writing performance of chip simultaneously.
For solving the problems of the technologies described above, making technology method for flash memory of the present invention may further comprise the steps: in the 1st step, isolated area/active area forms; The 2nd step, high voltage transistor, the memory cell trap injects; In the 3rd step, the floating boom gate oxidation forms the floating boom gate oxide; The 4th step, the floating boom polycrystalline deposition; The 5th step, silicon nitride deposition; The 6th step, the floating boom selective oxidation; The 7th step, the floating boom etching; In the 8th step, the residual oxide layer wet etching is clean; In the 9th step, high-pressure gate oxide/tunnel oxide forms, and wherein, increases between the 4th step and the 5th step: floating boom superficial growth one deck thin oxide film.
The thickness of described thin oxide film is
Figure C200610117431D00041
The present invention utilizes at the thin heat oxide film of floating boom superficial growth one deck, be applied to the Mini-LOCOS technology of SST type flash memory, thickness that can fine controlled oxidation film, can effectively control the beak shape of Mini-LOCOS, enlarge process window, help in the control and raising silicon chip of floating boom wedge angle, in same batch, and the stability, uniformity between the different batches, help the simplification of subsequent technique, improve the wiping/writing performance of entire chip, other devices are influenced little simultaneously, help the simplification of subsequent technique, the reduction of cost.
Description of drawings
Below in conjunction with accompanying drawing and embodiment the present invention is described in further detail:
Fig. 1 is the structural representation of flash memory cell;
Fig. 2 is conventional floating boom location oxidation of silicon process schematic diagram;
Fig. 3 is a floating boom location oxidation of silicon process schematic diagram of the present invention.
Embodiment
The main technique step that the present invention adopts is as follows: 1. isolated area/active area forms (with existing technology); 2. high voltage transistor, memory cell trap inject (with existing technology); The floating boom gate oxidation (with existing technology,
Figure C200610117431D00051
); The floating boom polycrystalline deposition (with existing technology,
Figure C200610117431D00052
); 5. the oxide-film that growth one deck is thin earlier on the floating boom surface approximately
Figure C200610117431D00053
6. silicon nitride deposition; 7. floating boom selective oxidation (with existing technology); 8. floating boom etching (with existing technology); 9. subsequent steps is also as existing technology.
The present invention compares with existing technology: step 1~4 are with existing technology, behind the floating boom gate oxidation, at surface deposition one deck polysilicon; Add process afterwards one, promptly play thickness and be at polysilicon surface growth one deck
Figure C200610117431D00054
Oxide-film; The step that continues is identical as original processing step, at floating boom superficial growth one deck silicon nitride; Secondly, to the local windowing of floating boom and carry out oxidation, as shown in Figure 3; Afterwards floating boom is carried out the autoregistration etching.
Since at the very thin oxide-film of floating boom superficial growth one deck, therefore, when the floating boom selective oxidation, just can form beak to a certain degree, by the thickness of controlled oxidation film, the size of may command beak and shape.
Consider the characteristics of etching technics, change less zone if can form one section wedge angle angle on the floating boom surface, just can improve the process window of floating boom autoregistration etching, reduced the influence degree that wedge angle is subjected to subsequent technique simultaneously, improved the uniformity of memory cell wedge angle, the performance of wiping of whole flash memory is improved.

Claims (2)

1, a kind of making technology method for flash memory may further comprise the steps: in the 1st step, isolated area/active area forms; The 2nd step, high voltage transistor, the memory cell trap injects; In the 3rd step, the floating boom gate oxidation forms the floating boom gate oxide; The 4th step, the floating boom polycrystalline deposition; The 5th step, silicon nitride deposition; The 6th step, the floating boom selective oxidation; The 7th step, the floating boom etching; In the 8th step, the residual oxide layer wet etching is clean; In the 9th step, high-pressure gate oxide/tunnel oxide forms, and it is characterized in that: increase between the 4th step and the 5th step: floating boom superficial growth one deck thin oxide film.
2, making technology method for flash memory as claimed in claim 1 is characterized in that: the thickness of described thin oxide film is
Figure C200610117431C00021
CNB2006101174311A 2006-10-23 2006-10-23 Making technology method for flash memory Active CN100490123C (en)

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CN100490123C true CN100490123C (en) 2009-05-20

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN102136481B (en) * 2010-01-25 2013-03-13 上海华虹Nec电子有限公司 Manufacture method of EEPROM (Electronically Erasable Programmable Read-Only Memory) device
CN108257962A (en) * 2016-12-29 2018-07-06 无锡华润上华科技有限公司 Flash memory storage structure and its manufacturing method
CN109216362B (en) * 2017-06-30 2021-01-05 无锡华润上华科技有限公司 Flash memory and preparation method thereof
CN110957370B (en) * 2019-12-27 2022-08-23 杰华特微电子股份有限公司 Method for manufacturing lateral double-diffused transistor

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Patentee before: Shanghai Huahong NEC Electronics Co., Ltd.

Patentee before: Shanghai integrated circuit research and Development Center Co., Ltd.