CN100492595C - 处理半导体衬底的方法 - Google Patents

处理半导体衬底的方法 Download PDF

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CN100492595C
CN100492595C CNB2005800203772A CN200580020377A CN100492595C CN 100492595 C CN100492595 C CN 100492595C CN B2005800203772 A CNB2005800203772 A CN B2005800203772A CN 200580020377 A CN200580020377 A CN 200580020377A CN 100492595 C CN100492595 C CN 100492595C
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CN1973362A (zh
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戴维·P.·曼西尼
杨·纯
威廉·J·道克什
唐纳德·F·韦斯顿
斯蒂文·R·杨
罗伯特·W·拜尔德
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NXP USA Inc
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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/3065Plasma etching; Reactive-ion etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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    • Y10STECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00Semiconductor device manufacturing: process
    • Y10S438/977Thinning or removal of substrate

Abstract

根据具体实施方式,公开了一种处理半导体衬底的方法,从而减薄衬底,并且通过普通的工艺将衬底上形成的小片分成单个。在衬底的背侧上形成沟槽区(42、43)。对背侧的各向异性蚀刻导致了衬底减薄同时保持沟槽深度,从而便于将管芯分成单个。

Description

处理半导体衬底的方法
技术领域
本公开内容涉及一种半导体器件,更具体地涉及一种关于降低半导体器件厚度的方法。
背景技术
试验研究和计算机模型已经证明,可通过减薄半导体管芯来改善半导体器件的性能。最通常用于减薄管芯的方法是在管芯锯切和分成单个(singulation)之前进行的背面研磨工序。然而,单独研磨在包括机械力的芯片或破坏半导体晶片之前仅提供那么多的管芯减薄。此外,在背面研磨工艺之后,使用锯切或划片技术将晶片上形成的各个管芯分成单个。在将管芯分成单个的分离工艺中,尤其是当其处于被减薄状态中时,存在导致对管芯进一步损伤的可能性。因此,克服该问题的方法是有用的。
发明内容
根据本发明的一个方面,提供一种方法,包括:在半导体衬底背侧上形成掩模层;在掩模层中形成沟槽区,掩模层中的沟槽区限定了将由半导体衬底形成的小片的位置;在形成沟槽区之后,蚀刻掩模层和半导体衬底以同时移除掩模层和在半导体衬底中形成沟槽区;和在蚀刻掩模层之后,从半导体衬底的背侧蚀刻以同时减薄半导体衬底并将半导体衬底分成多个管芯。
根据本发明的另一方面,提供一种方法,包括:在具有第一厚度的半导体衬底背侧中形成沟槽区;和在形成沟槽区之后,从半导体衬底的背侧蚀刻,以便由半导体衬底形成所需厚度的多个管芯,其中所需厚度小于第一厚度。
根据本发明的再一方面,提供一种方法,包括:蚀刻半导体衬底的背侧表面以减薄对应于管芯位置的至少一部分半导体衬底;和在蚀刻背侧表面期间,暴露将在管芯位置处形成的管芯侧壁部分。
附图说明
通过参考附图,可更好地理解本公开内容,并且其大量特征及优点对于本领域技术人员是明显的。
图1-11说明根据本公开内容在减薄半导体衬底中包括的各个步骤的截面图。
图12说明根据本公开内容的具体实施方式在衬底上的沟槽区位置。
在不同附图中使用相同的参考符号表示相似或相同的项。
具体实施方式
根据本公开内容的具体实施方式,公开了一种处理半导体衬底的方法,从而在普通的工艺期间同时减薄并切片(分成单个)衬底。在一个实施方式中,使用标准光刻工艺结合背侧对准技术,在衬底的背侧上形成掩模层,如具有开口沟槽区的光致抗蚀剂或其它可图形化有机层。典型地,沟槽区被对准到衬底的前侧上限定的划片栅格区。应用于背侧的各向异性蚀刻将沟槽区的图形转移到衬底的背侧上。在移除掩模层之后,通过蚀刻消耗或剥离,进行衬底背侧的蚀刻以在背侧表面上均匀地减薄晶片。同时蚀刻构成背侧最深部分的沟槽区,并保持背侧最深部分贯穿。在将晶片分成单个管芯时,通过蚀刻减薄衬底持续进行直到沟槽区穿通到前侧。在耗尽或移除掩模层时,即在开始体晶片蚀刻时,沟槽深度确定了最终管芯的最大厚度。通过参考图1-12,将更好理解本公开内容的具体实施方式。
图1说明包括半导体衬底10并具有两个平行的主表面12和14以及形成两个主表面12和14之间的边缘的次表面的工件31的截面图。次表面或边缘形成工件31的周边。为了参考目的,主表面14也称作前面、前侧或有源表面14,以表示这是具有形成操作器件的有源区的表面。参照主表面12相对于前面的有源表面14的位置,还将该主表面称作衬底的背面12、背侧。参考数字21表示工件31的厚度。在一个实施方式中,厚度21表示与在处理有源表面14以形成操作器件期间的衬底10基本上相同的厚度。衬底10的示范性厚度约26密尔(660.4微米),尽管可使用将需要被减薄的任意工件厚度。
衬底10典型地是硅或砷化镓晶片,但是也可以是锗掺杂层、外延硅、绝缘体上的硅(SOI)衬底或者适合于形成半导体器件的任意相似衬底。
图2说明在被减薄以形成具有厚度211的工件32之后的衬底10。在具体实施方式中,研磨机械背面研磨工艺已经通过将一种或多种磨料应用到衬底10的背侧减薄了衬底10,以获得所需的中间厚度211。衬底10的厚度211受到减薄的衬底材料的机械强度极限的限制,这使得衬底更加容易受到连续机械减薄工艺的影响而破裂。典型地,厚度211在4-10密尔的范围内,然而,厚度211可表示需要另外减薄的任意厚度的衬底。例如,对较厚或较薄衬底进行图3-10中描述的随后处理。
图3说明具有在工件32的衬底10背侧上形成的掩模层16的工件33。掩模层16可由照射敏感材料或非照射敏感材料形成,或者可包括多层。使用光刻领域中非常公知的图形化掩模(未示出)即光掩模、或使用背面对准技术的直接照射技术即e束或激光,这有利于在掩模层16中形成沟槽区41,以对准沟槽区41的位置和工件的前侧,从而在直接在划片区上形成沟槽区41。
在一个实施方式中,掩模层16由具有典型地在0.25到25微米范围内厚度的光致抗蚀剂材料形成,其它厚度范围为1-2微米、1-4微米、0.75-1.25微米、0.5-1.5微米和0.5-3微米,且典型的厚度约为1微米。当掩模层16为光致抗蚀剂层时,通过使用光刻技术将沟槽41形成到光致抗蚀剂材料中。在另一实施方式中,掩模层16由硬掩模材料即非照射敏感材料形成,且在蚀刻掩模层16期间,使用独立的掩模层(未示出)如光致抗蚀剂层对其进行蚀刻,以限定沟槽区41的位置。硬掩模材料可以是提供蚀刻阻挡的任意材料。硬掩模材料可包括有机材料、氧化硅、氮化硅、碳化硅或金属如铝、钨、钛,或其组合。
图12说明具有表示划片栅格位于有源表面14上的位置的栅格位置411的衬底的平面图。在器件46之间形成这些划片区,且划片区位于典型地进行切割和划片以将管芯相互分开单个的位置处。划片区宽度典型地约为20-100微米,从而基于对准精确度利于形成稍小于该范围的沟槽41的宽度。将理解,根据本公开内容的具体实施方式,器件46可以是除了矩形之外的形状如圆形,或者是具有圆形边缘的器件,并且切片线可以是任意所需图形,且跨过衬底表面可以形成或不形成不中断的通道。
在图4中说明工件33的部分110(图3)的放大图。图4的放大图说明完全穿过掩模层16蚀刻沟槽区41以暴露部分衬底10,或者可部分穿过掩模层16形成沟槽41,如到达由虚线141示出的位置处。部分穿过掩模层16到达位置141形成的沟槽可通过使用各种技术获得。例如,当掩模16由单种材料类型形成(即,区域161和162是相同的硬掩模材料)时,典型地使用计时蚀刻。当使用多层掩模时可使用选择以停止在下部层161上的蚀刻,即,层162下部的层161由不同的材料形成。使用通过检测终点控制的蚀刻,如当层161表示在表示所需沟槽深度141的深度处形成的可检测层。将理解,可使用光学质谱仪或者其它标准或专用检测技术来进行终点检测。
图5说明通过蚀刻工艺62在掩模层16和衬底10的背侧中形成的沟槽42,以形成工件34。在一个实施方式中,蚀刻62对掩模层16基本上是选择性的,从而以比掩模层16大的速率蚀刻衬底10。例如,当掩模层16是光致抗蚀剂材料时,使用公知为Bosch或深度硅蚀刻的工艺对于掩模层16优选蚀刻衬底10。该蚀刻工艺的结果是,将在图3中形成的沟槽转移到衬底中,如图5中示出。在形成了在衬底10中具有所需深度的沟槽区42之后,在图6的蚀刻工艺63过程期间移除掩模层16,这形成了具有于衬底10中形成的沟槽区43的工件35而无需硬掩模16。例如,当掩模层16是光致抗蚀剂材料时,一旦沟槽区在衬底10中达到所需深度,就使用氧等离体的蚀刻工艺或便于剥离或灰化光致抗蚀剂的蚀刻,以移除光致抗蚀剂掩模层。
在替代实施方式中,在消耗掩模层16的蚀刻期间同时形成工件35的沟槽区43。例如,蚀刻62(图5)形成了中间工件34,其中掩模层16已经被部分消耗并且沟槽区43仅部分形成;且图6的蚀刻63表示蚀刻62的继续,并说明在已经通过蚀刻工艺63完全消耗即移除了掩模层16并且已经完全形成了沟槽区43时的工件35。在一个实施方式中,掩模层16的厚度允许在衬底中形成沟槽区43和使用深度蚀刻工艺如Bosch蚀刻完全消耗掩模层同时进行。
典型的Bosch蚀刻工艺基于反复沉积(例如使用C4H8)和蚀刻(例如SF6/O2)工艺。总之,在被蚀刻的特征上进行聚合物沉积。所施加的衬底偏置用于有利于与沿着侧壁相反在沟槽底部处移除聚合物。然后进行足够长时间的蚀刻步骤以较深地蚀刻沟槽而不穿透保护侧壁聚合物。重复沉积和蚀刻步骤直到达到所需深度。
在Bosch工艺中,使用低的衬底偏置以增强各向异性蚀刻特性。等离子体是高密度的,从而导致高的蚀刻速率并可能导致高选择性。将构成为允许很高气流的低压。
Bosch蚀刻的结果可以具有原子级光滑的粗糙度、即小于5nm的表面粗糙度的水平(主)表面,以及具有约50nm轴向变化特性(scalloping nature)粗糙度的垂直(次)表面。
在掩模层16是通过在形成沟槽43期间同时消耗来移除的光致抗蚀剂的实施方式中,掩模层16的最小厚度通过以下的等式确定。公知的变量包括衬底10的移除速率、光致抗蚀剂的移除速率和所需的管芯厚度。所需的管芯厚度通过穿过具有最小厚度的光致抗蚀剂掩模层16形成沟槽41来获得,由以下的等式确定,并且按需要在分成单个后过蚀刻。
最小掩模厚度=所需的管芯厚度*(蚀刻速率(掩模)/蚀刻速率(衬底))
由于蚀刻通过在穿过前面有源侧时停止而结束,因此最初的掩模厚度限定了分成单个时的管芯厚度。
图7是说明在通过使用中间胶粘层51附加到操作衬底52上之后的工件35。使用操作衬底52来将单独管芯支撑在原位,这是由于所公开的工艺将会将其分成单个。将理解,在将衬底10减薄到超出其则不能有效控制衬底10而不损坏的点处之前的任一时间,将操作衬底52附加到衬底10,这允许对准前侧。例如,在图3的工艺之后可增加操作衬底。
图7也说明以均匀方式继续减薄晶片的蚀刻64。蚀刻64是基本上以相同的速率或者以公知的方式蚀刻背侧的上表面和沟槽区43的底部的任一种蚀刻,从而保持沟槽区43相对于背侧12的上表面基本已知的深度。厚度211表示在减薄工艺期间衬底10的厚度。在具体实施方式中,蚀刻64是深硅蚀刻,如在此描述的Bosch蚀刻。蚀刻继续进行直到获得了所需的管芯厚度214,且将各个管芯46分成单个,如图8中所示,从而形成工件37。在具体实施方式中,所需管芯厚度低于65微米。在另一实施方式中,该厚度小于51微米。在再一实施方式中,所需的管芯厚度小于40微米。典型地,选择超薄管芯厚度以适应随后的操作和功耗要求。通过如图7中所示出的蚀刻,减薄在衬底10上的管芯位置,同时在沟槽内部暴露管芯的侧壁,直到暴露管芯的整个侧壁,见图8。
将理解,基于沟槽区43的开始深度,可精确控制最终的管芯厚度214达预定量(图6)。图6说明通过在形成沟槽区43期间的蚀刻消耗或者通过剥离全部消耗了掩模层16时的工件。在图6所表示的时间之后继续的蚀刻允许检测何时蚀刻穿过前侧。例如,通过终点检测,一旦穿透就终止蚀刻,其中,可在等离子蚀刻的等离子体中可检测到已知将在晶片前侧划片区域上发现的化学元素即终点材料。例如,在前侧划片区上可形成终点层,以提供可通过背侧蚀刻期间在等离子体中的光谱可检测的材料。检测这种“标记”元素表示已经达到了前面,或者很快将达到,并且停止蚀刻。替代地,检测标记元素或者条件随后可进行短时间蚀刻以确保分成单个。这些技术可防止不能完全穿通晶片且从而不能将小片分成单个的不完全蚀刻,和移除过多的材料并过多减薄小片的过蚀刻。
图9说明包括在小片46的背侧上方形成背面金属层11以形成小片47的工件38。背面金属层11利于随后将各个管芯47附加到封装衬底。
图10说明应用到工件38背侧上的拾取带53,从而形成工件39。在图11中,胶粘层5已经溶解,或者被移除以允许分离操作衬底52以形成工件40。
在分成单个之后,使用常规的或者专用封装技术和材料封装管芯47。例如,可使用倒装芯片技术、引线键合技术或者其组合来封装管芯。封装可以是包括陶瓷或塑料封装的任一种材料类型,以及球栅封装、引线导线封装或者任何其他封装类型。
在优选实施方式的前面详细描述中,参考作为其一部分的附图,并且附图借助于示出具体的优选实施方式示出,在具体优选实施方式中实施了本发明。以足够的细节描述了这些实施方式,以确保本领域技术人员能够实施本发明,并且应当理解,可使用其它实施方式而不脱离本发明的精神和范围。为了避免不必要的细节以使得本领域技术人员能够实施本发明,省略了本领域技术人员公知的某些信息的描述。而且,本领域技术人员结合本发明的教导可容易构造很多其它变化实施方式。因此,不希望本发明限于在此列出的具体形式,而是相反,希望涵盖这种替代、修改和等同物,正如可合理地包含在本发明的精神和范围内的那样。因此,前面的详细描述并不具有限制性意义,且本发明的范围仅通过附属的权利要求来限定。

Claims (21)

1.一种处理半导体衬底的方法,包括:
在半导体衬底背侧上形成掩模层;
在掩模层中形成沟槽,掩模层中的沟槽限定了将由半导体衬底形成的小片的位置;
在掩模层中形成沟槽之后,蚀刻掩模层和半导体衬底以同时移除掩模层和在半导体衬底中形成沟槽区;和
在蚀刻掩模层之后,从半导体衬底的背侧蚀刻以同时减薄半导体衬底并将半导体衬底分成多个管芯,
该方法还包括:在蚀刻掩模层之前,在半导体衬底前侧上附加操作衬底。
2.如权利要求1的方法,其中在掩模层中形成沟槽包括使掩模层中的沟槽与在半导体衬底前侧上形成的特征对准。
3.如权利要求1的方法,还包括:
在所述多个管芯中的管芯的背侧上形成背面金属层。
4.如权利要求3的方法,还包括:
在形成背面金属层之后,从所述多个管芯移除操作衬底。
5.如权利要求1的方法,其中从半导体衬底的背侧蚀刻包括检测蚀刻终点。
6.如权利要求5的方法,其中检测蚀刻终点包括检测在半导体衬底前侧上形成的层。
7.如权利要求5的方法,其中从半导体衬底的背侧蚀刻包括在检测蚀刻终点之后蚀刻预定时间量。
8.如权利要求1的方法,其中所述多个管芯具有小于65微米的最终厚度。
9.如权利要求1的方法,其中所述多个管芯具有小于51微米的最终厚度。
10.如权利要求1的方法,其中所述多个管芯具有小于40微米的最终厚度。
11.如权利要求1的方法,还包括在形成掩模层之前减薄半导体衬底。
12.如权利要求11的方法,其中减薄半导体衬底包括使用背面研磨工艺。
13.一种处理半导体衬底的方法,包括:
在具有第一厚度的半导体衬底背侧中形成沟槽区;和
在形成沟槽区之后,从半导体衬底的背侧进行蚀刻,以便由半导体衬底形成所需厚度的多个管芯,其中所需厚度小于第一厚度,
该方法还包括:在从半导体衬底的背侧进行蚀刻之前,在半导体衬底前侧上附加操作衬底。
14.如权利要求13的方法,其中在半导体衬底的背侧中形成沟槽区包括:
在半导体衬底背侧上形成掩模层;和
在掩模层中形成沟槽以利于在半导体衬底的背侧中形成沟槽区。
15.如权利要求14的方法,其中在半导体衬底的背侧中形成沟槽区还包括:
在掩模层中形成沟槽之后,移除掩模层,同时在衬底的背侧中形成沟槽区。
16.如权利要求15的方法,其中:
形成掩模层还包括含有光致抗蚀剂材料的掩模层;和
在掩模层中形成沟槽包括使用光刻。
17.如权利要求16的方法,其中在掩模层中形成沟槽还包括在掩模层中的具有等于掩模层厚度的深度的沟槽。
18.如权利要求13的方法,其中在半导体衬底背侧中的沟槽区与在半导体衬底前侧上形成的特征对准。
19.一种处理半导体衬底的方法,包括:
在半导体衬底前侧上附加操作衬底;
蚀刻半导体衬底的背侧表面以减薄对应于管芯位置的至少一部分半导体衬底;和
在蚀刻背侧表面期间,暴露将在管芯位置处形成的管芯侧壁部分,
其中该方法还包括:在蚀刻半导体衬底的背侧表面之前,在半导体衬底背侧中形成沟槽区。
20.如权利要求19的方法,其中暴露包括暴露管芯的整个侧壁。
21.如权利要求19的方法,其中所述至少部分半导体衬底是整个半导体衬底。
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