CN100492645C - Nonvolatile semiconductor storage device - Google Patents

Nonvolatile semiconductor storage device Download PDF

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Publication number
CN100492645C
CN100492645C CNB2004800190049A CN200480019004A CN100492645C CN 100492645 C CN100492645 C CN 100492645C CN B2004800190049 A CNB2004800190049 A CN B2004800190049A CN 200480019004 A CN200480019004 A CN 200480019004A CN 100492645 C CN100492645 C CN 100492645C
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source
drain region
column structure
conductivity
column
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CN1816913A (en
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L·弗伯斯
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Micron Technology Inc
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Micron Technology Inc
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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/10—EEPROM devices comprising charge-trapping gate insulators characterised by the top-view layout
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

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Abstract

The present invention includes floating gate transistor structures used in non-volatile memory devices such as flash memory devices. In one embodiment, a system includes a CPU and a memory device including an array having memory cells having columnar structures and a floating gate structure interposed between the structures that is positioned closer to one of the structures. In another embodiment, a memory device includes an array having memory cells having adjacent FETs having source/drain regions and a common floating gate structure that is spaced apart from the source/drain region of one FET by a first distance, and spaced apart from the source/drain region of the opposing FET by a second distance. In still another embodiment, a memory device is formed by positioning columnar structures on a substrate, and interposing a floating gate between the structures that is closer to one of the structures.

Description

Nonvolatile semiconductor memory
Technical field
The present invention relates generally to semiconductor memory, relate in particular to the floating boom transistor arrangement that in Nonvolatile semiconductor memory device such as flash memory element, uses.
Background technology
Flash memory element is highdensity nonvolatile memory device, and this device has low-power consumption, fast access time and low cost.Therefore flash memory element can be used for multiple portable electron device satisfactorily, and these electronic installations require highdensity memory, but because the high power consumption of these devices or additional weight and can not support disc driver or other mass storage device.An additional advantage of flash memory storage is that it provides online programmability.Therefore when device resides on the circuit board of electronic installation, can under software control, programme again to flash memory element.
Fig. 1 is the flash memory cell 10 according to prior art.Flash memory cell 10 has metal-oxide semiconductor (MOS) (MOS) structure, and this structure comprises substrate 12, pair source 14, at floating boom on the MOS channel region 16 18 and the control gate on floating boom 18 20.Oxide structure 22 is separated floating boom 18 and channel region 16, also floating boom 18 and control gate 20 is separated.For shown in device, the p type impurity that mixed in the substrate 12, and the N type impurity that mixed in source/drain region 14.
By enough positive gate voltage V CGWith positive drain voltage V DPut on device 10, keep source voltage V simultaneously SBe zero or earth potential, can programme memory cell 10.When electric charge from source/drain region 14 when moving to floating boom 18, device 10 reaches logic state " 0 ".On the other hand, if having less electric charge or do not have electric charge, then the logic state corresponding to " 1 " is stored on the device 10 at floating boom 18 places.
The positive voltage V of pre-determined amount CGPut on control gate 18, keep V simultaneously DFor just, come the state of read-out device 10.Be enough to make device 10 conductings if put on the voltage of control gate 18, then can flow to another source/drain region 14 from a source/drain region 14 by the detected electric current of other external circuit, so presentation logic state " 1 ".Correspondingly, if floating boom 18 places exist enough electric charges to stop device 10 conductings, then read logic state " 0 ".By positive source voltage V SPut on source/drain region 14 and keep V simultaneously CGBe negative potential, can wipe the logic state of device 10.Device 10 reaches logic state " 1 " and has followed an erase cycle.
Though above-mentioned flash memory cell 10 is extremely effective for logic states in storage component part, observes, the programming efficiency of memory cell 10 reduces with the increase of the number of times of the program/erase cycle that is accumulated.As a result, after number of times value of overstepping the extreme limit of program/erase cycle, memory cell 10 can lose efficacy, and the term of this limiting value is the fatigue limit of memory cell 10.Though fatigue limit is quite unessential in only to memory cell 10 programmings situation once, device 10 is being wiped and again in the programming situation many times, fatigue limit is must consideration.The reduction of believing programming efficiency is owing to hot electron causes, during programming cycle, these hot electrons become in the quite thin oxide skin(coating) that is trapped in separation floating boom 18 and substrate 12, and this has permanently destroyed oxide skin(coating).In addition, produce extremely strong electric field strength during erase cycle, this becomes the hole with quite low momentum and is trapped in the oxide skin(coating) of separating floating boom 18 and substrate 12.When memory cell 10 stands the program/erase cycle of repetition, in oxide skin(coating), accumulate the hole of being held back, the electric field that therefore causes applying between reading duration reduces.
Qualitative influence in the reduction of flash memory cell 10 shown in Fig. 2-4.Fig. 2 to the performance of acyclic flash memory cell 10 and stood quite a lot of number of times wipe with program cycles after the performance of memory cell 10 compare.As shown in FIG. 2, for comparable fixedly control gate pole tension V CG, the source/drain current I of memory cell 10 through circulating DSTo reduce widely than the source/drain current that obtains from acyclic memory cell 10.As a result, because the reduction of the source/drain current in the memory cell 10 through circulating, to the negative effect that defines of the logic state during readout interval.Fig. 3 further illustrates this influence, wherein observes the source/drain current I of memory cell 10 DSReduce steadily with the accumulation of memory cell 10 cocycle number of times.The fatigue limit that Fig. 3 also illustrates memory cell 10 may occur in about 10 5With 10 6Between the inferior circulation.
The threshold voltage V of memory cell 10 when Fig. 4 illustrates the increase of program/erase cycle number of times TVariation.Definition threshold voltage V TFor during readout interval, making the needed minimum voltage of memory cell 10 conductings.In Fig. 4, V T, 1Corresponding to when to the charging of the floating boom of memory cell 10 (presentation logic state " 0 ") make the needed threshold value of memory cell 10 conductings, and V T, 2Corresponding to when not to the charging of the floating boom of memory cell 10, making the needed threshold value of memory cell 10 conductings.So V T, 1And V T, 2Difference definition threshold voltage " window " between the value, as shown in FIG. 4.When memory cell 10 stands circulation time, " window " diminishes gradually, so that being stored in to become between two logic states in the memory cell 10 and more being difficult to distinguish.
A prior art solution for above-mentioned fatigue limit problem is a kind of flash memory cell, this flash memory cell has the asymmetric floating boom in source electrode position, control gate is on floating boom, but also directly on the channel region of memory cell, as in being entitled as of people such as P.Pavan " Flash Memories-AnOverview " (IEEE Proceedings, 85 volumes, 8 phases, 1248-1271 pages, 1997) paper in institute at length disclose.Because programming and erase feature occur in a part of channel region of contiguous source electrode, so be limited in only a part of channel region for the destruction of gate oxide.Though above-mentioned flash memory cell configuration obtains the raising of some fatigue limits, it is excessive that the destruction of the oxide skin(coating) above the floating boom becomes significantly, so that no longer may read the logic state that is stored in the memory cell muchly.
Another kind of prior art flash memory cell comprises the source area that N one district centers on, the influence of the big electric field strength that takes place when making it not to be subjected to eraseable memory unit with the source junction of further protection memory cell.A great shortcoming in this configuration is to exchange the durability that source region and drain region enlarge memory cell.In addition, asymmetric configuration has increased the total manufacturing cost of flash memory element.
Therefore, needing to have the flash memory element that strengthens fatigue limit in the art.
Summary of the invention
The present invention is directed to system, equipment and method, be used to form the floating boom transistor arrangement that in Nonvolatile semiconductor memory device such as flash memory element, uses.In one aspect, system can comprise CPU (CPU), and the storage component part that is coupled to processor, this device comprises having array of memory cells, each memory cell comprises first column structure and second column structure that separates, have be inserted between first column structure and second column structure and with the first and second structure spaced floating gates structures.In yet another aspect, storage component part comprises the array of memory cells with first and second opposite field effect transistors (FET), described field-effect transistor have separately source/drain region and common floating gate structure, source/drain region of a floating gate structure that this is common and a FET separates first distance, and separates second distance with source/drain region of the 2nd FET.Of the present invention aspect another, a kind of method of storage component part that formation has a memory cell of a plurality of interconnection is included in places first column structure on the substrate, on substrate, place second column structure that separates with first column structure, between first structure and second structure, form grid structure; And being inserted in floating gate structure between first structure and the grid structure and between second structure and the grid structure, the position of floating gate structure is near in first structure and second structure selected one.
Description of drawings
Fig. 1 is the sectional view according to the flash memory cell of prior art.
Fig. 2 is curve chart circulation and the qualitative comparison source/drain current performance of acyclic flash memory cell.
Fig. 3 is a curve chart, illustrates that qualitatively source/drain current performance reduces with the increase of flash memory cell cycle-index.
Fig. 4 is a curve chart, and the voltage threshold window that flash memory cell is described qualitatively narrows down with the increase of cycle-index.
Fig. 5 is the block diagram of computer system 100 according to an embodiment of the invention.
Fig. 6 is the block diagram of storage component part in accordance with another embodiment of the present invention.
Fig. 7 is the part schematic diagram of memory cell array according to an embodiment of the invention.
Fig. 8 is the partial isometry axle figure of a part of memory cell array according to an embodiment of the invention.
Fig. 9 is the partial cross section figure of memory array according to an embodiment of the invention.
Figure 10 is the partial plan of memory array according to an embodiment of the invention.
Figure 11 is partial cross section figure, and a step in the method that forms memory array according to another embodiment of the invention is described.
Figure 12 is partial cross section figure, and a step in the method that forms memory array according to another embodiment of the invention is described.
Figure 13 is partial cross section figure, and a step in the method that forms memory array according to another embodiment of the invention is described.
Figure 14 is partial cross section figure, and a step in the method that forms memory array according to another embodiment of the invention is described.
Figure 15 is a partial plan, and a step in the method that forms memory array according to another embodiment of the invention is described.
Figure 16 is partial cross section figure, and a step in the method that forms memory array according to another embodiment of the invention is described.
Figure 17 is partial cross section figure, and a step in the method that forms memory array according to another embodiment of the invention is described.
Embodiment
The present invention relates in particular to the floating boom transistor arrangement that uses generally at semiconductor memory in Nonvolatile semiconductor memory device such as flash memory element.In following explanation, illustrate many specific details of some embodiment of the present invention, and the thorough understanding to these embodiment is provided in Fig. 5-17.Yet those skilled in the art that will appreciate that several details of describing in not the following describes also may realize the present invention.In addition, in the following description, be not appreciated that to be interpreted as passing on any specific or relevant physical size the accompanying drawing relevant with each embodiment.But be appreciated that if state the specific or relevant size relevant with embodiment, do not think restriction, unless in claims, express separately yet.
Fig. 5 illustrates an embodiment of computer system 100, and this computer system can be used the storage component part of Fig. 6-17 or according to some other embodiment of storage component part of the present invention.Computer system 100 comprises processor 102, and it carries out various computing functions, carries out specific calculating or task such as carrying out specific software.Processor 102 comprises processor bus 104, and it generally includes address bus, control bus and data/address bus.Processor bus 104 is coupled to Memory Controller 106, and it is coupled to many other parts successively.Processor 102 generally also is coupled to the normally cache memory 107 of static RAM (" SRAM ") device by processor bus 104.
Memory Controller 106 is coupled to system storage by address bus 110 and control bus 112 in the mode of synchronous RAM (" SDRAM ") device 108.The external data bus 113 of SDRAM device 108, or directly or be coupled to the data/address bus of processor 102 by Memory Controller 106.
Also Memory Controller 106 is coupled to such as one or more input equipments such as keyboard or mouses, 114, to allow operator and computer system 100 intercoordinations.Generally, computer system 100 also comprises the one or more output equipments 116 that are coupled to processor 102 by Memory Controller 106, and these output equipments generally are printer or video terminal.Generally also one or more data storage devices 118 are coupled to processor 102, to store data or retrieve data from the external memory media (not shown) by Memory Controller 106.The example of typical memory device 118 comprises hard disk and floppy disk, cassette tape and compact disc-ROM (CD-ROM).Finally, Memory Controller 106 is coupled to basic input-output (" BIOS ") memory (" ROM ") device 120, this device is used for the bios program that storage of processor 102 is carried out when powering up.Bios program is being sent to SDRAM device 108 and after shielding (shadow) bios program from BIOS ROM device 120, processor 102 can directly be carried out processors 102 from BIOS ROM device 120 or from SDRAM device 108.BIOS ROM device 120 is the nonvolatile memory device of (such as at the embodiments of the invention shown in the storage component part of Fig. 6-17) preferably according to the present invention.Can also in computer system 100, use storage component part according to the present invention as other function.
Fig. 6 is the block diagram of storage component part 200 according to an embodiment of the invention, and it can comprise at least a portion of the memory 108 shown in Fig. 5.Storage component part 200 comprises memory cell array 210, and memory cell array 210 comprises the memory cell of being made up of the floating boom FET transistor device that will be described in greater detail below.Storage component part 200 also comprises x-gate decoder 230, and it provides many gate line XG1, XG2 ... XGN is used for the memory cell of memory cell array 210 is carried out addressing.Y-source/drain decoder 240 provides many roots/drain line YD1, YD2 ... YDN is used for the first source/drain region of accessed array 210 floating boom FET transistor cells.X-source/drain decoder 250 similarly provides many data lines XS1, XS2 ... XSN is used for visiting the second source/drain region of these memory array 210 floating boom FET transistor cells.X-source/drain decoder 250 can also comprise sensor amplifier and I/O (I/O) device, is used for reading, writing or obliterated data from memory cell array 210.Storage component part 200 further comprises address buffer 220, and it is from address bus 140 receiver address signal AO ... AN (as shown in FIG. 5).Address buffer 220 is coupled to x-gate decoder 230, y-source/drain decoder 240 and x-source/drain decoder 250, with reading, writing and erase operation on the memory cell in the control storage cell array 210.
Fig. 7 is the part schematic diagram, and an embodiment of memory cell array 210 as shown in FIG. 6 is described.Memory cell array 210 comprises configuration memory cells 300 similar in fact, a plurality of adjacent and interconnection, and a row of their arrays from memory cell 300AA to memory cell 300AN 210 in the first direction upper edge extends.Array also extends up to capable 300NA in second party, further extends up to memory cell 300NN in first party.Memory cell 300AA comprises a pair of field-effect transistor (FET) 310 to each of 300NN, and these field-effect transistors have the floating boom of the electric insulation that conducts electricity between source area and the drain region among the control FET310.Share such as XG1, XG2 to the FET310 in each of 300NN at this unit 300AA ... public grids such as XGN, and in column structure, form, will be as described in greater detail.
Fig. 8 is axle figure such as part, the part of the memory cell array 210 of presentation graphs 7.For clarity, the memory cell 300AA and the 300AB of array 210 only is shown, and in the following description, only describes memory cell 300AA.Yet, be appreciated that, array 210 comprises having a large amount of memory cell of analog structure in fact, so that array 210 is in first direction (" x " direction, as shown in FIG. 8) go up extension, and substantially vertical with first direction second direction (" y " direction, also as shown in FIG. 8) goes up extension.Memory cell 300AA is included in pair of columnar structure 328A and the 328B that forms on p-type substrate 320.Each of column structure 328 comprise by the material with N+ conductance constitute along substrate in x side upwardly extending first source/drain region 322. Structure 328A and 328B also comprise second source/drain region 326, and it also has the N+ conductance of first source that is placed on/drain region 322 vicinities.Being doped with the separator 324 that material makes it to have P-conductance is inserted between first source/drain region 322 and the second source/drain region 328.
Still with reference to figure 8, column structure 328A and 328B are separated out, and are placed between structure 328A and the 328B to allow gate line XG1.Floating boom 330 is inserted between structure 328A and the gate line XG1, and between structure 328B and the gate line XG1.Floating boom 330 also extends under gate line XG1, so that floating boom 330 also is inserted between gate line XG1 and the substrate 320 to form the single control grid 330 between structure 328A and the 328B.Make floating boom 330 and gate line XG1 electric insulation by first dielectric layer 340 that is inserted between gate line XG1 and the floating boom 330.Floating boom 330 is also by being inserted in second dielectric layer 350 and the first structure 328A and the second structure 328B electric insulation between floating boom 330 and structure 328A and the 328B.Also floating boom 330 is placed between the first structure 328A and the second structure 328B thus the position of floating boom 330 from the first structure 328A than near from the second structure 328B, this will be described in greater detail below.Therefore, a part second dielectric 350 of the contiguous in fact first structure 328A wants the appropriate section of second dielectric 350 of neighbour nearly second structure 328B to approach.Yet those skilled in the art that will appreciate that, the thin part of second dielectric 350 can be placed near the second structure 328B, and second dielectric 350 can place near the first structure 328A than thickness portion.Floating boom 330 can be included in the polycrystalline silicon material that is deposited on during the manufacture process on the array 210, and this also will describe in detail below.First dielectric layer 340 and second dielectric layer 350 can be included in the silicon dioxide that generates or deposit during array 210 is made, though also can use other similar dielectric substance.
Make second source of the second source/drain region 326A and the second structure 328B of the first structure 328A/drain region 326B interconnection by data wire YD1, data wire YD1 is made of the metal or other interconnection line that serve as a contrast topological electric insulation with the base of array 210 in fact.Therefore, can understand, can use dielectric material layer (not shown) covering array 210 as shown in Figure 8, this dielectric material layer comprises that the contact that is etched in the dielectric substance runs through thing, so that allow data wire YD1 to be connected to the first structure 328A and the second structure 328B.
Fig. 9 is the partial cross section figure of the memory array 210 seen from the hatching 9-9 of Fig. 8, therefore, generally with Fig. 8 in parallel the watching of x direction.As mentioned above, second dielectric layer 350 by different-thickness separates floating boom 330 and the first structure 328A and the second structure 328B.Therefore, the first structure 328A and floating boom 330 separate first apart from d 1, and the second structure 328B and floating boom 330 separate second distance d 2, wherein first apart from d 1Less than second distance d 2In a certain embodiments, second distance d 2Be about first apart from d 1Double thickness.In another particular embodiment, floating boom 330 has the height d of about 0.1 μ m 3And separate about 33 with the first and second structure 328A and 328B
Figure C200480019004D0012123237QIETU
First apart from d 1With about 66
Figure C200480019004D0012123237QIETU
Second distance d 2
Figure 10 is the partial plan of memory array 210 shown in Figure 9.Especially, unit 300AA has the spacing of extending about 2F at y-direction, and in the spacing of x-about 2F of direction extension, wherein F is the characteristic size that is associated with minimum lithographic plate characteristic size.Therefore, can advantageously be stored in about 4F to logic state corresponding to the individual data position 2The zone in.With the 8F that has that in the DRAM memory array, finds usually 2The folded array structure that the crowd of characteristic size knows is compared, and this is favourable.
The foregoing description also provides other advantages over the prior art.For example, refer again to Fig. 9, during read operation, owing on the first structure 328A of the thin part usually of the dielectric layer 350 that separates with floating boom 330, carry out programming and erase feature, having only less influence with respect to the second structure 328B (this layer position is common than thickness portion near dielectric layer 350) than the electric charge capture in the thin oxide layer.
Figure 11-the 16th, partial cross section figure illustrates the step in the method that forms memory array according to another embodiment of the invention.At first, use from silicon and form and be doping to the substrate 320 of P-conductance as starting material with reference to Figure 11.On substrate 320, form first source/drain region 322.Can on substrate 320, form district 322 by ion injection or other similar procedure, so that obtain desired N+ conductance.On the other hand, can generate the epitaxial loayer of N+ silicon on the surface of substrate 320.Can on first source/drain region 322, form separating layer 324 by making the P-silicon epitaxy be generated to needed thickness then.Another extension generation by N+ silicon can form second source/drain electrode layer 326 on separating layer 324.Can on the exposed surface of second source/drain electrode layer 326, form the laying 400 that constitutes by silica, can cover the laying 420 that constitutes by silicon nitride thereon.
Forward Figure 12 now to, in structure shown in Figure 11, form a plurality of first raceway grooves 440 and a plurality of second raceway groove 460.With the approximately perpendicular direction of y-direction on, and in fact also in parallel to each other, form first raceway groove 440 and second raceway groove 460 in the structure of Figure 11.First raceway groove 440 and second raceway groove 460 protrude into downwards in the structure to p-substrate layer 320.Can be on the exposed surface of structure shown in Figure 11 with photoresist layer (not shown among Figure 12) form a pattern and form with the assigned address etch stop layer that meet, that have exposed surface portion thereof of first raceway groove 440 and second raceway groove 460 and form first raceway groove 440 and second raceway groove 460.Can pass through method for plasma etching, or remove backing material above the exposed surface portion thereof by many wet etchings of knowing in the technical field.
Still, use the silicon dioxide 480 that generates in first raceway groove 440 and second raceway groove 460 by oxidizing process or many perception methods are deposited in first raceway groove 440 and second raceway groove, second raceway groove 460 by other to fill first raceway groove 440 and second raceway groove, second raceway groove 460 in fact with reference to Figure 12.Remove the material (as shown in Figure 12) that is placed between first raceway groove 440 and second raceway groove 460 by another etching stopping layer (not shown) that forms photoresist, and remove material by wet method or method for plasma etching and form hole 500, as shown in Figure 13.The deposition process of knowing by oxidation or other crowd forms the bottom 510 that comprises earth silicon material, to form second dielectric layer 350.
With reference now to Figure 14,, on the structure of Figure 13, form polysilicon layer 520, extend in the space 500 of Figure 13 each under this course.The method that can know by various crowds is deposit spathic silicon layer 520 structurally.On polysilicon layer 520, form oxide skin(coating) 530 then by exposed polysilicon layer 520 in oxidizing process.Can on oxide skin(coating) 530, form polysilicon or metal level 540 by polysilicon or the metal deposition that various crowds know then.
Figure 15 is a partial plan, is illustrated in the formation of upwardly extending, a plurality of parallel in fact groove 520 in y-side.Form groove 520 by the structure shown in etching Figure 14 selectively, so that polysilicon or metal interconnected 530 extends and crosses groove 520.Interconnection 530 forms gate line XG1, XG2...XGN, as it is described in detail to link Fig. 8-10.Can remove polysilicon layer 520, oxide layer 530 and polysilicon or metal level 540 from upper surface 540 then, as in Figure 16, describing in more detail.Can use chemistry-mechanical planarization method to remove layer 520,530 and 540.
Forward Figure 17 to, can be on surface 550 deposition surface oxide skin(coating) 560, and make with photoresist (not shown) form pattern and form etching stopping layer, to form a plurality of protrusions 590 that extend to second source/drain region 326 by oxide layer 560.Deposition extends downwardly into each protrusion 590 so that the metal level 570 of electric coupling is carried out in second source/drain region 326 on oxide layer 560 then, forms and links data wire YD1, the YD2...YDN that Fig. 8-10 describes in detail.
Though be appreciated that from top description and described specific embodiment of the present invention for illustrative purposes here, can carry out various modifications and without departing from the spirit and scope of the present invention.For example, also can be being attached among other embodiment in some feature shown in the context of one embodiment of the present of invention.Therefore, except following claim, the present invention is not subjected to the restriction of the above-mentioned explanation of embodiment.

Claims (28)

1. computer system comprises:
CPU; And
Be coupled at least one storage component part of CPU, described storage component part comprises having the array of memory cells of arranging with row and column, be used to store needed logic state, each unit comprises first column structure and second column structure that separates, described first column structure and second column structure all have first a source/drain region and second a source/drain region, have be inserted between first column structure and second column structure and with the first and second column structure spaced floating gates structures, in the position of floating boom and first and second column structures selected one more approaching, wherein, second source of second source of the described first column structure/drain region and second column structure/drain region electric coupling.
2. computer system as claimed in claim 1 is characterized in that, described storage component part also comprise be arranged in floating gate structure and with the gate line of floating gate structure electric insulation.
3. computer system as claimed in claim 2 is characterized in that described first and second sources/drain region comprises the semi-conducting material with first conductivity.
4. computer system as claimed in claim 3 is characterized in that, also comprises the separating layer of the semi-conducting material between the described first and second sources/drain region that is inserted in described first and second column structures each, and described separating layer has second conductivity.
5. computer system as claimed in claim 3 is characterized in that described first and second sources/drain region comprises silicon, and first conductivity is N+ conductivity.
6. computer system as claimed in claim 4 is characterized in that described separating layer comprises silicon, and second conductivity is P-conductivity.
7. computer system as claimed in claim 2 is characterized in that described storage component part also comprises decoder, and it is coupled in first source/drain region, second source/drain region and the gate line each.
8. computer system as claimed in claim 7 is characterized in that, also comprises the address buffer that is coupled to decoder.
9. computer system as claimed in claim 1 is characterized in that, also comprises the address bus, data/address bus and the control bus that CPU are coupled at least one described storage component part.
10. computer system as claimed in claim 9 is characterized in that, also comprises the system controller that is coupled to described address bus, data/address bus and control bus.
11. computer system as claimed in claim 10 is characterized in that, also comprises in keyboard, mouse, display unit and the modulator-demodulator that is coupled to input/output module at least one.
12. computer system as claimed in claim 9 is characterized in that, also comprises outside second mass storage device.
13. a semiconductor memory comprises:
Has the array of memory cells that is used to store needed logic state, each unit also comprises the first and second adjacent field-effect transistors, second source/drain region that each field-effect transistor has first source/drain region and separates, described first and second sources/drain region is configured to have the column structure that inserts separating layer, and each unit also comprises public floating gate structure, source/the drain region of the described floating gate structure and first field-effect transistor separates first distance, and separate second distance with the source/drain region of second field-effect transistor, wherein, described first distance is less than described second distance, and each in described first and second field-effect transistors all is formed on the backing material of first conductivity type, and the separating layer that has source/drain region that the material by second conductivity type forms and formed by the material of described first conductivity type.
14. semiconductor memory as claimed in claim 13, it is characterized in that, the described first source/drain region of each field-effect transistor and second source/drain region are to be made of the semi-conducting material with N+ conductivity, and wherein the described separating layer of each field-effect transistor is to be made of the semi-conducting material with P-conductivity.
15. semiconductor memory as claimed in claim 13 is characterized in that, described public floating gate structure is made of polysilicon.
16. semiconductor memory as claimed in claim 13 is characterized in that, described second distance is the twice of described first distance.
17. semiconductor memory as claimed in claim 13 is characterized in that, described first distance is
18. semiconductor memory as claimed in claim 13, it is characterized in that, described array is included in also that first party extends upward and the drain line of the described second source/drain region of first and second field-effect transistors that are coupled, and wherein first source of first and second field-effect transistors/drain region extends upward in the second party vertical with first direction.
19. semiconductor memory as claimed in claim 18 is characterized in that, described array also is included in the upwardly extending gate line of second party.
20. semiconductor memory as claimed in claim 19 is characterized in that, also comprises each the decoder that is coupled to drain line, first source/drain region and gate line.
21. a formation has the method for the storage component part of a plurality of interconnection memory cells, each unit comprises: place first column structure on substrate, it has first source/drain region and second source/drain region;
Place second column structure on substrate, wherein, described second column structure and described first column structure separate, and this second column structure has first source/drain region and second source/drain region;
Between first column structure and second column structure, form grid structure; Inserting floating gate structure between first column structure and the grid structure and between second column structure and the grid structure, in the position of described floating gate structure and described first column structure and second column structure selected one more approaching; And
Second source/the drain region of described first column structure is electrically coupled to the second source/drain region of described second column structure,
Wherein, the step of described first and second column structures of placement also comprises on substrate:
On substrate, form first source/drain region with first conductivity;
Form second source/drain region, each in this second source/drain region press close to they separately first
Source/drain region, this second source/drain region have described first conductivity; With
Between the described first source/drain region of each column structure and second source/drain region, insert and separate
Layer.
22. method as claimed in claim 21 is characterized in that, also comprises at described first and second column structures of placement on the substrate: be doping to and placing first and second column structures on the silicon substrate with described first conductivity.
23. method as claimed in claim 22 is characterized in that, place described first and second column structures and comprise being doping on the silicon substrate with described first conductivity: the described substrate that mixes makes it to have P conductivity.
24. method as claimed in claim 21 is characterized in that, forms the described first source/drain region with first conductivity and comprises: form the described first source/drain region with N+ conductivity.
25. method as claimed in claim 21, it is characterized in that, form each described second source/drain region of pressing close to their first source/drain regions separately and comprise: on their first source/drain regions separately, form described source/drain region with N+ conductivity.
26. method as claimed in claim 21, it is characterized in that, inserting separating layer between the described first source/drain region of each column structure and second source/drain region comprises: for each column structure, form the layer with second conductivity between first source/drain region and second source/drain region.
27. method as claimed in claim 26, it is characterized in that, describedly comprise forming layer between first source/drain region and the second source/drain region: between first source/drain region and second source/drain region, form the layer that is doping to P-conductivity with second conductivity.
28. method as claimed in claim 21, it is characterized in that, describedly also comprising between first column structure and the grid structure and inserting floating gate structure between second column structure and the grid structure: between floating gate structure and first and second column structure, place insulating barrier.
29. method as claimed in claim 28, it is characterized in that, the described insulating barrier of placing between floating gate structure and first and second column structure comprises: form first insulating barrier with first thickness between first column structure and floating gate structure, and between second column structure and floating gate structure, forming second insulating barrier with second thickness, described first thickness is less than described second thickness.
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KR100772742B1 (en) 2007-11-01
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US20060197143A1 (en) 2006-09-07
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JP2007527614A (en) 2007-09-27
US7719046B2 (en) 2010-05-18

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