CN100508178C - Semiconductor device and method for establishing virtual assembly structure on it - Google Patents

Abstract

The invention relates to a semiconductor device which comprises a circuit, a first conductor component connected to the circuit, a semiconductor substance insulating the first conductor component, and at least two second conductor components which have irregular shape and is next to the first conductor component, and the electric linkage does not exist between the circuits. The method for manufacturing the semiconductor device of the invention, especially designing and manufacturing the nominal component in the semiconductor device can obtain a better flattened effect.

Description

Semiconductor device reaches the method for setting up illusory modular construction on semiconductor device

Technical field

The invention relates to the manufacturing of semiconductor device, particularly, make it possible to obtain better planarization effect relevant for the method that in semiconductor device, designs and make illusory assembly.

Background technology

When the semiconductor subassembly size decreases and the manufacturing technology of its use evolves to time micron during the stage, dual-damascene technics is just widely used in semiconductor technology.In dual-damascene technics, use copper usually as online conductor material.Other conductor material then comprises tungsten, titanium, reaches titanium nitride.And, the dielectric material of silica, fluorine-containing silicate glasses or low-k etc. then as interlayer dielectric (inter-leveldielectric, ILD).Chemical mechanical milling tech then is used to carry out etching or wafer surface planarization.In the material removal process of cmp, relate to mechanical lapping and chemical etching.Yet because the rate that removes of metal and dielectric material is usually different, the grinding selectivity causes be unwilling dish-likeization or the corrosion effect seen of people.Dish-likeization effect be in copper sunken in or protrude in its contiguous dielectric plane.Corrosion effect then is the local attenuation of dielectric.

Figure 1A～Fig. 1 D shows because of chemical mechanical milling tech, and the schematic diagram of dish-likeization that on semiconductor wafer, produces and corrosion effect.In Figure 1A, when the grinding rate of metal 124 when being high than dielectric substance 122, the semiconductor device 120 on the semiconductor wafer has presented dish-likeization effect.Dielectric material 122 can be the dielectric material of silica, fluorine-containing silicate glasses, low-k, or is its combination.124 on metal can be copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride or its combination.Dielectric material 122 and metal 124 can be the parts of inside conductor structure in the semiconductor integrated circuit, and it can be handled by dual-damascene technics, and it comprises similar to a plurality of technologies such as deposition, etching and cmps.In grinding technics (for example chemical mechanical milling tech), when the grinding rate of metal 124 when being high than dielectric material 122, the uneven variation that its surface profile presented is referred to as dish-likeization effect.

In Figure 1B, when the grinding rate of dielectric material 142 when being high than metal 144, the semiconductor device 140 on the semiconductor wafer has presented dish-likeization effect.When the grinding rate of dielectric material 142 when being high than metal 144, the uneven variation that its surface profile presented is referred to as dish-likeization effect.

In Fig. 1 C, when the grinding rate of dielectric material 162 when being high than metal 164, the semiconductor device 160 on the semiconductor wafer has presented corrosion effect.When the grinding rate of dielectric material 162 when being high than metal 164, the uneven variation that its surface profile presented is referred to as corrosion effect.

In Fig. 1 D, when the grinding rate of dielectric material 182 when being high than metal 184, the semiconductor device 180 on the semiconductor wafer has presented corrosion effect.When the grinding rate of dielectric material 182 when being high than metal 184, the uneven variation that its surface profile presented is referred to as corrosion effect.

Semiconductor device 120,140,160, and 180 can further comprise circuit and semiconductor substrate.This circuit can comprise mos field effect transistor (MOSFET), diode transistor, diode, memory cell (memory cell), resistor, capacitor, inductor, high voltage transistor, transducer or its combination.This semiconductor substrate can comprise semiconductor element (for example crystal silicon, polysilicon, amorphous silicon, and germanium), semiconducting compound (for example carborundum and gallium arsenic), semiconducting alloy (for example SiGe, gallium arsenide phosphide, aluminium indium arsenide, aluminum gallium arsenide, phosphorus gallium indium) and/or its combination.This semiconductor substrate can (for example: semiconductor substrate be the silicon-on-insulator base material, and SOI), it has buried oxide (Buried oxide) structure for the semiconductor substrate on the insulator.In other example, compound semiconductor substrate can comprise multiple silicon structure, and perhaps this silicon substrate can comprise the composite semiconductor structure of multilayer.

Dish-likeization and corrosion effect also may be that (for example shallow trench isolation produces in the time of STI) at chemical mechanical milling tech manufacturing isolation structure.This kind shallow trench isolation can be by forming groove structure with dry ecthing on base material, this groove structure is formed with megohmite insulant (silica for example, low-k material or its in conjunction with) filling again.Silicon nitride can be used as etching stopping layer (ESL), with the active region between the protection shallow trench isolation district.The groove of this filling can have sandwich construction, and for example hot growth oxide layer liner adds the silica or the low-k material of chemical vapour deposition (CVD).When using chemical mechanical milling tech to carry out the planarization of etch-back or semiconductor surface, the grinding selectivity between silica and silicon nitride may cause dish-likeization effect.

Dish-likeization and corrosion effect are all relevant with layout patterns density.In order to eliminate dish-likeization and the corrosion effect that in flatening process (comprising the chemical mechanical milling tech that forms shallow trench isolation and inside conductor), takes place, need make that the layout density homogeneity is higher with illusory assembly, and reduce the phenomenon of surface profile injustice.

Dish-likeization and corrosion effect are very responsive for layout structure and density.Illusory metal assembly is design and refers to be integrated in the dual-damascene structure, makes layout density more even, and then help the carrying out of flatening process.

Other has the technology that uses chemical grinding also can suffer from similar above-mentioned problem.For example, shallow trench isolation (STI) utilizes chemical grinding technology to carry out etch-back and global planarization.Generally also can carry out etching program, so that the silica etching on the silicon nitride is more complete.The surface differences phenomenon relevant with layout density with local layout can be eliminated by using illusory assembly (for example illusory driving component in shallow trench isolation).

Illusory assembly with the inventive method manufacturing can be strengthened the arrangement space characteristic, but can obviously not compensate to some extent for the high difference in rank.

Summary of the invention

The invention relates to the manufacturing of semiconductor device, particularly, make it possible to obtain better planarization effect relevant for the method that in semiconductor device, designs and make illusory assembly.

The invention provides a kind of method that is used on semiconductor device, setting up illusory modular construction.This method at first defines the process specification of this semiconductor device.And testing tool is provided, wherein this testing tool comprises: test structure and metal assembly.Wherein this test structure is in order to measuring resistance and capacitance.This metal assembly is irregularly shaped, and at least two.By this testing tool data collection, it at first grinds this testing tool again, and the surface appearance of measuring this testing tool again to be determining its grinding rate, to grind selectivity and surface level difference, and measures the resistance and the capacitance of the test surfaces of this testing tool.Again according to the above-mentioned data decision layout density upper limit and target function.

The present invention also provides another kind of method.This method at first is divided into the semiconductor product surface MxN grid, determine the density matrix of this grid again, and in each element of density matrix is cut apart, add irregular illusory assembly respectively, and then calculating target function and whether assess this target function be minimum value.

Said method can be by realizing in the computer program loads computer system that will be stored in computer-readable storage media.

Description of drawings

For above-mentioned purpose of the present invention, feature and advantage can be become apparent, embodiment cited below particularly, and cooperate appended diagram, it is as follows to be elaborated:

Figure 1A～Fig. 1 D shows the schematic diagram of dish-likeization and corrosion effect;

Fig. 2 is presented at the illusory assembly cross sectional representation of making on the semiconductor device;

Fig. 3 shows the schematic diagram of being located at the illusory assembly of semiconductor device according to the embodiment of the invention;

Fig. 4 demonstration is according to the schematic diagram of the irregular illusory assembly of the embodiment of the invention;

Fig. 5 shows the schematic diagram according to embodiment of the invention density matrix;

Fig. 6 shows the flow chart that determines illusory assembly insertion method according to the embodiment of the invention;

Fig. 7 shows the method for designing flow chart that uses illusory assembly in the new product of given technology according to the embodiment of the invention;

Fig. 8 A and Fig. 8 B show according to the embodiment of the invention at the average density metal skew of inserting illusory assembly front and back and the schematic diagram of standard deviation skew;

Fig. 9 shows the schematic diagram according to the integrated circuit (IC) apparatus of the embodiment of the invention.

Symbol description:

120,140,160,180,200,500 semiconductor devices;

124,144,164,184,220,230,240,520 metals;

122,142,162,182,210,510 dielectric substances;

530 zones;

540,600,610,620,630,640,650,660,670,680,690 illusory assemblies;

700 density matrix;

710 grids;

1100 integrated circuit (IC) apparatus;

1110 semiconductor devices;

1120 inside conductors;

1130 dielectric layers;

1140 illusory assemblies;

1150 insulating groove structures;

1160 illusory driving components.

Embodiment

For allow purpose of the present invention, feature, and advantage can become apparent, preferred embodiment cited below particularly, and cooperate appended pictorial image 2 to Fig. 9 is described in detail.

Fig. 2 is presented at the illusory assembly cross sectional representation of making on the semiconductor device 200.Semiconductor device 200 comprises dielectric material 210 and metal assembly 220,230, reaches 240.Dielectric material 210 can comprise dielectric material or its combination of silica, fluorine-containing silicate glasses, low-k.Metal assembly 220,230, and 240 can be copper, tungsten, titanium, titanium nitride or its combination.Metal assembly 220 and 240 can with bottom circuit and loam cake bonding pad electrically connect, metal assembly 230 is not then and other any functional circuit or bonding pad binding.On the contrary, metal assembly 230 can be electrically isolated, and it is as illusory assembly.The illusory assembly of this kind can be used to adjust local layout density, to obtain better grinding effect.

Similarly, illusory assembly also can be used for the formation technology of shallow trench isolation isolation structure, to obtain better planarization effect.According to the embodiment of the invention, illusory active region can be provided with or be located at illusory assembly active zone separately, makes that the layout density homogeneity is higher, to improve the planarization effect of chemical mechanical milling tech.The method that will be placed on dummy structures to center of gravity and make dummy structures in the multilayer inside conductor below is described.Yet this illustrates that disclosed method goes in order to the illusory assembly in the insulation structure of shallow groove that increases the planarization effect.

Referring to Fig. 3, it shows the schematic diagram of being located at the illusory assembly of semiconductor device 500 according to the embodiment of the invention.Semiconductor device 500 comprises dielectric material 510 and metal assembly 520, and it is the part of integrating apparatus.Dielectric material 510 can comprise dielectric material or its combination of silica, fluorine-containing silicate glasses, low-k.520 of metal assemblies can be copper, tungsten, titanium, titanium nitride, tantalum, tantalum nitride or its combination.Being looped around metal assembly 520 outer zones 530 is its Precinct, in order to stop the insertion of illusory assembly.Outside zone 530, be provided with the irregularly shaped and big or small illusory assembly 540 of a group in the dielectric material 510.Irregular illusory assembly 540 is generally identical metal with metal assembly 520 and constitutes.

Especially illusory assembly 540 has predefined irregular shape.Illusory assembly 540 can have different shapes, size and thickness.The method that designs irregular illusory assembly then is referred to as the irregular illusory assembly insertion in model basis.The irregular illusory assembly insertion in this model basis is used irregular assembly, and makes that local density and insertion position can be different, to reach better homogeneity, lower dead resistance and electric capacity and less level difference.And this irregular illusory assembly insertion in model basis can form irregular illusory assembly, inserts with random device.This irregular illusory assembly insertion in model basis also can be provided with illusory assembly at random, comprises its position and orientation.The irregular illusory assembly of this kind can be in order to reducing or eliminating arrangement space characteristic and dead resistance/electric capacity, to reduce level difference, and promote the planarization effect.

Fig. 4 shows the various embodiments of irregular illusory assembly 600.For example, illusory assembly 600 can comprise square 610, rectangle 620, the capable matrix-like 630 of square, interrupted linear 640, dotted line shape 650, circular 660, triangle 670, polygonal 680, and cross 690.Above-mentioned only is the description of several examples, and illusory assembly 600 can have other shape that designs according to actual needs.Irregular illusory assembly can have different sizes and thickness, and position is set for it and the orientation also can determine at random.

Generally speaking, illusory assembly can be constituted by metal and other conductive materials that is used for the multilayer inside conductor.This conductive materials can comprise copper, tungsten, titanium, titanium nitride or its combination.This irregular illusory assembly also can be the illusory driving component that is used for shallow trench isolation.This illusory driving component can comprise silicon, polysilicon, silica and silicon nitride.This irregular illusory assembly can have sandwich construction, reaches better planarization effect to match to merge with functional unit.

Fig. 5 shows the schematic diagram according to embodiment of the invention density matrix 700.Before inserting illusory assembly, will prepare the aimed wafer region separation of inserting illusory assembly earlier is MxN grid.The size that this wafer area is separated is according to used technology and technology and different.For example, when size of components was dwindled, this grid also dwindled accordingly.According to another embodiment, when the employed grinding pad of cmp is harder, and this grinding technics is insensitive for the structure of part, and then this split dimension should strengthen.Grid 710 is for being positioned at the grid of the capable j row of i, and its corresponding density is S _Ij, it is to produce according to following model.The parameter-definition relevant with illusory assembly insertion is as follows:

D _IjLayout density for the capable j row of i grid;

S _IjIllusory assembly layout density for the capable j row of i grid;

F _IjBe whole layout density of the capable j row of i grid, wherein:

(formula 1)

F _ij＝D _ij+S _ij；

U _IjThe upper limit for whole layout density of the capable j row of i grid;

K is an average contact hole size when calculating the target function of following definition;

μ _IjFor being the center with the capable j row of i grid, be the mean value of whole layout density of grid on every side of radius with k grid, wherein:

(formula 2)

${\mathrm{\μ}}_{\mathrm{ij}}=\sqrt{\frac{\underset{m=i-k}{\overset{i+k}{\mathrm{\Σ}}}\underset{n=j-k}{\overset{j+k}{\mathrm{\Σ}}}\mathrm{Fmn}}{{(2k+1)}^2-1}};$

σ _IjFor being the center with the capable j row of i grid, be the standard deviation of whole layout density of grid on every side of radius with k grid, wherein:

(formula 3)

${\mathrm{\σ}}_{\mathrm{ij}}=\sqrt{\frac{\underset{m=i-k}{\overset{i+k}{\mathrm{\Σ}}}\underset{n=j-k}{\overset{j+k}{\mathrm{\Σ}}}{(\mathrm{Fmn}-{\mathrm{\μ}}_{\mathrm{ij}})}^2}{{(2k+1)}^2-1}};$

And this target function is

This target function is minimized also promptly to try to achieve following result in order to determine the density of illusory assembly, and make F _IjBe less than or equal to U _Ij

(formula 4)

$\min \left(\underset{i}{\mathrm{\Σ}}\underset{j}{\mathrm{\Σ}}\frac{{\mathrm{\σ}}_{\mathrm{ij}}}{{\mathrm{\μ}}_{\mathrm{ij}}}\right);$

Above-mentioned (formula 4) is the upper limit that whole layout density of defining each grid can not surpass whole layout density.The decision of the upper limit of these whole layout density is to do according to method shown in Figure 8.According to an embodiment of the irregular illusory assembly insertion in model basis, average contact hole size k is the measured value of the interactive distance of layout density in the chemical mechanical milling tech.The grinding result of a certain position is with relevant apart from the layout density of the grid in the k grid.Usually this average contact hole size k can comprise metallics, dielectric material, lapping liquid, grinding pad, grinding pressure and other parameter according to the decision of grinding technics parameter.The upper limit U of these whole layout density _IjThen can be according to the decision of localized design metal structure, it also can be the function of position.At whole layout density F _IjUpper limit U with whole layout density _IjAfter all having determined, just can decide the average value mu of whole layout density respectively according to above-mentioned (formula 2) and (formula 3) _IjStandard deviation sigma with whole layout density _IjThen, the calculating according to (formula 1) just can draw illusory component density.

According to above-mentioned illusory component density, can adopt irregular illusory assembly.This illusory assembly can be any shown in Fig. 4, but not as limit.And the size of illusory assembly and thickness can determine at random, to meet this illusory component density that calculates.Position and orientation that illusory assembly inserts also can determine at random.Irregular illusory assembly and inserted mode at random can reduce the arrangement space characteristic and reduce rank high level difference.

Fig. 6 shows the flow chart that determines illusory assembly insertion method according to the embodiment of the invention.Method 800 is specially adapted to new semiconductor technology (for example technology below 0.13 micron or 0.09 micron).New semiconductor technology can comprise new or different semi-conducting materials, semiconductor board, semiconductor circuit design, manufacturing environment and parameter etc.For example, the employed material of inner layer dielectric layer (ILD) can comprise silica, fluorine-containing silicate glasses, and the dielectric material of low-k (for example: black diamond (Black Diamond), dried glue (Xerogel), gas glue (Aerogel), mix fluorine amorphous carbon film (amorphous fluorinated carbon), poly-to dimethyl benzene (Parylene), benzocyclobutene (BCB) and SiLK), wherein the employed parameter of cmp can change thereupon.

In method 800, step S810 definition process specification.According to the inside conductor flatening process of the embodiment of the invention, its process specification comprises the specification of metallics, size of wire, inner layer dielectric layer dielectric material, flatness permissible range, grinding technics instrument and grinding technics parameter (for example grinding pad hardness, grinding pad kind, lapping liquid composition, grinding pressure, rotating speed and grinding selectivity).

Step S820 provides testing tool, also irregular illusory assembly is inserted the standardization that influences that is caused to collect illusory assembly insertion data.Testing tool has semiconductor layout specificity, and set for testing and testing.Testing tool can comprise the electrical testing structure, and it places the metal structure next door, and it comprises and the design metal wire of new technology compatibility and the illusory assembly with difformity, thickness, position and orientation.According to the embodiment of the invention because Kai Shi resistor (Kelvin resistor) can provide higher electrical measurement accuracy, therefore with it as this electrical testing structure.When the design test instrument, the metal wire of different size and density can be included in its layout structure.Testing tool can comprise different pre-locking assemblies and layout (for example shown in Figure 3), makes that these assemblies can be evaluated to determine this layout density upper limit and target function.According to embodiment, testing tool is semiconductor regions, semiconductor chip or the semiconductor wafer with particular design layout.According to embodiment, this target area or entire wafer zone are split into MxN grid, as shown in Figure 5.

Among the step S830, utilize above-mentioned testing tool to simulate grinding technics.Collect test data simultaneously, it comprises the relation between grinding rate, grinding selectivity, surface level difference and grinding result's (comprising grinding rate and surface level difference) and the layout structure (comprising layout density).According to embodiment, the data of collection can be in order to determine the average contact hole size and/or the layout density upper limit.With regard to a certain technology, it has only one layout density to greatest extent.For example, density metal can not be higher than 75%.Yet with regard to a given design metal layout, can be used for space that the dummy metal assembly inserts may be still less.Each grid can have its local layout density upper limit and localized design layout structure and layout density.Step S830 can decide this layout density upper limit by simulation and calculating.This kind layout density upper limit can be used for illusory assembly and inserts.In step S830, (formula 4) defined target function can use different average contact hole sizes to be calculated, and draws the layout density upper limit.The collected data of step S830 can comprise the resistance and the electric capacity data of this testing tool, and its demonstration puts on the dead resistance and the electric capacity of this layout.Whether the grinding result who is drawn by this testing tool and the estimation of dead resistance/electric capacity can be compared with the target function that calculates, be consistent to verify it, and verify that whether safe this target function suitably and effectively.

In step S840, use some condition to assess above-mentioned test, simulation and calculating, whether meet the process specification among the step S810 to determine this average contact hole size.And whether decision, the target function that calculates and the data of collecting from chemical grinding technology and this test structure are consistent.When at least one was negative among the above-mentioned affirmation result, this method was got back to step S830, otherwise this method is carried out step S850.

In step S850, write down the layout density upper limit and the target function of each given layout structure.Above-mentioned data can be used for carrying out the illusory assembly insertion of new product, referring to Fig. 7.

In step S860, set up the processing simulation instrument according to above-mentioned data, it comprises average contact hole size, the layout density upper limit and dead resistance/electric capacity.This processing simulation instrument can comprise the target function of process specification, foundation, irregular illusory assembly data bank and irregular illusory assembly generator.This processing simulation instrument can be used for irregular illusory assembly insertion, grinding technics design and grinding control.

Fig. 7 shows the method for designing flow chart that uses illusory assembly in the new product of given technology according to the embodiment of the invention.This given technology is to define in above-mentioned method shown in Figure 6.

The density matrix of the step S910 decision grid in the method 900.This semiconductor wafer surface zone is separated into MxN grid.This separation is according to simulation in the method 800 and data collection.Can determine its layout density by this New Product's Design layout structure.The program of this decision can be carried out by the processing simulation instrument.

In step S920, with the processing simulation optimization.This processing simulation needs input analog parameter earlier, comprises average contact hole size, the layout density upper limit and generator, to produce irregular illusory assembly.The data of this input can obtain by method 800.Also may need some parameter, make it possible to according to this density matrix of this new product and/or out of Memory is revised and optimization.

In step S930, by the illusory assembly of simulation decision, and with in its adding layout, it is to do according to the specific calculation of processing simulation and (formula 1) to (formula 4).The optimization of illusory assembly also can be done by this target function is minimized, and it is under the prerequisite of global density at each grid layout density upper limit that is not higher than this grid and do.Illusory assembly is the irregular illusory assembly with difformity, size, thickness, position, orientation.According to embodiment, the illusory assembly of each grid is to select at random and with the assessment of the layout density upper limit of this grid.If it surpasses this upper limit, then should give up by illusory assembly, select new illusory assembly and assessment in addition.Other different screening conditions also can be used to determine illusory assembly, for example dead resistance/electric capacity and grinding result etc.This step is implemented at each grid, all determines up to the illusory assembly of all grids.This target function can calculate further to assess.

In step S940, this target function is assessed to determine whether it is minimum value.If this target function is not to be minimum value, and this planarization is not up to specification, then gets back to step S930.Whether perhaps, can assess this target function with a special value minimizes.

In step S950, the illusory assembly of design is integrated in final products, and be recorded in order to the design document of making the light shield and the manufacturing, and the light shield design document in.

Fig. 8 A and Fig. 8 B show according to the embodiment of the invention at the average density metal skew of inserting illusory assembly front and back and the schematic diagram of standard deviation skew.Fig. 8 A is presented at the integral layout density distribution after illusory assembly inserts preceding and insertion.Can observe after illusory assembly inserts, the layout density allocation offsets is to a side of high value.Fig. 8 B is presented at after the illusory assembly insertion, the obvious step-down of standard deviation, and integral layout density is average.Therefore, the planarization effect of chemical mechanical milling tech can be because of more average out to improve of layout density.

Fig. 9 shows the schematic diagram according to the integrated circuit (IC) apparatus of the embodiment of the invention.Integrated circuit (IC) apparatus 1100 comprises a plurality of semiconductor devices 1110.Semiconductor device 1110 can form logical circuit, memory cell or other transistor array, and it comprises monobasic, binary, three-dimensional space array, and it also can be arranged at the above or above configuration of row of delegation.

Integrated circuit (IC) apparatus 1100 can comprise inside conductor 1120, its along and/or pass one dielectric layer 1130 at least.Dielectric layer 1130 can comprise silica, fluorine-containing silicate glasses, black diamond (BlackDiamond), dried glue (Xerogel), gas glue (Aerogel), mixes the amorphous carbon film (amorphousfluorinated carbon) of fluorine, gather dimethyl benzene (Parylene), benzocyclobutene (BCB) and SiLK and/or other material, and it can be done by chemical vapor deposition (CVD), ald (ALD), physical vapor deposition (PVD), method of spin coating and/or other technology.Inside conductor 1120 can comprise the alloy of copper, tungsten, titanium, titanium nitride, gold, aluminium, carbon nanotube, carbon fullerene (Fullerenes), refractory metal (refractory metal), this metal and/or other material, and it can be done by chemical vapor deposition (CVD), physical vapor deposition (PVD), plating and/or other technology.Inside conductor 1120 can comprise adhesion layer (Adhesion Layer) (it can comprise titanium, titanium nitride, tantalum or tantalum nitride), barrier layer (it can comprise titanium nitride or tantalum nitride) and table body conductor layer (it comprises copper, tungsten, aluminium or aluminium alloy).Inside conductor 1120 can further comprise at least one illusory assembly 1140, and wherein irregular illusory assembly 1140 inserts interlayer dielectric layer 1130 according to the inventive method, and its its tandem circuit binding down of getting along well.Illusory assembly can use material the same with inside conductor and technology manufacturing.

Semiconductor device 1110 can be silicon-on-insulator (SOI) base material, and it has the BOX structure.In other example, the composite semiconductor base material can comprise multilayer silicon structure or MULTILAYER COMPOSITE semiconductor structure.Semiconductor device 1110 can comprise between a plurality of insulating groove structures 1150 of active region in order to insulation.And, at insulating regions illusory driving component 1160 can be set, to promote the layout average degree, make it possible to improve grinding technics.This illusory driving component can have irregularly shaped.Illusory driving component 1160 can comprise silicon or polysilicon.Illusory driving component 1160 can further comprise cushion oxide layer and silicon nitride layer, and wherein most of this layer is removed after grinding technics is handled.Except silicon nitride, can also comprise silicon oxynitride and carborundum. Illusory assembly 1140 and 1160 can have at random shape, size, thickness, position, and orientation.This shape at random comprises: square, rectangle, the capable matrix-like of square, intermittently linear, dotted line shape, circle, triangle, polygonal, and cross.

Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those who are familiar with this art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking accompanying the claim person of defining.

Claims (6)

1, a kind of method of setting up illusory modular construction on semiconductor device is characterized in that, this method comprises the following steps:

Define the process specification of this semiconductor device;

Testing tool is provided, and it comprises:

Test structure is in order to measuring resistance and capacitance;

At least two have erose metal assembly;

By this testing tool data collection, it comprises:

Grind this testing tool;

The surface appearance of measuring this testing tool is to determine its grinding rate, to grind selectivity and surface level difference; And

Measure the resistance and the capacitance of the test surfaces of this testing tool;

The decision layout density upper limit; And

The decision target function.

2, the method for setting up illusory modular construction on semiconductor device as claimed in claim 1 is characterized in that, this method further comprises the following step:

Further set up the processing simulation device.

3, the method for setting up illusory modular construction on semiconductor device as claimed in claim 1 is characterized in that, this method further comprises the following step:

According to average contact hole size decision metal layout density;

Determine the standard deviation of this metal layout density; And

Calculate the totalling of average metal layout density criterion difference.

4, the method for on semiconductor device, setting up illusory modular construction as claimed in claim 1, it is characterized in that, this process specification comprises the specification of metallics, interlayer dielectric material, grinding technics instrument and grinding technics parameter, wherein the process specifications of this grinding technics instrument comprises grinding pad hardness and lapping liquid composition, and wherein the process specifications of this grinding technics parameter is set grinding pressure and ground selectivity.

5, the method for setting up illusory modular construction on semiconductor device as claimed in claim 1 is characterized in that, this test structure comprises the Kai Shi resistor.

6, the method for on semiconductor device, setting up illusory modular construction as claimed in claim 1, it is characterized in that, this metal assembly irregularly shaped be following in any: square, rectangle, the capable matrix-like of square, intermittently linear, dotted line shape, circle, triangle, polygonal, cross.

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