CN100524170C - Controller for controlling memory to low power consumption mode and control method therefor - Google Patents
Controller for controlling memory to low power consumption mode and control method therefor Download PDFInfo
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- CN100524170C CN100524170C CNB2006100905292A CN200610090529A CN100524170C CN 100524170 C CN100524170 C CN 100524170C CN B2006100905292 A CNB2006100905292 A CN B2006100905292A CN 200610090529 A CN200610090529 A CN 200610090529A CN 100524170 C CN100524170 C CN 100524170C
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Abstract
The invention provides a controller for making storage device enter into low power consumption mode and a control method. The invention is characterized in that the status controller can automatically generate low power consumption mode control signal after CPU completes read/write on storage device with low power consumption, and control the storage device enter into low power consumption mode; when read/write operation finished, the status controller sends reset signal to interrupt generator which start to time according to the reset signal and sends out an interrupt signal to the status controller when it gets to pre-set time value, and then the status controller generates a low power consumption control signal according to the interrupt signal and send it to the storage device.
Description
Technical field
The present invention relates to Low-power Technology, particularly relate to controller and control method that a kind of control store enters low-power consumption mode.
Background technology
Owing to be subjected to battery powered restriction, mobile devices such as mobile phone are to storer, as: the power consumption of synchronous DRAM (SDRAM) requires very high.SDRAM is a memory device important in the mobile device, and special battery saving mode or low-power consumption mode can be provided, such as power-off (POWERDOWN) pattern, self-refresh (Selfrefresh) pattern etc.
In general, the storer that SDRAM etc. have the low-power consumption function only provides low-power consumption mode, and control store enters low-power consumption mode and then need be realized by special software.The basic thought that utilizes the software control storer to enter low-power consumption mode is: whether need use storer, if desired, then control store enters normal mode of operation if detecting mobile device in real time; Otherwise control store enters low-power consumption mode.Use storer described here is meant that mobile device realizes in the process of certain function, needs storer to participate in.Such as: the video data of MP4 is stored among the SDRAM, when mobile device is realized the MP4 function, will use SDRAM inevitably, promptly needs SDRAM to participate in.At this moment, when software detection starts the MP4 video capability to mobile device, will send an instruction that enters normal mode of operation to SDRAM; When software detection when mobile device is closed the MP4 video capability, then send an instruction that enters low-power consumption mode to SDRAM.Certainly, in the practical application, software can't be directly sends instruction to SDRAM, generally is that the CPU by mobile device carries out the instruction that control SDRAM enters normal mode of operation or enters low-power consumption mode, by CPU to the SDRAM transmitting control commands.
In the practical application, when mobile device used SDRAM, when promptly software control SDRAM entered normal mode of operation, CPU carried out read/write operation to SDRAM always, generally can have certain free time between double read/write operation.Such as: mobile device is in the process of playing the MP4 video frequency program, and CPU reads a batch data from SDRAM, and saves the data in the buffer memory.Afterwards, CPU directly from buffer memory reading of data play, play by the time after the data in the buffer memory, just from SDRAM, read the next group data once more, and the rest may be inferred.
That is to say that in the prior art, double between the memory read/write data as CPU, in fact storer is in idle condition, but owing to be in the mode of operation by software control, power consumption is still than higher.
This shows that when mobile device need use storer, prior art can't reduce the storer power consumption of free time.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of control store to enter the controller of low-power consumption mode, can make storer enter low-power consumption mode in making memory-aided process, reduces the power consumption of storer during the free time.
At the device that the present invention proposes, the method that the present invention also provides a kind of control store to enter low-power consumption mode can make storer enter low-power consumption mode in making memory-aided process, reduces the power consumption of storer during the free time.
At first goal of the invention, the technical scheme that the present invention proposes is:
A kind of control store enters the controller of low-power consumption mode, and this controller comprises at least:
Interrupt generator, be used to receive from the reset signal of state controller and pick up counting, when reaching the Preset Time value, export look-at-me to state controller;
State controller, be used for when the memory read/write EO to interrupting generator output reset signal, reception is from the look-at-me of interrupting generator, determine the numbering of the low-power consumption mode that storer will enter, and export to storer according to the numbering generation low-power consumption mode control signal of described low-power consumption mode;
Wherein, described state controller comprises:
Core controller is used for receiving the look-at-me of described interruption generator input to described interruption generator output reset signal, and the numbering of the low-power consumption mode that storer will be entered is exported to the control signal maker;
The control signal maker is used for producing the low-power consumption mode control signal according to the pattern numbering by the core controller input, and exports to storer.
Preferably, described interruption generator comprises:
Timer is used to receive from the reset signal of state controller and picks up counting, and exports look-at-me to state controller when the Preset Time value that is provided by the timer configuration register is provided;
The timer configuration register is used to preserve the Preset Time value that is solidificated in self in advance or is write by CPU, and the Preset Time value is offered timer.
Preferably, described timer is the timer that comprises one or more comparers;
Described timer configuration register is for preserving the timer configuration register of one or more Preset Time values.
Preferably, described state controller further comprises:
Memory status register, the pattern that is used for the current low-power consumption mode of record storage is numbered;
Described core controller is further used for reading from memory status register the pattern numbering of the current low-power consumption mode of storer, with the next one numbering of the numbering of the current low-power consumption mode numbering as the low-power consumption mode that will enter, and the numbering of the low-power consumption mode that storer will be entered is exported to memory status register.
Preferably, described storer is synchronous DRAM SDRAM.
At second goal of the invention, the technical scheme that the present invention proposes is:
A kind of control store enters the method for low-power consumption mode, and the Preset Time value is set earlier, and when the memory read/write EO, this method is further comprising the steps of:
A, state controller send reset signal to interrupting generator;
B, interruption generator begin to carry out timing according to reset signal, and send look-at-me to state controller when arriving the Preset Time value;
C, state controller are determined the numbering of the low-power consumption mode that storer will enter according to look-at-me, comprise: the numbering that directly will be kept at the low-power consumption mode that the pattern numbering in the memory status register in the state controller will enter as storer in advance, perhaps, the pattern numbering of the current low-power consumption mode of storer that writes down in the memory status register in elder generation's query State controller, the next one that present mode is numbered is numbered the numbering of the low-power consumption mode that will enter as storer again;
Numbering according to described low-power consumption mode produces the low-power consumption mode control signal, sends to storer.
Preferably, described Preset Time value is one or more Preset Time values.
Preferably, the described method that the Preset Time value is set is: the Preset Time value is solidificated in interrupts perhaps writing the interruption generator by CPU in the generator.
Preferably, described storer is SDRAM.
In sum, a kind of control store of proposing of the present invention controller and control method of entering low-power consumption mode has the following advantages:
(1) because state controller can be after CPU finishes memory read/write operations, send the low-power consumption mode control signal to storer, be that control store enters low-power consumption mode, so, even storer just uses at mobile device, free time reaches certain limit between the double read/write operation but need only, and just can enter low-power consumption mode, reaches the purpose of the further saving mobile device energy content of battery.
(2) the present invention can be provided with a plurality of Preset Time values in interrupting generator, and state controller is according to the storer difference of free time, and control store enters different low-power consumption modes.Free time, storer entered the higher but simple low-power consumption mode of process of power consumption in short-term, and free time is long more, and storer then enters the lower but low-power consumption mode of process complexity of power consumption.Like this, if storer just need carry out read/write operation through of short duration free time, can withdraw from low-power consumption mode very soon and enter normal mode of operation; If the free time of storer is very long, just can enter the lower low-power consumption mode of power consumption, reach the purpose that reduces power consumption to greatest extent.
(3) the Preset Time value of interrupting in the generator not only can be solidified in advance, can also be write by CPU, and the condition that control store enters low-power consumption mode can be set flexibly.
Description of drawings
Fig. 1 is the system architecture synoptic diagram that control store enters the controller place of low-power consumption mode;
Fig. 2 is the basic structure synoptic diagram of the controller that control store enters low-power consumption mode among the present invention;
Fig. 3 is the basic structure synoptic diagram of device embodiment one;
Fig. 4 is the present invention program's a process flow diagram;
Fig. 5 is a process flow diagram of using the present invention program's scheme implementation example.
Embodiment
For making the purpose, technical solutions and advantages of the present invention clearer, the present invention is described in further detail below in conjunction with the accompanying drawings and the specific embodiments.
Among the present invention, the low-power consumption mode controller is after CPU finishes memory read/write operations, produces the low-power consumption mode control signal, and control store enters corresponding low-power consumption mode.
Fig. 1 has shown the system architecture synoptic diagram at low-power consumption mode controller place among the present invention.As shown in Figure 1, this system comprises CPU, low-power consumption mode controller, storer.In the practical application, when CPU will carry out read/write to storer, will send out read, storer will be carried out read/write operation, data be read from storer or in the writing data into memory to storer.Owing to can specify the byte number of read/write in the read, and generally fix, roughly several clock period the time of a byte of read/write.So when CPU carried out read/write operation to storer, the low-power consumption mode controller can be determined the correct time that this read/write operation finishes, thereby can enter low-power consumption mode by control store when read/write operation finishes.
Storer described here promptly can provide the storer of low-power consumption function for having electricity-saving function, as SDRAM, mobile RAM etc.
Wherein, the basic structure of low-power consumption mode controller as shown in Figure 2.Among the present invention, the low-power consumption mode controller comprises interruption generator 201 and state controller 202 at least.
When memory read/write operations finished, state controller 202 was to interrupting generator 201 output reset signals; Interrupt just picking up counting after generator 201 receives reset signal from state controller 202, and when reaching the Preset Time value to state controller 202 output look-at-mes; When state controller 202 receives from the look-at-me of interruption generator 201, produce the low-power consumption mode control signal and also export to storer.When state controller 202 sent to storer with the low-power consumption mode control signal, storer just can enter corresponding low-power consumption mode according to described low-power consumption mode control signal.
In the practical application, the storer with low-power consumption function may provide one or more low-power consumption modes.If storer can provide more than one low-power consumption modes, then state controller 202 will produce the control signal that instruction memory enters a certain low-power consumption mode.The form of described low-power consumption mode control signal is relevant with concrete storer, if having the storer of low-power consumption function can the status recognition controller the 202 low-power consumption mode control signals that send.
Such as: if control SDRAM enters low-power consumption mode, then the low-power consumption mode control signal that sends to SDRAM of state controller 202 can the JEDEC standard except following the electronic component industrial combination, also supports the specific criteria etc. of manufacturer's proposition of the SDRAM that uses.How to enter low-power consumption mode as for SDRAM and then belong to prior art, the present invention no longer is described in detail.
Fig. 3 has shown the basic structure synoptic diagram of a kind of embodiment of device of the present invention.In the present embodiment, the low-power consumption mode controller will be controlled SDRAM and enter low-power consumption mode.As shown in Figure 3, interrupt generator 201 and comprise timer configuration register 301 and timer 302, state controller 202 comprises core controller 303, control signal maker 304, SDRAM status register 305.Wherein,
Low-power consumption mode control signal described here is to number one to one with pattern, the corresponding relation between pattern numbering and the low-power consumption mode control signal that will produce can be kept in the control signal maker 304 in advance.The pattern that receives core controller 303 inputs when control signal maker 304 is numbered, and can directly produce corresponding low-power consumption mode control signal according to corresponding relation.
When the SDRAM read-write operation finished, core controller 303 was to timer 302 output reset signals; Timer 302 picks up counting, and exports look-at-mes to core controller 303 when reaching the Preset Time value; Core controller 303 reads the pattern numbering of the current low-power consumption mode of SDRAM in the SDRAM status register 305, determine that SDRAM will enter the pattern numbering of low-power consumption mode next time, the pattern numbering that SDRAM will be entered next time low-power consumption mode is exported to control signal maker 304, and the pattern numbering that SDRAM will be entered next time low-power consumption mode is recorded in the SDRAM status register 305 as the current state of SDRAM; Control signal maker 304 produces the low-power consumption mode control signal according to the pattern numbering, and exports to SDRAM.
In the practical application, interrupt in the generator 201 timer configuration register 301 being arranged, also can not have timer configuration register 301.If there is not timer configuration register 301, timer 302 can be represented described Preset Time value by ground connection and the mode that connects power supply.Such as: connect the bit representation " 1 " of power supply, the bit representation of ground connection " 0 ".If the Preset Time value is 5, be shown 101 with binary form, then the 2nd and the 0th of timer input end can be connect power supply, the 1st ground connection.At this moment, timer 302 itself just can serve as an interruption generator.
If timer configuration register 301 is arranged, can in advance described Preset Time value be solidificated in the timer configuration register 301, and do not change the Preset Time value at the controller duration of work, also can write the Preset Time value by CPU according to actual conditions, timer 302 carries out work according to the Preset Time value that CPU writes.Afterwards, CPU can also write new Preset Time value to timer configuration register 301 according to actual conditions, and the Preset Time value that 302 bases of timer are new is carried out work.
In the practical application, SDRAM can provide one or more low-power consumption mode.If SDRAM provides a kind of low-power consumption mode, then have only a comparer in the timer 302, also have only a Preset Time value in the timer configuration register 301, and can not have SDRAM status register 305.That is to say that after timer 302 received the reset signal of core controller 303, timer 302 picked up counting, when comparer determined that the present timing value equates with the Preset Time value, timer 302 just sent look-at-me to core controller 303; Core controller 303 directly will be kept at the pattern numbering that SDRAM in self will enter low-power consumption mode in advance and export to control signal maker 304; Control signal maker 304 generates according to the pattern numbering and produces the low-power consumption mode control signal, and exports to SDRAM.Here, because SDRAM only provides a kind of low-power consumption mode, then core controller 303 can send to control signal maker 304 with certain numbering of fixing, and control signal maker 304 also only generates a kind of low-power consumption mode control signal.Certainly, what numbering of core controller 303 usefulness represents that low-power consumption mode can be definite voluntarily by application user of the present invention, as long as control signal maker 304 can be discerned.
If SDRAM can provide more than one low-power consumption mode, then comprise more than one comparer in the timer 302, more than one Preset Time value is arranged in the timer configuration register 301, and need be used to write down the SDRAM status register 305 of SDRAM current state.Here, there is relation one to one between comparer in Preset Time value, the timer 302 and the low-power consumption mode.Can provide three kinds of low-power consumption modes with SDRAM is example: comprise three comparers in the timer 302, three Preset Time value Ta, Tb and Tc are arranged in the timer configuration register 301, and Ta＜Tb＜Tc.Suppose to have corresponding relation between Preset Time value Ta, comparer 1 and the low-power consumption mode one; There is corresponding relation between Preset Time value Tb, comparer 2 and the low-power consumption mode two; There is corresponding relation between Preset Time value Tc, comparer 3 and the low-power consumption mode three.After timer 302 received the reset signal of core controller 303, timer 302 picked up counting, and in the process of timing, Ta offers comparer 1 and compares, and Tb offers comparer 2 and compares, and Tc offers comparer 3 and compares.When comparer 1 determined that the present timing value equates with Ta, timer 302 just sent look-at-me to core controller 303, and core controller 303 control SDRAM enter low-power consumption mode one.Afterwards, timer 302 still continues timing, and when comparer 2 determined that the present timing value equates with Tb, timer 302 sent look-at-me to core controller 303 again, and core controller 303 control SDRAM enter low-power consumption mode two, and push away class successively.
Use the present embodiment scheme, can control SDRAM and enter different low-power consumption modes.In actual applications, also can control other storeies such as mobile RAM and enter low-power consumption mode, thereby reach the purpose of the further saving mobile device energy content of battery with low-power consumption function.Certainly, state controller 202 is not to comprise SDRAM status register 305 just at this moment, and other has the memory status register 305 of low-power consumption functional memory state but be replaced by record.
At device provided by the invention, the present invention also proposes the control method that a kind of control store enters low-power consumption mode.
Basic thought of the present invention is: state controller finishes the back in memory read/write operations and sends the low-power consumption mode control signal to storer, and control store enters low-power consumption mode.
Fig. 4 has shown process flow diagram of the present invention.Among the present invention, earlier set in advance time value in interrupting generator, as CPU during to the memory read/write EO, the method that control store of the present invention enters low-power consumption mode may further comprise the steps:
Step 401: state controller is to interrupting generator output reset signal;
Step 402: interrupt beginning to carry out timing after generator receives reset signal, and when arriving the Preset Time value, export look-at-me to state controller;
Step 403: state controller produces the low-power consumption mode control signal according to look-at-me, and sends to storer.
Storer of the present invention is the storer with low-power consumption function, as: SDRAM etc.
In the practical application, storer with low-power consumption function may provide one or more low-power consumption mode, then among the present invention, state controller produces the control signal of corresponding different low-power consumption modes according to look-at-me, and storer can enter different low-power consumption modes according to different low-power consumption mode control signals.The form of described low-power consumption mode control signal is relevant with concrete storer, can discern this low-power consumption mode control signal as long as have the storer of low-power consumption function.
Such as: to low-power consumption mode control signal that SDRAM sends except follow the electronic component industrial combination can the JEDEC standard, also to follow the standard of employed SDRAM manufacturer.How to enter low-power consumption mode as for storeies such as SDRAM and then belong to prior art, the present invention no longer is described in detail.
In the practical application, the number of the Preset Time value that is provided with and size can be determined voluntarily by the user who uses the present invention program in advance.In general, the number of Preset Time value provides the number of low-power consumption mode to equate with storer.As: storer provides three kinds of low-power consumption modes, then needs to be provided with three Preset Time values, and the corresponding a kind of low-power consumption mode of each Preset Time value.The size of Preset Time value then can be determined adjacent twice actual conditions such as read/write operation time interval T of storer according to CPU.In general, have at least the Preset Time value should be less than adjacent twice read/write operation time interval of storer.Certainly, if adjacent twice read/write operation time interval of storer is long, then more than one time preset value all can be set to less than the storer value in adjacent twice read/write operation time interval.
Fig. 5 has shown the process flow diagram of a kind of embodiment of the inventive method.In the present embodiment, the low-power consumption mode controller will send the low-power consumption mode control signal to SDRAM, promptly control SDRAM and enter different low-power consumption modes.SDRAM can provide three kinds of low-power consumption modes, i.e. pattern one, pattern two and pattern three; CPU writes the interruption generator with three Preset Time values in advance, and these three Preset Time values are respectively Ta, Tb and Tc, and Ta＜Tb＜Tc.In the present embodiment, Ta associative mode one, Tb associative mode two, Tc associative mode three.That is to say that if clocking value reaches Ta, State Control will be controlled SDRAM and enter first kind of low-power consumption mode; If clocking value reaches Tb, State Control will be controlled SDRAM and enter second kind of low-power consumption mode; If clocking value reaches Tc, State Control will be controlled SDRAM and enter the third low-power consumption mode.
In addition, in the present embodiment, the low-power consumption mode of SDRAM is represented with numbering, that is: is represented normal mode of operation with 000,001 expression pattern, one, 010 expression pattern, two, 011 expression patterns three.When CPU carried out read/write operation to SDRAM, state controller was recorded as 000 with the current state of SDRAM; When control SDRAM entered different low-power consumption modes, then the current state with SDRAM was recorded as 001,010 or 011.
As shown in Figure 5, when CPU finished the read/write of SDRAM, the method that present embodiment control SDRAM enters low-power consumption mode may further comprise the steps:
Step 501: state controller sends reset signal to interrupting generator, interrupts generator and begins to carry out timing;
Step 502: interrupt generator and when the present timing value reaches the Preset Time value, send look-at-me to state controller;
Step 503: the pattern numbering of the current low-power consumption mode of state controller query note SDRAM, the pattern numbering that again next one numbering of present mode numbering will be entered next time low-power consumption mode as SDRAM;
Step 504: state controller generates the low-power consumption mode control signal according to the pattern numbering, and sends to SDRAM.
Present embodiment has three different Preset Time value Ta, Tb and Tc, carries out the size of the interval T of read/write operation time according to the adjacent twice couple of SDRAM of CPU, then controls SDRAM and enters low-power consumption mode following three kinds of different situations are arranged:
If Ta＜T＜Tb only needs execution in step 502～step 504 once.That is to say, interrupt generator and after resetting, pick up counting, and when timing arrives Ta, send look-at-me to state controller; The pattern of the current low-power consumption mode of state controller query note SDRAM numbering determines that the SDRAM present mode is numbered 000, with the next one numbering of present mode numbering, i.e. and the 001 pattern numbering that next time will enter low-power consumption mode as SDRAM; State controller generates corresponding low-power consumption mode control signal according to pattern numbering 001, sends to SDRAM, and control SDRAM enters pattern one.After SDRAM enters pattern one, interrupt generator and will continue timing, but since no show Tb during the time CPU initiate read/write operation to SDRAM, then SARAM immediately Be Controlled enter mode of operation, the SDRAM present mode is numbered and is registered as 000 again.
If Tb＜T＜Tc then needs repeated execution of steps 502～step 504 once.That is to say, elder generation enters after the low-power consumption mode one according to above-mentioned first kind of situation control SDRAM, because CPU does not also initiate the read/write operation to SDRAM, then interrupt generator and will continue timing, when arriving Tb, timing by the time sends look-at-me to state controller once more; State controller is the pattern numbering of the current low-power consumption mode of query note SDRAM once more, determines that the SDRAM present mode is numbered 001, and with next one numbering, i.e. the 010 pattern numbering that next time will enter low-power consumption mode as SDRAM; State controller generates corresponding low-power consumption mode control signal according to pattern numbering 010, sends to SDRAM, and control SDRAM enters pattern two.After SDRAM enters pattern two, interrupt generator and will continue timing, but since no show Tc during the time CPU initiate read/write operation to SDRAM, then SARAM immediately Be Controlled enter mode of operation, the SDRAM present mode is numbered and is registered as 000 again.
If Tb＜T＜Tc then needs repeated execution of steps 502～step 504 twice, promptly SDRAM will be introduced into low-power consumption mode one, enter low-power consumption mode two again, enter low-power consumption mode three at last.That is to say, after entering low-power consumption mode two according to above-mentioned second kind of situation control SDRAM, because CPU does not also initiate the read/write operation to SDRAM, then interrupt generator and will continue timing, when arriving Tc, timing by the time sends look-at-me to state controller once more; State controller is the pattern numbering of the current low-power consumption mode of query note SDRAM once more, determines that the SDRAM present mode is numbered 010, and with next one numbering, i.e. the 011 pattern numbering that next time will enter low-power consumption mode as SDRAM; State controller generates corresponding low-power consumption mode control signal according to pattern numbering 011, sends to SDRAM, and control SDRAM enters pattern three.After the pattern of entering three, SDRAM will be in low power consumpting state always, till CPU initiates read/write operation to SDRAM.
In the practical application, which kind of low-power consumption mode of the corresponding SDRAM of each Preset Time value can be determined voluntarily by the user who uses the present invention program.In general, few more pattern that consumes energy is complicated more, and it is also consuming time more to return normal mode from low-power consumption mode.So pattern that can power consumption is low is corresponding with bigger Preset Time value.That is to say that SDRAM can be introduced into the power consumption height but fairly simple low-power consumption mode is waited until when long period CPU does not still carry out read/write, SDRAM enters and consumes energy low but the low-power consumption mode of more complicated.Like this, if SDRAM just need carry out read/write operation through of short duration free time, can withdraw from low-power consumption mode very soon and enter normal mode of operation; If the free time of SDRAM is very long, just can enter the lower low-power consumption mode of power consumption, reach the purpose that reduces power consumption to greatest extent.
In the practical application, if SDRAM only provides a kind of low-power consumption mode, then state controller need not to write down that SDRAM is current is in any low-power consumption mode, only need be after receiving look-at-me, directly the pattern numbering of sending out fixing to SDRAM promptly directly will be kept at the numbering that the pattern numbering in self will enter low-power consumption mode as SDRAM next time in advance.Such as: can stipulate " 1 " low-power consumption mode numbering, after state controller receives look-at-me, directly produce the low-power consumption mode control signal according to numbering " 1 " for SDRAM.
In addition, in the practical application, when state controller receives read from CPU, can send the control signal that withdraw from low-power consumption mode to SDRAM immediately, enter the normal mode of operation control signal then, control is to the read/write operation of SDRAM.
In sum, more than be preferred embodiment of the present invention only, be not to be used to limit protection scope of the present invention.Within the spirit and principles in the present invention all, any modification of being done, be equal to replacement, improvement etc., all should be included within protection scope of the present invention.
Claims (9)
1, a kind of control store enters the controller of low-power consumption mode, it is characterized in that, this controller comprises at least:
Interrupt generator, be used to receive from the reset signal of state controller and pick up counting, when reaching the Preset Time value, export look-at-me to state controller;
State controller, be used for when the memory read/write EO to interrupting generator output reset signal, reception is from the look-at-me of interrupting generator, determine the numbering of the low-power consumption mode that storer will enter, and export to storer according to the numbering generation low-power consumption mode control signal of described low-power consumption mode;
Wherein, described state controller comprises:
Core controller is used for receiving the look-at-me of described interruption generator input to described interruption generator output reset signal, and the numbering of the low-power consumption mode that storer will be entered is exported to the control signal maker;
The control signal maker is used for producing the low-power consumption mode control signal according to the pattern numbering by the core controller input, and exports to storer.
2, controller according to claim 1 is characterized in that, described interruption generator comprises:
Timer is used to receive from the reset signal of state controller and picks up counting, and exports look-at-me to state controller when the Preset Time value that is provided by the timer configuration register is provided;
The timer configuration register is used to preserve the Preset Time value that is solidificated in self in advance or is write by CPU, and the Preset Time value is offered timer.
3, controller according to claim 2 is characterized in that, described timer is the timer that comprises one or more comparers;
Described timer configuration register is for preserving the timer configuration register of one or more Preset Time values.
4, controller according to claim 1 is characterized in that, described state controller further comprises:
Memory status register, the pattern that is used for the current low-power consumption mode of record storage is numbered;
Described core controller is further used for reading from memory status register the pattern numbering of the current low-power consumption mode of storer, with the next one numbering of the numbering of the current low-power consumption mode numbering as the low-power consumption mode that will enter, and the numbering of the low-power consumption mode that storer will be entered is exported to memory status register.
According to each described controller of claim 1 to 4, it is characterized in that 5, described storer is synchronous DRAM SDRAM.
6, a kind of control store enters the method for low-power consumption mode, it is characterized in that, the Preset Time value is set earlier, and when the memory read/write EO, this method is further comprising the steps of:
A, state controller send reset signal to interrupting generator;
B, interruption generator begin to carry out timing according to reset signal, and send look-at-me to state controller when arriving the Preset Time value;
C, state controller are determined the numbering of the low-power consumption mode that storer will enter according to look-at-me, comprise: the numbering that directly will be kept at the low-power consumption mode that the pattern numbering in the memory status register in the state controller will enter as storer in advance, perhaps, the pattern numbering of the current low-power consumption mode of storer that writes down in the memory status register in elder generation's query State controller, the next one that present mode is numbered is numbered the numbering of the low-power consumption mode that will enter as storer again;
Numbering according to described low-power consumption mode produces the low-power consumption mode control signal, sends to storer.
7, method according to claim 6 is characterized in that, described Preset Time value is one or more Preset Time values.
8, method according to claim 6 is characterized in that, the described method that the Preset Time value is set is: the Preset Time value is solidificated in interrupts perhaps writing the interruption generator by CPU in the generator.
According to each described method of claim 6 to 8, it is characterized in that 9, described storer is SDRAM.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100905292A CN100524170C (en) | 2006-06-27 | 2006-06-27 | Controller for controlling memory to low power consumption mode and control method therefor |
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| CNB2006100905292A CN100524170C (en) | 2006-06-27 | 2006-06-27 | Controller for controlling memory to low power consumption mode and control method therefor |
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| CN100524170C true CN100524170C (en) | 2009-08-05 |
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Families Citing this family (6)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN100458663C (en) * | 2007-04-24 | 2009-02-04 | 北京中星微电子有限公司 | Control method for low-power consumption RAM and RAM control module |
| CN101639725B (en) * | 2008-07-31 | 2013-07-17 | 国际商业机器公司 | Device and method for processing instruction and executive control device used by same |
| US8417979B2 (en) * | 2010-12-23 | 2013-04-09 | Western Digital Technologies, Inc. | Method and system for progressive power reduction of inactive device while maintaining ready status with host |
| US8463970B2 (en) * | 2011-01-04 | 2013-06-11 | Qualcomm Incorporated | Method and system for managing sleep states of interrupt controllers in a portable computing device |
| KR20140122567A (en) * | 2013-04-10 | 2014-10-20 | 에스케이하이닉스 주식회사 | Semiconductor memory device including power on reset circuit |
| CN112234698A (en) * | 2020-08-03 | 2021-01-15 | 青岛鼎信通讯股份有限公司 | Design scheme for quickly entering low power consumption during power failure of electric energy meter |
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