CN100530144C - Method and device for preventing internal storage data from losing - Google Patents
Method and device for preventing internal storage data from losing Download PDFInfo
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- CN100530144C CN100530144C CNB200610137607XA CN200610137607A CN100530144C CN 100530144 C CN100530144 C CN 100530144C CN B200610137607X A CNB200610137607X A CN B200610137607XA CN 200610137607 A CN200610137607 A CN 200610137607A CN 100530144 C CN100530144 C CN 100530144C
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Abstract
This invention provides a method and device to avoid the loss of memory data, belonging to the field of processor, to solve such existing problems as lost memory data, low reliability and high cost during the period of CPU release, including the following steps: when CPU is released, delaying the release time and making the memory enter auto-refreshing state, ending delay and triggering CPU real release. The invention also provides a device, including delay module, auto-refreshing configuration module and release module, and memory data are not lost, not only enhancing the reliability of running software, but also improving the starting efficiency.
Description
Technical field
The present invention relates to field of processors, particularly a kind of method and apparatus that prevents that internal storage data from losing.
Background technology
Common DRAM (Dynamic Random Access Memory, dynamic RAM) (includes but not limited to DDR SDRAM (Double Data Rate Synchronous Dynamic Random Access Memory, the double-speed synchronous dynamic random access memory)) internal storage data is at CPU (Central ProcessingUnit, central processing unit) reseting period can only keep limited a period of time, and should the time according to different memory chips and different PCB (Printed Circuit Board, printed circuit board) design is different, the time that dram chip itself can guarantee is Millisecond, if the time of restarting after central processing unit resets is oversize, may cause central processing unit to restart the back internal storage data and become random value, thereby cause the reading of data mistake, influence the normal operation of intrasystem software and can not return to the preceding running status that resets.Because the existence of this problem, the processing that keeps with the laggard line data that resets before need resetting to central processing unit ensures that internal storage data is normal, satisfies the application need of running software in the system.
Be illustrated in figure 1 as the system architecture synoptic diagram of prior art one, reset pin by reset control circuit control CPU in the system makes cpu reset, system relies on length interval time (international standard is defined as 64ms and finishes refreshing of whole memory chip) of the obliterated data of DRAM internal memory own to keep internal storage data during cpu reset, and promptly CPU is from the time less than internal memory obliterated data time interval of resetting to startup.If the system discovery internal storage data occurs wrong then abandons former data, regenerate internal storage data.The place one's entire reliance upon intrinsic design of system of this technology is not controlled.
The shortcoming of prior art one is as follows:
Because the circuit board of different internal memory manufacturers design may be different, cause possibility interval time of the obliterated data of internal memory own different, therefore have unreliability, randomness; Only can satisfy general application, not good to the support requirement of carrier class high reliability; Compare before regenerating information that internal storage data may cause system operation and resetting, occur than big-difference, and can cause the software startup time of system elongated, cause catastrophic consequence sometimes---loss of traffic or business network fault.
Be illustrated in figure 2 as the system architecture synoptic diagram of prior art two, system adopts SRAM (Static Random AccessMemory, static random-access memory) memory chip carries out some special data storages, and the reset pin of controlling CPU by reset control circuit makes cpu reset.Because the SRAM self characteristics has determined SRAM will depend on the periodic refreshing of CPU unlike DRAM, even cpu reset can not cause loss of data in the sram memory chip yet.
The shortcoming of prior art two is as follows:
Sram memory chip particle finite capacity generally all less than the 2M byte, if need jumbo storage space, will multi-disc sram chip connection in series-parallel be realized, is subjected to the restriction of PCB size to bring difficulty to the PCB design; Also the price than SDRAM is expensive a lot of for the price of SRAM in addition, and therefore the Material Cost of exploitation also can rise at double.
Summary of the invention
In order to solve that internal storage data may be lost during cpu reset in the prior art, reliability is low and problem such as cost height, the invention provides a kind of method that prevents that internal storage data from losing, specifically may further comprise the steps:
Steps A: when CPU resets, postpone the reset time of described CPU by in reset control circuit, increasing delay cell, and make internal memory enter the self-refresh state;
Step B: finish to postpone, trigger described CPU and really reset.
The described step that postpones the reset time of described CPU by increase delay cell in reset control circuit is specially:
Reset control circuit transmission lag request signal is given the delay cell that increases in advance, and described delay cell picks up counting after receiving this signal, postpones the reset time of described CPU.
Described step B is specially:
Described delay cell finishes to postpone when timing arrives official hour, and the reset pin that triggers described CPU really resets described CPU.
The time of described delay resets to the time that described internal memory enters the self-refresh state greater than described CPU.
The described step that makes internal memory enter the self-refresh state is specially:
The interrupt pin that is triggered described CPU by reset control circuit is interrupted described CPU, when described CPU has detected the look-at-me generation, calling interrupt service routine sends the order that makes internal memory enter the self-refresh state and gives described internal memory, after described internal memory is received this order by data, address and control bus, the correlation behavior register is set makes described internal memory enter the self-refresh state.
The described step that makes internal memory enter the self-refresh state is specially:
At first in described CPU, increase state control circuit, when described CPU resets, send reset request to described state control circuit by reset control circuit, after described state control circuit is received this request, forbid the processor core operation, and the control store controller sends the order that makes internal memory enter the self-refresh state and gives described internal memory, after described internal memory is received this order by data, address and control bus, the correlation behavior register is set makes described internal memory enter the self-refresh state.
Described method also comprises:
Step C: system restart, the self-refresh recovering state with described internal memory in initialization procedure arrives normal read-write state.
The present invention also provides a kind of device that prevents that internal storage data from losing, and described device comprises:
Reset control circuit is used for when CPU resets, and postpones the reset time of described CPU by the delay cell that increases in advance;
The self-refresh configuration module is used for making when CPU resets internal memory to enter the self-refresh state;
Reseting module is used for the described cpu reset of real triggering after described internal memory enters the self-refresh state.
Described self-refresh configuration module comprises:
Interrupt the self-refresh unit, be used for when CPU resets, trigger described CPU and interrupt and call interrupt service routine making internal memory enter the self-refresh state.
Described self-refresh configuration module comprises:
State Control self-refresh unit is used for when CPU resets, and makes internal memory enter the self-refresh state by state control circuit control store controller.
Described device also comprises:
Initialization module is used for after system restart, with the self-refresh recovering state of described internal memory to normal read-write state.
Beneficial effect of the present invention mainly shows:
By increasing the reset delay circuit, make internal memory enter the later CPU of self-refresh state and really reset again, can when resetting, CPU keep internal storage data not lose, not only strengthened the reliability of running software, also improved the starting efficiency of software.
Description of drawings
Fig. 1 is the system architecture synoptic diagram of prior art one;
Fig. 2 is the system architecture synoptic diagram of prior art two;
Fig. 3 is that the present invention prevents the method embodiment process flow diagram that internal storage data is lost;
Fig. 4 is that the present invention prevents the method embodiment processing procedure synoptic diagram that internal storage data is lost;
Fig. 5 is delay of the present invention and interrupt circuit structural representation;
Fig. 6 is delay of the present invention and state control circuit structural representation;
Fig. 7 is that the present invention prevents the method embodiment system state change synoptic diagram that internal storage data is lost;
Fig. 8 is that the present invention prevents the device example structure figure that internal storage data is lost.
Embodiment
The invention will be further described below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Reset control circuit among the present invention can adopt outer watchdog of the prior art to reset, external signal (button) directly resets to the cpu reset pin, or the watchdog reset of CPU own etc., also can adopt the software reset of system call or software anomaly to reset etc.
Save as the DRAM internal memory among the present invention.
Referring to Fig. 3, the invention provides a kind of method that prevents that internal storage data from losing, specifically may further comprise the steps:
Step 101: when CPU resets, trigger the external interrupt of CPU, and the time that will reset postpone a period of time backward, when CPU has detected look-at-me and produces, call interrupt service routine and make internal memory enter the self-refresh state;
The time that postpones carries out according to predefined value, is set to usually begin to enter time of self-refresh state to internal memory greater than the i.e. interruption that resets from CPU; For example resetting to the time that internal memory enters the self-refresh state from CPU is 2ms, then can be set to 3ms time delay, as long as greater than 2ms;
The operation that postpones realizes that by increase delay cell in reset control circuit as shown in Figure 4, the input end of delay cell links to each other with the output terminal of reset control circuit, and output terminal links to each other with the reset pin of CPU; When CPU resets, reset control circuit transmission lag request signal is given delay cell, the startup timer picked up counting after delay cell was received this signal, according to predefined value control lag a period of time, after internal memory enters the self-refresh state, trigger the reset pin of CPU again by delay cell, CPU is really resetted;
The external interrupt of CPU is triggered by reset control circuit, and the output terminal of reset control circuit links to each other with the interrupt pin of CPU, and when CPU resetted, reset control circuit triggered the interrupt pin of CPU, and notice CPU interrupts;
Make internal memory enter the self-refresh state and generally realize, as readjustment (hook) function by the correlation behavior register of function setup internal memory; During the self-refresh state, internal memory no longer relies on the periodic refreshing of CPU and keeps internal storage data, but internal memory oneself is kept data, thereby the guarantee internal storage data is not lost; After internal memory enters the self-refresh state, then withdraw from interrupt service routine;
Step 102: when the timer timing of delay cell arrives the default time, after promptly internal memory enters the self-refresh state, postpone promptly to finish, the reset pin by delay cell triggering CPU makes CPU really begin to reset; Therefore resetting of CPU will can not influence the self-refresh of internal memory this moment, also can not cause the unusual or situation such as lose of internal storage data to take place;
After step 103:CPU really resetted, system restart, and carry out initialization detected the state of internal memory by software (as the Boot rom software) in initialized process, and with internal storage state from the self-refresh recovering state to normal read-write state.
Trigger the external interrupt of CPU in the present embodiment step 101, call the mode that interrupt service routine makes internal memory enter the self-refresh state and can be replaced by the mode that hardware circuit is realized, as shown in Figure 5, implementation procedure is as follows:
Increase state control circuit in CPU, its input end links to each other with the output terminal of reset control circuit, and its output terminal links to each other with processor CORE (nuclear), and another output terminal links to each other with MEMORY (storage) controller;
When CPU resets, at first send reset request, the notify status control circuit by reset control circuit; After state control circuit has notice, forbid processor CORE operation, and control the MEMORY controller and send the order that makes internal memory enter the self-refresh state that after this order was passed to internal memory by data, address and control bus, internal memory promptly entered the self-refresh state.
Referring to Fig. 6, the present embodiment software and hardware cooperates processing procedure as follows:
When reset trigger person triggers CPU and resets, trigger the CPU external interrupt, by reset control circuit notice delay units delay a period of time, the work of treatment before really resetting simultaneously promptly changes the state of DRAM internal memory, makes it become the self-refresh state; In case internal memory enters the self-refresh state, just finish the time of delay, the reset pin by delay cell triggering CPU makes CPU really begin to reset; After CPU really resets, system restart, and carry out initialization, in initialized process with internal storage state from the self-refresh recovering state to normal read-write state.
No matter be software interrupt mode, or the hardware controls mode, in the above-mentioned cpu reset process, the state variation of CPU and DRAM internal memory is as shown in Figure 7.Wherein state 1 is the CPU normal operating condition, and save as normal read in the DRAM and write state this moment.When detecting (when having look-at-me or reset request to produce) when resetting, CPU gets the hang of 2, the state that is about to reset, and this moment, the DRAM internal memory entered the self-refresh state.After delay circuit is postponed the regular hour, trigger CPU and really reset, thereby make CPU get the hang of 3, the state during carrying out of promptly resetting, this moment, the DRAM internal memory kept the self-refresh state.System restart and initialization behind the cpu reset, CPU entered normal operating condition again after initialization was finished, and the DRAM internal memory also reverts to the support read-write state, has promptly got back to state 1 again.
Even from the cpu reset to the system restart, needing to occur situation for a long time in the present invention, can ensure that also internal storage data do not lose in the central processing unit reseting procedure.
Referring to Fig. 8, the present invention also provides a kind of device that prevents that internal storage data from losing, and specifically comprises:
(1) Postponement module is used for postponing the reset time of CPU when CPU resets;
(2) self-refresh configuration module is used for making when CPU resets internal memory to enter the self-refresh state;
(3) reseting module is used for the real cpu reset that triggers after internal memory enters the self-refresh state.
When adopting software mode, the self-refresh configuration module comprises:
Interrupt the self-refresh unit, be used for when CPU resets, trigger CPU and interrupt and call interrupt service routine making internal memory enter the self-refresh state.
When adopting hardware mode, the self-refresh configuration module comprises:
State Control self-refresh unit is used for when CPU resets, and makes internal memory enter the self-refresh state by state control circuit control store controller.
Device also comprises:
Initialization module is used for after system restart, with the self-refresh recovering state of internal memory to normal read-write state.
Above-described embodiment, the present invention embodiment a kind of more preferably just, the common variation that those skilled in the art carries out in the technical solution of the present invention scope and replacing all should be included in protection scope of the present invention.
Claims (11)
1. a method that prevents that internal storage data from losing is characterized in that, described method specifically may further comprise the steps:
Steps A: when CPU resets, postpone the reset time of described CPU by in reset control circuit, increasing delay cell, and make internal memory enter the self-refresh state;
Step B: finish to postpone, trigger described CPU and really reset.
2. the method that prevents that internal storage data from losing according to claim 1 is characterized in that, the described step that postpones the reset time of described CPU by increase delay cell in reset control circuit is specially:
Reset control circuit transmission lag request signal is given the delay cell that increases in advance, and described delay cell picks up counting after receiving this signal, postpones the reset time of described CPU.
3. the method that prevents that internal storage data from losing according to claim 2 is characterized in that, described step B is specially:
Described delay cell finishes to postpone when timing arrives official hour, and the reset pin that triggers described CPU really resets described CPU.
4. the method that prevents that internal storage data from losing according to claim 1 is characterized in that the time of described delay resets to the time that described internal memory enters the self-refresh state greater than described CPU.
5. according to the described method that prevents that internal storage data from losing of arbitrary claim in the claim 1 to 4, it is characterized in that the described step that makes internal memory enter the self-refresh state is specially:
The interrupt pin that is triggered described CPU by reset control circuit is interrupted described CPU, when described CPU has detected the look-at-me generation, calling interrupt service routine sends the order that makes internal memory enter the self-refresh state and gives described internal memory, after described internal memory is received this order by data, address and control bus, the correlation behavior register is set makes described internal memory enter the self-refresh state.
6. according to the described method that prevents that internal storage data from losing of arbitrary claim in the claim 1 to 4, it is characterized in that the described step that makes internal memory enter the self-refresh state is specially:
At first in described CPU, increase state control circuit, when described CPU resets, send reset request to described state control circuit by reset control circuit, after described state control circuit is received this request, forbid the processor core operation, and the control store controller sends the order that makes internal memory enter the self-refresh state and gives described internal memory, after described internal memory is received this order by data, address and control bus, the correlation behavior register is set makes described internal memory enter the self-refresh state.
7. according to the described method that prevents that internal storage data from losing of arbitrary claim in the claim 1 to 4, it is characterized in that described method also comprises:
Step C: system restart, the self-refresh recovering state with described internal memory in initialization procedure arrives normal read-write state.
8. a device that prevents that internal storage data from losing is characterized in that, described device comprises:
Reset control circuit is used for when CPU resets, and postpones the reset time of described CPU by the delay cell that increases in advance;
The self-refresh configuration module is used for making when CPU resets internal memory to enter the self-refresh state;
Reseting module is used for the described cpu reset of real triggering after described internal memory enters the self-refresh state.
9. the device that prevents that internal storage data from losing according to claim 8 is characterized in that, described self-refresh configuration module comprises:
Interrupt the self-refresh unit, be used for when CPU resets, trigger described CPU and interrupt and call interrupt service routine making internal memory enter the self-refresh state.
10. the device that prevents that internal storage data from losing according to claim 8 is characterized in that, described self-refresh configuration module comprises:
State Control self-refresh unit is used for when CPU resets, and makes internal memory enter the self-refresh state by state control circuit control store controller.
11. according to Claim 8, the 9 or 10 described devices that prevent that internal storage data from losing, it is characterized in that described device also comprises:
Initialization module is used for after system restart, with the self-refresh recovering state of described internal memory to normal read-write state.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB200610137607XA CN100530144C (en) | 2006-11-01 | 2006-11-01 | Method and device for preventing internal storage data from losing |
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| CNB200610137607XA CN100530144C (en) | 2006-11-01 | 2006-11-01 | Method and device for preventing internal storage data from losing |
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| CN1945555A CN1945555A (en) | 2007-04-11 |
| CN100530144C true CN100530144C (en) | 2009-08-19 |
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Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
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| CN102290094B (en) * | 2011-07-01 | 2013-09-18 | 创新科存储技术（深圳）有限公司 | Low power consumption circuit for reliably keeping self-refresh state of memory |
| CN104615223A (en) * | 2013-11-01 | 2015-05-13 | 沈阳晨讯希姆通科技有限公司 | Resetting method of GSM (Global System of Mobile Communication) module |
| CN104866051B (en) * | 2014-02-24 | 2018-09-07 | 华为技术有限公司 | A kind of prediction dog resets method, microcontroller and the embedded system of generation |
| CN104978001A (en) * | 2014-04-09 | 2015-10-14 | 中兴通讯股份有限公司 | Reset management method and device |
| CN105608023A (en) * | 2014-10-29 | 2016-05-25 | 梅特勒-托利多(常州)测量技术有限公司 | Method and system for protecting DRAM stored data of embedded system software |
| CN104572198B (en) * | 2014-12-31 | 2018-04-10 | 华为技术有限公司 | A kind of service restoration method and device |
| CN110633166B (en) * | 2018-06-22 | 2023-03-21 | 迈普通信技术股份有限公司 | Reset device and reset method |
| CN109917887A (en) * | 2019-03-06 | 2019-06-21 | 深圳芯马科技有限公司 | A kind of digital reset circuit applied to MCU chip |
| CN109918223A (en) * | 2019-05-06 | 2019-06-21 | 深圳市钮为通信技术有限公司 | Cpu reset monitoring device |
| CN116701041B (en) * | 2023-07-27 | 2023-11-10 | 飞腾信息技术有限公司 | Memory data retention method, retention device and related equipment |
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