CN100543534C - Shift register and liquid crystal indicator - Google Patents
Shift register and liquid crystal indicator Download PDFInfo
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- CN100543534C CN100543534C CNB2007100728146A CN200710072814A CN100543534C CN 100543534 C CN100543534 C CN 100543534C CN B2007100728146 A CNB2007100728146 A CN B2007100728146A CN 200710072814 A CN200710072814 A CN 200710072814A CN 100543534 C CN100543534 C CN 100543534C
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Abstract
The invention provides the liquid crystal indicator of a kind of shift register and this shift register of employing.This liquid crystal indicator comprises a display panels, a data drive circuit and scan driving circuit, this data drive circuit provides data-signal for this display panels, this scan drive circuit provides sweep signal for this display panels, and this data drive circuit and this scan drive circuit comprise the output timing of a shift register with control data signal and sweep signal respectively.This shift register comprises a plurality of shifting deposit units of series connection successively, and each shifting deposit unit comprises a clock signal input pin, an inversion clock signal input pin, a signal input pin, a signal output pin, a high level power pins, a low level power pin and five transistors.This shift register account for the circuit layout space little, need not feedback signal and the output signal zero lap of back one-level shifting deposit unit as the previous stage shifting deposit unit.This liquid crystal indicator shows good.
Description
Technical field
The invention relates to the liquid crystal indicator of a kind of shift register and this shift register of employing.
Background technology
Liquid crystal indicator because of have low diathermaneity, characteristics such as volume is compact and power consumption is low, be widely used in fields such as mobile phone, personal digital assistant, notebook computer, PC and TV, and become the main product of present display device.Usually, LCD drive circuits comprises a data drive circuit and scan driving circuit.Data drive circuit is used to control the display brightness of each pixel cell, and scan drive circuit then is used for the conducting of control TFT and ends.Two driving circuits are all used shift register as its core circuit unit.Shift register is to be in series by a plurality of shifting deposit units, and the output signal of previous stage shifting deposit unit is the input signal of back one-level shifting deposit unit, and the output signal of back one-level shifting deposit unit is the feedback signal of previous stage shifting deposit unit.
Please refer to Fig. 1, it is a kind of circuit diagram of prior art shifting deposit unit.This shifting deposit unit 100 comprises a signal input part V
IN1, a signal output part V
OUT1, a clock signal input part CK, an inversion clock signal input part CKb, a high level power input V
DD, a low level power input end V
SS, a feedback signal input end V
OUT2, a first transistor 101, a transistor seconds 102, one the 3rd transistor 103, one the 4th transistor 104, one the 5th transistor 105 and one the 6th transistor 106.The grid of this first transistor 101 is electrically connected on this inversion clock signal input part CKb, and drain electrode is electrically connected on this signal input part V
IN1, source electrode is electrically connected on the grid of the 4th transistor 104; The grid of this transistor seconds 102 and drain electrode all are electrically connected on this high level power input V
DD, source electrode is electrically connected on the drain electrode of the 3rd transistor 103 and the grid of the 5th transistor 105 respectively; The grid of the 3rd transistor 103 is electrically connected on this signal output part V
OUT1, source electrode is electrically connected on this low level power input end V
SSThe drain electrode of the 4th transistor 104 is electrically connected on this clock signal input terminal CK, and source electrode is electrically connected on drain electrode and this signal output part V of the 5th transistor 105 respectively
OUT1The source electrode of the 5th transistor 105 is electrically connected on this low level power input end V
SSThe grid of the 6th transistor 106 is electrically connected on this feedback signal input end V
OUT2, drain electrode is electrically connected on this signal output part V
OUT1, source electrode is electrically connected on this low level power input end V
SS
In order to make the output V of this shifting deposit unit 100
OUT1Can rapid charge and discharge, the 4th transistor 104 of being responsible for charging must bear bigger electric current with the 5th, the 6th transistor 105,106 of being responsible for discharge, so its channel width is bigger, in general its width so will occupy sizable circuit layout space about about thousands of microns.
This shifting deposit unit 100 is to utilize next stage output V in addition
OUT2,, then do not have next stage and be output as its feedback signal to discharge as its feedback signal, then possibly can't discharge fully if this shifting deposit unit 100 is an afterbody.
Please refer to Fig. 2, it is these shifting deposit unit 100 place shift registers sequential synoptic diagram of (figure does not show).Wherein, curve 15 and 17 represent respectively (N-1) and N level shifting deposit unit output signal discharge and recharge situation, the N level is an afterbody, therefore the incomplete situation of discharging can occur, shown in empty frame 10.Be example with curve 15 again, the output signal of (N-1) level is about 25 μ s discharge time, and when the output signal of N level is charging, discharge is not fully yet, make the signal overlap of adjacent two-stage, shown in empty frame 12, and then cause adopting the liquid crystal indicator of this shift register as data drive circuit and scan drive circuit, when carrying out column scan or line scanning, the phenomenon that exists adjacent two column or row to scan simultaneously, cause output signal to produce the phase mutual interference, make picture produce aberration, cause liquid crystal indicator normally to show.
Summary of the invention
In order to overcome the problem that shift register in the prior art accounts for the big and signal overlap in circuit layout space, be necessary to provide a kind of account for the circuit layout space little, need not feedback signal and the output signal non-overlapping shift register of back one-level shifting deposit unit as the previous stage shifting deposit unit.
Also be necessary to provide a kind of and adopt above-mentioned shift register, show good liquid crystal indicator.
A kind of shift register, it comprises a plurality of shifting deposit units of series connection successively, and each shifting deposit unit comprises a clock signal input pin, an inversion clock signal input pin, a signal input pin, a signal output pin, a high level power pins, a low level power pin, a first transistor, a transistor seconds, one the 3rd transistor, one the 4th transistor and one the 5th transistor.In a shifting deposit unit, the drain electrode of this first transistor is electrically connected on this signal input pin, and grid is electrically connected on this inversion clock signal input pin, and source electrode is electrically connected on the 4th transistorized grid; The grid of this transistor seconds is electrically connected on this inversion clock signal input pin, and drain electrode is electrically connected on this high level power pins, and source electrode is electrically connected on the 3rd transistor drain; The 3rd transistorized grid is electrically connected on this clock signal input pin, and source electrode is electrically connected on this low level power pin; The 4th transistor drain is electrically connected on this clock signal input pin, and source electrode is electrically connected on the 5th transistor drain and this signal output pin; The 5th transistorized grid is electrically connected on the 3rd transistor drain, and source electrode is electrically connected on this low level power pin.In the shifting deposit unit adjacent with this shifting deposit unit, this clock signal input pin and this inversion clock signal position opposite that input pin connects.
A kind of liquid crystal indicator, it comprises a display panels, a data drive circuit and scan driving circuit, this data drive circuit provides data-signal for this display panels, this scan drive circuit provides sweep signal for this display panels, and this data drive circuit and this scan drive circuit comprise the output timing of a shift register with control data signal and sweep signal respectively.This shift register comprises a plurality of shifting deposit units of series connection successively, and each shifting deposit unit comprises a clock signal input pin, an inversion clock signal input pin, a signal input pin, a signal output pin, a high level power pins, a low level power pin, a first transistor, a transistor seconds, one the 3rd transistor, one the 4th transistor and one the 5th transistor.In a shifting deposit unit, the drain electrode of this first transistor is electrically connected on this signal input pin, and grid is electrically connected on this inversion clock signal input pin, and source electrode is electrically connected on the 4th transistorized grid; The grid of this transistor seconds is electrically connected on this inversion clock signal input pin, and drain electrode is electrically connected on this high level power pins, and source electrode is electrically connected on the 3rd transistor drain; The 3rd transistorized grid is electrically connected on this clock signal input pin, and source electrode is electrically connected on this low level power pin; The 4th transistor drain is electrically connected on this clock signal input pin, and source electrode is electrically connected on the 5th transistor drain and this signal output pin; The 5th transistorized grid is electrically connected on the 3rd transistor drain, and source electrode is electrically connected on this low level power pin.In the shifting deposit unit adjacent with this shifting deposit unit, this clock signal input pin and this inversion clock signal position opposite that input pin connects.
Compared to prior art, the used number of transistors of the shifting deposit unit of this shift register is few, it is little to account for the circuit layout space, and need not the feedback signal of back one-level shifting deposit unit as the previous stage shifting deposit unit, but by inversion clock input signal control transistor seconds, clock input signal is controlled the 3rd transistor, and then control the accurate position of the 5th transistorized grid voltage, output signal is periodically dragged down, to reduce or to avoid in a frame time, the 5th transistor drain that can be stored in electric charge causes the accurate position of output signal to rise influences output waveform, thereby can not cause the output signal of previous stage shifting deposit unit overlapping with the output signal of back one-level shifting deposit unit.
The used number of transistors of the shifting deposit unit of the shift register that this liquid crystal indicator adopts is few, it is little to account for the circuit layout space, and need not the feedback signal of back one-level shifting deposit unit as the previous stage shifting deposit unit, but by inversion clock input signal control transistor seconds, clock input signal is controlled the 3rd transistor, and then control the accurate position of the 5th transistorized grid voltage, output signal is periodically dragged down, to reduce or to avoid in a frame time, the 5th transistor drain that can be stored in electric charge causes the accurate position of output signal to rise influences output waveform, thereby can not cause the output signal of previous stage shifting deposit unit overlapping with the output signal of back one-level shifting deposit unit.So use the scan drive circuit of this shift register and data drive circuit when carrying out line scanning or column scan, its output scanning signal and data-signal can not produce signal and disturb, thereby avoid display frame aberration to occur, so this liquid crystal indicator show good.
Description of drawings
Fig. 1 is a kind of circuit diagram of prior art shifting deposit unit.
Fig. 2 is the sequential synoptic diagram of shifting deposit unit place shift register among Fig. 1.
Fig. 3 is the structural representation of shift register better embodiment of the present invention.
Fig. 4 is the circuit diagram of the shifting deposit unit of Fig. 3.
Fig. 5 is the sequential synoptic diagram of shift register among Fig. 1.
Fig. 6 is the structural representation that adopts the liquid crystal indicator of shift register among Fig. 3.
Embodiment
Please refer to Fig. 3, it is the structural representation of shift register better embodiment of the present invention.This shift register 20 comprises a plurality of shifting deposit units 200.These a plurality of shifting deposit units 200 are connected successively, and the output signal of previous stage shifting deposit unit 200 is the input signal of back one-level shifting deposit unit 200.Each shifting deposit unit 200 comprises a clock signal input pin CK, an inversion clock signal input pin CKb, a signal input pin V
IN, a signal output pin V
OUT, a high level power pins V
DDWith a low level power pin V
SSThe clock signal input pin CK of one shifting deposit unit 200 of this shift register 20 receives from the external circuit clock input signal CK of (figure does not show), its inversion clock signal input pin CKb receives the inversion clock input signal CKb from external circuit, its high level power pins V
DDBe electrically connected outside high level power supply (figure does not show), to keep high level, its low level power pin V
SSBe electrically connected outside low level power (figure does not show), to keep low level, its signal input pin V
INAs the signal input part of this shifting deposit unit 200, its signal output pin V
OUTBe electrically connected to the signal input pin V of back one-level shifting deposit unit 200
INThe connected mode of back one-level shifting deposit unit 200 is similar to it.
Please refer to Fig. 4, it is the circuit diagram of the shifting deposit unit 200 of Fig. 3.This shifting deposit unit 200 comprises a first transistor 201, a transistor seconds 202, one the 3rd transistor 203, one the 4th transistor 204, one the 5th transistor 205 and an impact damper (Buffer) 206.Above-mentioned five transistors all are NMOS (N-channelMetal-Oxide Semiconductor, N NMOS N-channel MOS N) transistor npn npns.The drain electrode of this first transistor 201 is electrically connected on this signal input pin V
IN, grid is electrically connected on this inversion clock signal input pin CKb, and source electrode is electrically connected on the grid of the 4th transistor 204; The grid of this transistor seconds 202 is electrically connected on this inversion clock signal input pin CKb, and drain electrode is electrically connected on this high level power pins V
DD, source electrode is electrically connected on the drain electrode of the 3rd transistor 203; The grid of the 3rd transistor 203 is electrically connected on this clock signal input pin CK, and source electrode is electrically connected on this low level power pin V
SSThe drain electrode of the 4th transistor 204 is electrically connected on this clock signal input pin CK, and source electrode is electrically connected on the drain electrode of the 5th transistor 205; The grid of the 5th transistor 205 is electrically connected on the drain electrode of the 3rd transistor 203, and source electrode is electrically connected on this low level power pin V
SSThe input end of this impact damper 206 is electrically connected on the source electrode of the 4th transistor 204, and output terminal is electrically connected on this signal output pin V
OUTThis impact damper 206 is to be formed by two phase inverter serial connections, is mainly used in the output waveform that keeps this shifting deposit unit 200, avoids the output waveform distortion.
Wherein, the grid of the upper level shifting deposit unit 200 adjacent with this shifting deposit unit 200 and first, second transistor 201,202 of next stage shifting deposit unit 200 is electrically connected on its clock signal input pin CK, and the drain electrode of the grid of the 3rd transistor 203 and the 4th transistor 204 is electrically connected on its inversion clock signal input pin CKb.Also be the clock signal input pin CK and the inversion clock signal input pin position opposite that CKb connects of adjacent shifting deposit unit 200.
Please in the lump with reference to figure 5, it is the sequential synoptic diagram of shift register 20 among Fig. 1.In a shifting deposit unit 200, at t1 constantly, clock input signal CK is a low level, and inversion clock input signal CKb is a high level, signal input pin V
INInput upper level output signal V
OUT1Be high level, be high level because of inversion clock input signal CKb this moment, first, second transistor 201,202 conductings, and the source electrode of this first, second transistor 201,202 is a high level, 204,205 conductings of the 4th, the 5th transistor; Because of clock input signal CK is a low level, the 3rd transistor 203 ends, and the source electrode of the 4th transistor 204 is a low level, after these impact damper 206 outputs, and its output signal V
OUT2Be low level.
At t2 constantly, clock input signal CK is a high level, and inversion clock input signal CKb is a low level, signal input pin V
INInput upper level output signal V
OUT1Be low level, be low level because of inversion clock input signal CKb this moment, and first, second transistor 201,202 ends, and the source electrode of this first transistor 201 is kept high level, 204 conductings of the 4th transistor; Because of clock input signal CK is a high level, 203 conductings of the 3rd transistor, its drain electrode is low level, the 5th transistor 205 ends; The source electrode of the 4th transistor 204 is a high level, after these impact damper 206 outputs, and its output signal V
OUT2Be high level.
At t3 constantly, clock input signal CK is a low level, and inversion clock input signal CKb is a high level, signal input pin V
INInput upper level output signal V
OUT1Be low level, be low level because of clock input signal CK this moment, and the 3rd transistor 203 ends; Being stranded inversion clock input signal CKb is high level, first, second transistor 201,202 conductings, the source electrode of this first transistor 201 is a low level, the source electrode of this transistor seconds 202 is a high level, the 4th transistor 204 ends, 205 conductings of the 5th transistor, and the source electrode of the 5th transistor 205 is a low level, after these impact damper 206 outputs, its output signal V
OUT2Be low level.
This moment this shifting deposit unit 200 the output V of next stage shifting deposit unit 200
OUT3Be high level.The next stage shifting deposit unit 200 of this shifting deposit unit 200 and the duty of other shifting deposit unit 200 are all similar to this shifting deposit unit 200.
The used number of transistors of the shifting deposit unit 200 of this shift register 20 is few, it is little to account for the circuit layout space, and need not back one-level shifting deposit unit 200 feedback signals as previous stage shifting deposit unit 200, but control the 3rd transistor 203 by inversion clock input signal CKb control transistor seconds 202, clock input signal CK, and then the accurate position of the grid voltage of controlling the 5th transistor 205, make output signal V
OUTPeriodically drag down, to reduce or to avoid in a frame time, the drain electrode that electric charge can be stored in the 5th transistor 205 causes output signal V
OUTAccurate position rise and influence output waveform, thereby can not cause the output signal V of previous stage shifting deposit unit 200
OUTOutput signal V with back one-level shifting deposit unit 200
OUTOverlapping.
This shift register 20 can be used in counter and other digital electronic product.Please refer to Fig. 6, it is the structural representation of the liquid crystal indicator of the above-mentioned shift register 20 of an employing.This liquid crystal indicator 2 comprises a display panels 21, a data drive circuit 22 and scan driving circuit 23.This display panels 21 comprises that a upper substrate (figure do not show), an infrabasal plate (figure does not show) and are held on the liquid crystal layer (figure does not show) between upper substrate and infrabasal plate, and is provided with one in contiguous liquid crystal layer one side of this infrabasal plate and is used to control the thin film transistor (TFT) array (figure does not show) that liquid crystal molecule reverses situation.This data drive circuit 22 and this scan drive circuit 23 comprise an above-mentioned shift register 20 respectively.These scan drive circuit 23 output scanning signals are given this display panels 21, and with conducting and the off state of controlling its film transistor matrix, these data drive circuit 22 outputting data signals are given this display panels 21, to control its display variation.This scan drive circuit 23 and this data drive circuit 22 all utilize the output timing of these shift register 20 gated sweep signals and data-signal, thereby control the demonstration of this display panels 21.This shift register 20 can form in same processing procedure with the thin film transistor (TFT) array of this display panels 21.
Because there is not the signal overlap phenomenon in the output of the shifting deposit units at different levels 200 of this shift register 20, so use the scan drive circuit 22 of this shift register 20 and data drive circuit 23 when carrying out line scanning or column scan, its output scanning signal and data-signal can not produce signal and disturb, thereby avoid display frame aberration to occur, so this liquid crystal indicator 2 show good.
Claims (10)
1, a kind of shift register, it comprises a plurality of shifting deposit units of series connection successively, it is characterized in that: each shifting deposit unit comprises a clock signal input pin, one inversion clock signal input pin, one signal input pin, one signal output pin, one high level power pins, one low level power pin, one the first transistor, one transistor seconds, one the 3rd transistor, one the 4th transistor and one the 5th transistor, in a shifting deposit unit, the drain electrode of this first transistor is electrically connected on this signal input pin, grid is electrically connected on this inversion clock signal input pin, and source electrode is electrically connected on the 4th transistorized grid; The grid of this transistor seconds is electrically connected on this inversion clock signal input pin, and drain electrode is electrically connected on this high level power pins, and source electrode is electrically connected on the 3rd transistor drain; The 3rd transistorized grid is electrically connected on this clock signal input pin, and source electrode is electrically connected on this low level power pin; The 4th transistor drain is electrically connected on this clock signal input pin, and source electrode is electrically connected on the 5th transistor drain and this signal output pin; The 5th transistorized grid is electrically connected on the 3rd transistor drain, and source electrode is electrically connected on this low level power pin; In the shifting deposit unit adjacent with this shifting deposit unit, this clock signal input pin and this inversion clock signal position opposite that input pin connects.
2, shift register as claimed in claim 1 is characterized in that: the output signal of previous stage shifting deposit unit is the input signal of back one-level shifting deposit unit.
3, shift register as claimed in claim 2, it is characterized in that: this clock signal input pin receives the clock input signal from external circuit, this inversion clock signal input pin receives the inversion clock input signal from external circuit, this high level power pins is electrically connected outside high level power supply, to keep high level, this low level power pin is electrically connected outside low level power, to keep low level.
4, shift register as claimed in claim 1, it is characterized in that: this shift register further comprises an impact damper, this impact damper is serially connected with between the 4th transistorized source electrode and the 5th transistor drain and this signal output pin, its input end is electrically connected on the 4th transistorized source electrode and the 5th transistor drain, and output terminal is electrically connected on this signal output pin.
5, shift register as claimed in claim 1 is characterized in that: this first to the 5th transistor is nmos type transistor.
6, a kind of liquid crystal indicator, it comprises a display panels, one data drive circuit and scan driving circuit, this data drive circuit provides data-signal for this display panels, this scan drive circuit provides sweep signal for this display panels, this data drive circuit and this scan drive circuit comprise the output timing of a shift register with control data signal and sweep signal respectively, this shift register comprises a plurality of shifting deposit units of series connection successively, it is characterized in that: each shifting deposit unit comprises a clock signal input pin, one inversion clock signal input pin, one signal input pin, one signal output pin, one high level power pins, one low level power pin, one the first transistor, one transistor seconds, one the 3rd transistor, one the 4th transistor and one the 5th transistor, in a shifting deposit unit, the drain electrode of this first transistor is electrically connected on this signal input pin, grid is electrically connected on this inversion clock signal input pin, and source electrode is electrically connected on the 4th transistorized grid; The grid of this transistor seconds is electrically connected on this inversion clock signal input pin, and drain electrode is electrically connected on this high level power pins, and source electrode is electrically connected on the 3rd transistor drain; The 3rd transistorized grid is electrically connected on this clock signal input pin, and source electrode is electrically connected on this low level power pin; The 4th transistor drain is electrically connected on this clock signal input pin, and source electrode is electrically connected on the 5th transistor drain and this signal output pin; The 5th transistorized grid is electrically connected on the 3rd transistor drain, and source electrode is electrically connected on this low level power pin; In the shifting deposit unit adjacent with this shifting deposit unit, this clock signal input pin and this inversion clock signal position opposite that input pin connects.
7, liquid crystal indicator as claimed in claim 6 is characterized in that: the output signal of previous stage shifting deposit unit is the input signal of back one-level shifting deposit unit.
8, liquid crystal indicator as claimed in claim 7, it is characterized in that: this clock signal input pin receives the clock input signal from external circuit, this inversion clock signal input pin receives the inversion clock input signal from external circuit, this high level power pins is electrically connected outside high level power supply, to keep high level, this low level power pin is electrically connected outside low level power, to keep low level.
9, liquid crystal indicator as claimed in claim 6, it is characterized in that: this shift register further comprises an impact damper, this impact damper is serially connected with between the 4th transistorized source electrode and the 5th transistor drain and this signal output pin, its input end is electrically connected on the 4th transistorized source electrode and the 5th transistor drain, and output terminal is electrically connected on this signal output pin.
10, liquid crystal indicator as claimed in claim 6 is characterized in that: this first to the 5th transistor is nmos type transistor.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100728146A CN100543534C (en) | 2007-01-05 | 2007-01-05 | Shift register and liquid crystal indicator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2007100728146A CN100543534C (en) | 2007-01-05 | 2007-01-05 | Shift register and liquid crystal indicator |
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| CN101216622A CN101216622A (en) | 2008-07-09 |
| CN100543534C true CN100543534C (en) | 2009-09-23 |
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| CNB2007100728146A Expired - Fee Related CN100543534C (en) | 2007-01-05 | 2007-01-05 | Shift register and liquid crystal indicator |
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| CN101996605B (en) * | 2010-11-18 | 2013-01-02 | 友达光电股份有限公司 | Gate driving circuit on liquid crystal panel |
| TWI488187B (en) * | 2012-11-30 | 2015-06-11 | Au Optronics Corp | Shift register and display apparatus |
| CN106328064B (en) * | 2016-09-28 | 2019-05-03 | 昆山工研院新型平板显示技术中心有限公司 | A kind of scan drive circuit |
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