CN100544550C - Be applied to the method for manufacturing circuit board of integrated circuit encapsulation - Google Patents
Be applied to the method for manufacturing circuit board of integrated circuit encapsulation Download PDFInfo
- Publication number
- CN100544550C CN100544550C CNB2006100837971A CN200610083797A CN100544550C CN 100544550 C CN100544550 C CN 100544550C CN B2006100837971 A CNB2006100837971 A CN B2006100837971A CN 200610083797 A CN200610083797 A CN 200610083797A CN 100544550 C CN100544550 C CN 100544550C
- Authority
- CN
- China
- Prior art keywords
- circuit
- integrated circuit
- encapsulation
- copper
- circuit board
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Manufacturing Of Printed Circuit Boards (AREA)
Abstract
A kind of method of manufacturing circuit board that is applied to the integrated circuit encapsulation before printed circuit board (PCB) carries out circuit etching, is done the circuit surface treatment earlier, and plates the metal level that meets integrated circuit encapsulation (COB) processing procedure; Use the area number when avoiding connecting up and produce the height current effect, and prevent the excessive phenomenon of integrated circuit encapsulation (COB) coat of metal difference; In addition, electroplated lead need not drawn in the metal surface that can encapsulate (COB) in integrated circuit, and finishes the metal level of (COB) processing procedure, and then the area that connects up when improving engineering design.
Description
Technical field
The invention provides a kind of method of manufacturing circuit board that is applied to the integrated circuit encapsulation, refer to a kind of integrated circuit encapsulation procedure that reduces cost especially.
Technical background
The manufacture method of traditional printing circuit board includes positive processing procedure and negative film processing procedure;
The manufacturing process of traditional positive wherein, as shown in Figure 3, its step comprises:
X1: chemical perforation: on copper circuit board, do chemical perforation (PTH), make its upper and lower layer copper face conducting;
X2: circuit is made: use liquid printing ink or photosensitive type printing ink, see through egative film and light source exposure principle and form circuit, remove the logicalnot circuit surface ink with chemical mode again, make this surface expose the copper layer partly;
X3: circuit etching: the copper layer utilization chemical corrosion decomposition principle that will expose is removed copper fully, and is stayed the circuit of printing ink protection;
X4: circuit surface treatment: after the circuit surface ink removal that stays, the copper face that will expose plates the metal level that meets integrated circuit encapsulation (COB) processing procedure on demand.
Behind the processing procedure by above-mentioned printed circuit board (PCB), can carry out the processing procedure of integrated circuit encapsulation (COB), at first, can draw lead, carry out the mold pressing sealing again, use and finish encapsulation procedure prior to the metal level of above-mentioned integrated circuit encapsulation (COB) processing procedure.
Yet, because printed circuit board (PCB) is in the etched step of circuit, after the copper layer of not wanting etched away, therefore, after the copper face that online road surfaces processing will go out plates the metal level that meets integrated circuit encapsulation (COB) processing procedure on demand, the lead that needs before to be serially connected with routing solder joint (bonding pad) is removed in the lump, and so processing procedure will be subjected to drawing lead to occupy the restriction of wiring area.
In addition because after the copper layer of not wanting etches away, can form positive and negative surface area copper surface inequality, and the little copper layer absorption current speed of area is very fast, the copper layer absorption current speed that area is bigger is slower, can make the formation thickness of coating inequality of the different copper layer of two areas, cause when back segment mold pressing manufacture procedure of adhesive, cause the situation of the glue that overflows because of thickness of slab is uneven.
In addition, the manufacturing process of traditional negative film as shown in Figure 4, comprises as its step:
Y1: chemical perforation: on copper circuit board, do chemical perforation (PTH), make its upper and lower layer copper face conducting;
Y2: circuit is made: use liquid printing ink or photosensitive type printing ink, see through egative film and light source exposure principle and form circuit, remove the circuit surface ink with chemical mode again, make this circuit table show the copper layer partly;
Y3: route protection: the circuit surface that will expose the copper layer directly plates the tin metal protective layer with electrolysis mode in the circuit surface, with the integrality of protection circuit;
Y4: circuit etching:, make it to remove fully clean and stay logicalnot circuit copper layer with the printing ink of logicalnot circuit copper laminar surface utilization chemical breakdown principle; With the chemical etching principle logicalnot circuit copper face is removed fully again, will be protected the tin metal layer to remove at last again and stay circuit copper layer;
Y5: circuit surface treatment: after the circuit surface ink removal that stays, the copper face that will expose plates the metal level that meets integrated circuit encapsulation (COB) processing procedure on demand.
The negative film processing procedure that above-mentioned printed circuit board (PCB) is traditional needs the step of many one route protections than the positive processing procedure, and after plating tin, also need the step of one stripping tin, so step is comparatively complicated, and manufacturing cost is also higher.
Edge this, the inventor is at the existing problem points of above-mentioned known printed circuit board (PCB), by research and the manufacturing development of being engaged in association area for many years, after design is assessed with discretion in detail, finally create and a kind ofly improve above-mentioned shortcoming, and have more the method for manufacturing circuit board that is applied to the integrated circuit encapsulation of desirable practicality.
Therefore, the classical production process of known integrated circuit encapsulation (COB) includes positive processing procedure and negative film processing procedure:
Wherein the positive fabrication steps includes chemical perforation, circuit making, circuit etching and circuit surface treatment: yet, because behind the circuit etching, can form two surface areas copper surface inequality, therefore through forming the uneven thickness phenomenon of coating behind (COB) overlay coating processing procedure easily, and when the mold pressing manufacture procedure of adhesive of integrated circuit encapsulation (COB), cause the mold pressing glue that overflows easily because of being uneven; Moreover, only stay a part of circuit that needs, when integrated circuit encapsulation (COB) need be drawn the process design of lead, the area of wiring is restricted.
In addition; the negative film manufacturing step comprises: chemical perforation, circuit making, route protection, circuit etching and circuit surface treatment: yet, because the negative film manufacturing needs the step of many one route protections, and after plating tin; the step that also needs one stripping tin, so manufacturing cost is higher.
Summary of the invention
The object of the invention is, a kind of method of manufacturing circuit board that is applied to the integrated circuit encapsulation is provided, and its step comprises:
Step 2, circuit are made: use liquid printing ink or photosensitive type printing ink, see through egative film and light source exposure principle and form circuit, remove the circuit surface ink with chemical mode again, make this circuit table show the copper layer partly;
Step 3, circuit surface treatment: after the circuit surface ink removal that stays, the copper face that is exposed plates the metal level that meets integrated circuit encapsulation (COB) processing procedure on demand;
Step 4, circuit etching: with the copper laminar surface printing ink utilization chemical breakdown principle of logicalnot circuit, printing ink is removed fully, and stay logicalnot circuit copper layer, and with the chemical etching decomposition principle logicalnot circuit copper layer is removed fully again, only stay the metal surface that meets integrated circuit encapsulation (COB) processing procedure;
Step 5, circuit side copper clad: the copper layer that the line side is showed out directly plates coat of metal with chemical solution, to avoid revealing the copper wire oxidation;
Step 6, circuit cleaning surfaces: the surface of cleaning integrated circuit encapsulation.
By this, the present invention is because circuit surface-treated step has plated the metal level that meets integrated circuit encapsulation (COB) processing procedure, area number in the time of can avoiding connecting up and produce the height current effect, and do not need contact mat (PAD) serial connection conducting with all integrated circuit encapsulation (COB) circuits, reducing the circuit surface treatment (need increase the design of drawing lead and take the printed circuit board surface product space, can improve the printed circuit board wiring area during step 3).
The effect of contrast prior art: a kind of method of manufacturing circuit board that is applied to the integrated circuit encapsulation is provided, because the present invention has plated the metal level that meets integrated circuit encapsulation (COB) processing procedure before circuit etching, area number in the time of can avoiding connecting up and produce the height current effect, and do not need contact mat (PAD) serial connection conducting with all integrated circuit encapsulation (COB) circuits, the thickness of coating inequality that improves known circuit copper layer is uneven and the mold pressing glue that overflows when causing wafer package easily, and the shortcoming that is restricted of the area of wiring.
Next can enumerate a preferred embodiment; and cooperation diagram and figure number; other purpose and usefulness of the present invention is described further; make the auditor to the present invention more detailed understanding be arranged, and make and be familiar with this operator and can implement according to this, the following stated person only is to explain preferred embodiment; but not be to limit the scope of the invention; so all have based on invention spirit of the present invention, and be any type of change of invention of the present invention or modification, all belongs to the category that the invention is intended to protect.
Description of drawings
Fig. 1: the flow chart of the inventive method.
Fig. 2-1: the present invention utilizes the schematic diagram of printing ink exposure.
Fig. 2-2: the present invention removes the schematic diagram of printing ink.
Fig. 2-3: the present invention plates the schematic diagram of the metal level C that meets integrated circuit encapsulation (COB) processing procedure.
Fig. 2-4: the present invention removes the structural representation behind the printing ink.
Fig. 2-5: the printing ink structural representation of removing logicalnot circuit copper layer.
Fig. 2-6: copper layer line trackside bread of the present invention covers the structural representation of chemical solution.
Fig. 2-7: the present invention sets firmly the structural representation of semiconductor wafer, routing (Bonding) and mold pressing manufacture procedure of adhesive.
Fig. 3: the flow chart of traditional positive processing procedure.
Fig. 4: the flow chart of traditional negative film processing procedure.
Embodiment
The invention provides a kind of method of manufacturing circuit board that is applied to the integrated circuit encapsulation.
At first, see also shown in Figure 1ly, its step comprises:
Step 1 (S1), chemical perforation: on copper circuit board, do chemical perforation (PTH), make its upper and lower layer copper face conducting;
Step 2 (S2), circuit are made: use liquid printing ink or photosensitive type printing ink, see through egative film and light source exposure principle and form circuit (shown in Fig. 2-1, the copper layer is A, printing ink is B), remove the circuit surface ink with chemical mode again, make this circuit table show the copper layer partly, (shown in Fig. 2-2, the printing ink of removing is B ', the printing ink B that stays ", can expose beneath copper layer A after printing ink B ' removals).
Step 3 (S3), circuit surface treatment: after the circuit surface ink removal that stays, the copper face that is exposed plates the metal level that meets integrated circuit encapsulation (COB) processing procedure on demand, shown in Fig. 2-3, plate the metal level (C) that meets integrated circuit encapsulation (COB) processing procedure in the place of removing printing ink B ' originally; Wherein this integrated circuit encapsulation (COB) processing procedure is finished with electrolysis principle.
In addition, in this circuit surface-treated flow process, meet COB processing procedure metal surface coating element and formed with gold, silver, platinum, nickel, tin or other precious metal elements or two kinds of alloying elements synthetic more than the element; The precious metal element that wherein meets COB processing procedure metal surface coating by cobalt, palladium, indium, antimony, bismuth, etc., the group that the metal solid element is formed.
Again in this circuit surface-treated flow process, the synthetic alloying element of element more than two kinds that meets the precious metal element of COB processing procedure metal surface coating is formed, group family by gold, silver, platinum, nickel, tin or cobalt, palladium, indium, antimony, bismuth is formed, and for example: metals such as tin indium, Xi Yin, tin bismuth, nickeline, nickel gold, nickel tin, platinum nickel hold liquid.
Step 4 (S4), circuit etching: with the copper laminar surface printing ink utilization chemical breakdown principle of logicalnot circuit, make it to remove fully clean (shown in Fig. 2-4, with the printing ink B that originally stays " remove); and stay logicalnot circuit copper layer; with the chemical etching decomposition principle logicalnot circuit copper layer is removed fully again; and stay the metal surface that meets integrated circuit encapsulation (C0B) processing procedure (shown in Fig. 2-5, with the printing ink B that originally stays " under logicalnot circuit copper layer A ' removal, make circuit copper layer A " stay).
Step 5 (S5), circuit side copper face coat: the copper layer that the line side is showed out directly plates coat of metal with chemical solution, oxidation is (shown in Fig. 2-6 to avoid revealing copper wire, with copper layer A " circuit side D coat chemical solution); in addition; in the flow process that this circuit side copper face coats; the coat of metal of this circuit side, by gold, silver, platinum, nickel, tin or other precious metal elements, or two kinds of above synthetic alloying elements of element are formed; Wherein in the flow process that the circuit side copper face of this step 5 coats, the precious metal element of the coat of metal of this circuit side by cobalt, palladium, indium, antimony, bismuth, etc. the metal solid element formed.
Again in the flow process that this circuit side copper face coats; the above synthetic alloying element of two kinds of elements of this circuit side coat of metal; system is made up of the group family of gold, silver, platinum, nickel, tin or cobalt, palladium, indium, antimony, bismuth, and for example: metals such as tin indium, Xi Yin, tin bismuth, nickeline, nickel gold, nickel tin, platinum nickel hold liquid.
Step 6 (S6), circuit cleaning surfaces: the surface of cleaning integrated circuit encapsulation.
By above-mentioned step, shown in Fig. 2-7, the metal surface that can encapsulate (COB) processing procedure in integrated circuit sets firmly semiconductor wafer E, and on the metal surface of integrated circuit encapsulation (COB) processing procedure, draw lead F, on the metal of integrated circuit encapsulation (COB) processing procedure, carry out mold pressing manufacture procedure of adhesive G again.
Because step 3 circuit surface-treated step of the present invention has plated the metal level that meets integrated circuit encapsulation (COB) processing procedure, area number in the time of can avoiding because of wiring produces the height current effect, and prevents the excessive phenomenon of integrated circuit encapsulation (COB) metal layer thickness difference.
In addition, the circuit etching step of step 4 of the present invention, because the present invention plates the metal surface of integrated circuit encapsulation (COB) earlier, do not need contact mat (PAD) serial connection conducting with all integrated circuit encapsulation (COB) circuits, and the metal surface that can encapsulate (COB) in integrated circuit is directly finished (COB) surface treatment step and need do not increased and draw lead design, also can improve the wiring area.
Again because step 4 circuit etching step of the present invention, with the chemical etching decomposition principle logicalnot circuit copper layer is removed fully, and stay the metal surface that meets integrated circuit encapsulation (COB) processing procedure, therefore, the copper layer can be exposed in the circuit side of integrated circuit encapsulation (COB), and causes the copper oxidation easily, is commonly called as verdigris, therefore, must be in circuit side copper clad.
From the above mentioned, because circuit surface-treated step of the present invention has plated the metal level that meets integrated circuit encapsulation (COB) processing procedure, area number in the time of can avoiding connecting up and produce the height current effect, and do not need contact mat (PAD) serial connection conducting with all integrated circuit encapsulation (COB) circuits, and (COB) surface treatment step is directly finished in the metal surface that can encapsulate (COB) in integrated circuit, and produce the situation of the glue that overflows when avoiding the mold pressing sealing, the product that can prevent fraction defective produces, and reaches the purpose that reduces cost.
Conclude above-mentioned said, the present invention has above-mentioned numerous usefulness and practical value simultaneously, and can effectively promote whole economic benefit, therefore the present invention is the splendid invention of an intention really, and in constructed field, do not see identical or approximate product public use, should meet the key element of patent of invention, be to file an application in accordance with the law.
Claims (9)
1. one kind is applied to the method for manufacturing circuit board that integrated circuit encapsulates, and its step comprises:
Step 1, chemical perforation: on copper circuit board, do chemical perforation, make its upper and lower layer copper face conducting;
Step 2, circuit are made: use liquid printing ink or photosensitive type printing ink, see through egative film and light source exposure principle and form circuit, remove the circuit surface ink with chemical mode again, make this circuit table show the copper layer partly;
Step 3, circuit surface treatment: after the circuit surface ink removal that stays, the copper face that is exposed plates the metal level that is used for the integrated circuit encapsulation on demand;
Step 4, circuit etching: the copper laminar surface printing ink utilization chemical breakdown of logicalnot circuit is removed totally fully, and stayed logicalnot circuit copper layer, decompose with chemical etching again logicalnot circuit copper layer is removed fully, and stay the metal surface that meets the integrated circuit encapsulation procedure;
Step 5, circuit side copper clad: the copper layer that the line side is showed out directly plates coat of metal with chemical solution, to avoid revealing copper wire and oxidation.
2. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 1 is characterized in that: after the circuit side copper clad step of this step 5, further include step 6 circuit cleaning surfaces: the surface of cleaning integrated circuit encapsulation.
3. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 1, it is characterized in that: this integrated circuit encapsulation procedure is finished with electrolysis mode.
4. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 1, it is characterized in that: in the circuit surface-treated flow process of this step 3, be used for circuit package processing procedure metal surface coating element and formed with one or both alloys synthetic more than element of gold, silver, platinum, nickel, tin.
5. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 4, it is characterized in that: in the circuit surface-treated flow process of this step 3, the metallic element that is used for circuit package processing procedure metal surface coating is selected from a kind of or its alloy of cobalt, palladium, indium, antimony, bismuth metallic element.
6. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 4, it is characterized in that: in the circuit surface-treated flow process of this step 3, be used for being made up of the synthetic alloy of element more than two kinds of circuit package processing procedure metal surface coating, the element that constitutes described alloy is selected from gold, silver, platinum, nickel, tin, cobalt, palladium, indium, antimony, the bismuth.
7. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 1; it is characterized in that: in the flow process that the circuit side copper face of this step 5 coats; the coat of metal of this circuit side; a kind of by in gold, silver, platinum, nickel, the tin element, or two kinds of above synthetic alloys of element are formed.
8. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 7; it is characterized in that: in the flow process that the circuit side copper face of this step 5 coats, the metallic element of the coat of metal of this circuit side is selected from a kind of or its alloy in cobalt, palladium, indium, antimony, the bismuth metallic element.
9. the method for manufacturing circuit board that is applied to the integrated circuit encapsulation as claimed in claim 7; it is characterized in that: in the flow process that the circuit side copper face of this step 5 coats; the alloy that the element more than two kinds of the coat of metal of this circuit side is synthetic is made up of the element in gold, silver, platinum, nickel, tin, cobalt, palladium, indium, antimony, the bismuth.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100837971A CN100544550C (en) | 2006-06-06 | 2006-06-06 | Be applied to the method for manufacturing circuit board of integrated circuit encapsulation |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2006100837971A CN100544550C (en) | 2006-06-06 | 2006-06-06 | Be applied to the method for manufacturing circuit board of integrated circuit encapsulation |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101087493A CN101087493A (en) | 2007-12-12 |
| CN100544550C true CN100544550C (en) | 2009-09-23 |
Family
ID=38938181
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2006100837971A Expired - Fee Related CN100544550C (en) | 2006-06-06 | 2006-06-06 | Be applied to the method for manufacturing circuit board of integrated circuit encapsulation |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100544550C (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101699933B (en) * | 2009-11-02 | 2011-11-30 | 广东达进电子科技有限公司 | Production method of bright-copper-face high-heat-conductivity ceramic circuit board |
| CN108012443B (en) * | 2017-11-29 | 2020-02-14 | 惠州市特创电子科技有限公司 | Solder mask printing method for circuit board |
-
2006
- 2006-06-06 CN CNB2006100837971A patent/CN100544550C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN101087493A (en) | 2007-12-12 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101315917B (en) | Wiring board and its fabricating method | |
| CN104904326B (en) | For producing the semi-finished product, printed circuit board and its production method of printed circuit board | |
| CN101690434B (en) | Method for manufacturing substrate having built-in components | |
| CN104105350B (en) | The method and pcb board of selectivity electricity nickel gold | |
| JP2008263125A5 (en) | ||
| CN106231816A (en) | A kind of manufacture method of golden fingerboard without lead wire | |
| CN104681531B (en) | Package substrate and method for fabricating the same | |
| TW200931548A (en) | Method for manufacturing a substrate for mounting a semiconductor element | |
| CN102194763A (en) | Substrate for carrying semiconductor components and manufacturing method thereof | |
| CN104009006A (en) | Package substrate and method for fabricating the same, and semiconductor package and method for fabricating the same | |
| CN101908515A (en) | Semiconductor device and preparation method thereof | |
| KR101004063B1 (en) | method for nickel-gold plating and printed circuit board | |
| CN100544550C (en) | Be applied to the method for manufacturing circuit board of integrated circuit encapsulation | |
| JP2012004186A (en) | Substrate for mounting semiconductor element and method for manufacturing the same | |
| CN103426855A (en) | Semiconductor package and fabrication method thereof | |
| CN111465721B (en) | Circuit, electronic module of chip card implemented on the circuit and implementation method of the circuit | |
| CN102510675A (en) | Method for electroplating surface of substrate | |
| CN102104007A (en) | Method and equipment for manufacturing special circuit board | |
| KR101001876B1 (en) | Structure for multi-row leadless lead frame and semiconductor package thereof and manufacture method thereof | |
| CN104010444A (en) | Manufacturing method of step circuit, circuit board including step circuit and manufacturing method of circuit board | |
| TWI231734B (en) | Method of producing conductive patterns on a substrate | |
| TWI496226B (en) | Printed circuit board structure and method for protecting metal pad from being scraped | |
| CN103887180B (en) | lead frame processing method | |
| KR101114260B1 (en) | Manufacturing method of pcb using double gold plating process | |
| CN105489506B (en) | The chi frame and its manufacture method of high bonding wire quality |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20090923 Termination date: 20150606 |
|
| EXPY | Termination of patent right or utility model |