CN100546046C - 沟槽绝缘栅场效应晶体管 - Google Patents

沟槽绝缘栅场效应晶体管 Download PDF

Info

Publication number
CN100546046C
CN100546046C CNB2004800352236A CN200480035223A CN100546046C CN 100546046 C CN100546046 C CN 100546046C CN B2004800352236 A CNB2004800352236 A CN B2004800352236A CN 200480035223 A CN200480035223 A CN 200480035223A CN 100546046 C CN100546046 C CN 100546046C
Authority
CN
China
Prior art keywords
region
field effect
effect transistor
drift region
type surface
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
CNB2004800352236A
Other languages
English (en)
Other versions
CN1886836A (zh
Inventor
R·J·E·许廷
E·A·海曾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yasuyo Co Ltd
Original Assignee
Koninklijke Philips Electronics NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Koninklijke Philips Electronics NV filed Critical Koninklijke Philips Electronics NV
Publication of CN1886836A publication Critical patent/CN1886836A/zh
Application granted granted Critical
Publication of CN100546046C publication Critical patent/CN100546046C/zh
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7801—DMOS transistors, i.e. MISFETs with a channel accommodating body or base region adjoining a drain drift region
    • H01L29/7802—Vertical DMOS transistors, i.e. VDMOS transistors
    • H01L29/7813—Vertical DMOS transistors, i.e. VDMOS transistors with trench gate electrode, e.g. UMOS transistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H01L29/0653—Dielectric regions, e.g. SiO2 regions, air gaps adjoining the input or output region of a field-effect device, e.g. the source or drain region
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0684—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by the shape, relative sizes or dispositions of the semiconductor regions or junctions between the regions
    • H01L29/0692—Surface layout
    • H01L29/0696—Surface layout of cellular field-effect devices, e.g. multicellular DMOS transistors or IGBTs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H01L29/0852—Source or drain regions of field-effect devices of field-effect transistors with insulated gate of DMOS transistors
    • H01L29/0873—Drain regions
    • H01L29/0878—Impurity concentration or distribution
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42364—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity
    • H01L29/42368—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the insulating layer, e.g. thickness or uniformity the thickness being non-uniform
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/4238—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the surface lay-out

Abstract

本发明涉及具有漏极(8)、漂移区(10)、主体(12)和源极(14)的沟槽MOSFET。为了提高用作控制和同步FET的MOSFET的品质因数，沟槽(20)部分填充有电介质(24)，其与漂移区(10)相邻，且漂移区(10)中采用渐变的掺杂分布。

Description

沟槽绝缘栅场效应晶体管
本发明涉及沟槽MOSFET(金属氧化物半导体场效应晶体管)，尤其但不专门涉及适于用作控制和同步FET的沟槽MOSFET结构。
低压沟槽MOSFET通常例如用在诸如个人计算机的电子设备的电源中的电压调节器模块(VRM)中。通常，采用一对MOSFET，即通常所说的控制FET和同步FET。这些FET的理想特性差别很小。对于同步FET，传导功率损耗应尽可能低。由于传导功率损耗与特定导通电阻(Rds，on)成比例，所以应该减小这个参数。另一方面，对于控制FET，应最小化开关损耗，其与栅-漏极电荷密度(Qgd)成比例。
品质因数(FOM)已被定义为Rds，on和Qgd的乘积，以提供晶体管在供VRM之用中适用程度的指示。注意，FOM越小越好。存在对提供改进品质因数的结构的需要。
通常就晶体管而论，有减小沟槽MOSFET尺寸的驱动力。在此考虑的器件情况下，这样的主要好处是减小有效面积并从而减小Rds，on。例如可采用深紫外线光刻技术制造这种减小尺寸的沟槽MOSFET。
然而，对于控制FET，尺寸的减小并不一定具有吸引力，因为在传统结构中，随着尺寸的减小，栅漏极电荷密度Qgd急剧增大。因此，简单地减小结构的尺寸不能提供象所期望那样大的改进。
因此存在对给出VRM的改进FET特性的改进结构的需要。
根据本发明，提供了一种绝缘栅场效应晶体管，其包括：源极区，具有第一导电类型；主体区，具有与第一导电类型相反的第二导电类型，与源极区相邻；漂移区，具有专有的第一导电类型，与主体区相邻；漏极区，具有第一导电类型，与漂移区相邻，以使主体区和漂移区布置在源极和漏极区之间，漏极区具有比漂移区高的掺杂浓度；以及绝缘沟槽，从源极区贯穿主体区并进入漂移区，每个沟槽具有侧壁，并包括侧壁上的绝缘体，以及导电的栅电极，其中每个沟槽的底部填充有绝缘填料(plug)，其基本与主体区和漏极区之间的漂移区全长相邻，且各自栅电极设置在填料上的沟槽中，与源极区和主体区相邻。
本发明采用降低表面场(RESURF)效应，而不像传统的RESURF晶体管，RESURF是非优化的，因为与漂移区相邻的沟槽填充有绝缘体，不是栅电极。此外，不像一些漂移区具有两种导电类型的条带以获得显著降低表面场(RESURF)效应的器件，本发明采用单一导电类型的漂移区。
与传统的沟槽MOSFET相比，尽管本发明得到了高的非优化RESURF效应，但对于相同的击穿电压，器件仍能获得降低的Rds，on。与传统的FET相比，可以提高漂移掺杂浓度，这能对Qgd产生影响，但这可由栅极和漏极之间厚的电介质来补偿。
该器件获得这个结果，在某种意义上，其制造起来比在漂移区采用n型和p型掺杂的器件简单得多。
填料可以是在与漏极相邻的侧壁上绝缘体之间填充沟槽的电介质填充物。备选地，填料可以填充沟槽的整个底部，并且只在填料之上提供的侧壁绝缘体使栅电极与主体区和源极区绝缘。
最好，漂移区中的掺杂浓度是不均匀的，更好的是线性渐变的，并且最好，邻近漏极区的掺杂浓度比邻近主体区的要高。由耗尽电荷将Qgd值确定在有效范围，并且这是采用渐变的掺杂分布来解决的，其使Qgd获得了改进。
计算(下面给出)示出本发明能在Qgd获得一些改进的同时，使Rds，on值获得显著的改进。因此，根据本发明的器件的品质因数较现有技术的器件有显著的改进。
在实施例中，主体掺杂浓度范围在0.5到3×1017cm-3，且漂移掺杂浓度范围在1015到2×1017cm-3。可以选择具体的值，以在Rds，on和Qgd之间获得适当的折衷。
本发明特别应用于垂直沟槽MOSFET，即，半导体主体具有相对的第一和第二主表面的MOSFET，其中源极区在主体区之上的第一主表面，主体区在漂移区之上，而漂移区在漏极区之上，并且沟槽从第一主表面穿过源极、主体区和漂移区向第二主表面延伸。
注意，在本说明书中，术语“之上”用于表示朝向第一主表面的方向，而“之下”用于表示朝向第二主表面的方向，没有预定MOSFET空间中的任何定向。
具体地说，晶体管可以有多个单元，每个单元具有在单元中心由绝缘沟槽包围的源极区。
单元可具有六边形的几何形状，或旋转的正方形几何形状。
备选地，单元可以是横向排列在第一主表面上的条带，其中源极和沟槽交替。
单元间距通常可在0.2到0.7微米的范围内，以使击穿电压达到30V。为了得到更高的击穿电压，沟槽可以比其它的更深，并且这可导致对增大单元间距的需要，例如达到1.5微米，或者为了得到更高的击穿电压，甚至可以更大。
沟槽可以在侧壁上具有栅极氧化物，并且与漂移区相邻的沟槽底部可以在侧壁上的栅极氧化物之间填充有氧化物填充物。备选地，可用氮化物或氮氧化物作为填充物。
现在将纯粹以示例的方式参考附图描述本发明的实施例，其中：
图1示出了根据本发明第一实施例的MOSFET的剖面侧视图；
图2示出了图1实施例的俯视图；
图3示出了根据第一实施例的MOSFET的掺杂分布；以及
图4示出了根据本发明第二实施例的MOSFET的俯视图。
注意，附图是示意图并未按比例。在不同的图中，相同或相似的特征采用类似的附图标记。
图1示出了根据本发明第一实施例的半导体器件的横截面。硅半导体主体2具有相对的第一主表面4和第二主表面6。n+漏极区8与第二主表面相邻。n-漂移区10设置在漏极区8的上面，p主体区12在漏极的上面，且n+源极区14在主体区12的上面。源极接点16设置在第一主表面4上以连接源极区14，并且漏极接点18设置在第二主表面6上以连接漏极区。
沟槽20从第一主表面4贯穿源极区14、主体区12和漂移区10，具有侧壁22以及靠近漏极区-漂移区界面26的底部24。在侧壁22上设置有栅极氧化物28。沟槽20的底部用氧化物电介质填充物30填充，与漂移区10相邻。在电介质填充物30上提供多晶硅栅极32，其与源极区14和主体区12相邻。栅极接点38连接到栅极32。
如图2中图解的，在具体例子中，多个单元40在第一主表面上延伸，以定义多个条带，其中源极区14和沟槽20交替。单元间距是0.5微米，并且沟槽是1.2微米深和0.25微米宽。线A-A指示出截取图1断面的位置。如专业技术人员将理解的，可根据需要改变这些尺寸值。
P型主体区12延伸到0.6微米深，且在第一主表面4露出，以使它能连接到远离线A-A隔开的位置的源极接点16。为了清晰起见，源极接点16未在图2中显示。
在图3中，掺杂分布显示为深度的函数。漂移区10的掺杂浓度不同于主体区12和漂移区10接合处的5×1015cm-3，并线性增加到漂移区-漏极区界面26处的大约1017cm-3的值。漏极区为1019cm-3的n型掺杂，主体区为1017cm-3的p型掺杂，而源极是1021cm-3的n型重掺杂。
在这个具体例子中，已经计算出击穿电压BV为25V，其中击穿发生在靠近p型主体区12/漂移区10接合处。对于10V的栅源电压，已经计算出不包括衬底电阻的Rds，on的值为1.1mΩ.mm2，并对于12V的漏源电压，已经计算出Qgd为2.2nC/mm2。这给出了2.4mΩ.nC的品质因数。这相比于具有200nm厚的沟槽底部氧化物且间距、沟槽宽度和击穿电压与该例子相同但具有恒定漂移掺杂密度的传统沟槽MOSFET的6.3mΩ.nC。
本发明由此能提供非常显著的品质因数改进。
在第二实施例中，采用晶胞几何形状代替条带几何形状，如图4中所示的六边形几何形状。每个六边形细胞的中心包括源极14、主体区12和漂移区10的堆叠，并且沟槽式栅极32的互连矩阵围绕这些细胞。
对于10V的栅源电压，已经进行了计算，并给出了不包括衬底电阻的Rds，on的值为1.4mΩ.mm2，并且对于12V的漏源电压，Qgd为1.6nC/mm2。这给出了2.2mΩ.nC的品质因数。这比图1的实施例更好。如果要求更高的阈值电压，则p型主体12的掺杂密度可以稍微地提高。备选地，取代n型多晶硅的p型可用于栅极导电层，这也增加了阈值电压。
近期公布的LDMOS结构(Ludikhuize AW，ISPSD p301-304，2002)的品质因数是22mΩ.nC。这是对于较大的细胞尺寸，但即使缩小到0.5微米的间距，仍给出达到6.6nC/mm2的Qgd。因此，本发明提供了比这个公布的值更好的结果。
通过阅读本公开，其它的变化和修改对于本领域技术人员来说将是显而易见的。这种变化和修改可以包括等效的或其它的特征，其在半导体器件的设计、制造和使用上已经众所周知，并且其可应用于除这里描述的特征之外的特征，或取代这里描述的特征。尽管在这个申请中已经阐明了针对特征的特定组合的权利要求，但要理解到，公开的范围也包括在此明确或隐含地公开的任何新颖的特征或任何新颖的特征组合，或者其任何广义性，不论其是否减轻了与本发明相同的任何或所有技术问题。申请人借此通知，在本申请或任何源于此的任何进一步申请的执行期间，可以针对这种特征和/或这种特征的组合提出新的权利要求。
例如，p型和n型层可以互换。
代替硅主体，本发明也可采用其它半导体材料，包括例如III-V族材料。
例如，沟槽中的氧化物电介质可用氮化物或氮氧化物取代。这会增加Qgd，但减小Rds，on。可以采用低k材料，这会有相反的效果。
可以采用其它材料代替多晶硅栅极。具体地说，可以采用硅化物栅极。
同样，虽然具体实施例采用分离的栅极氧化物和沟槽填充物，但在沟槽中用单一的电介质来实现本发明也是可能的。
可以采用n中取1(1 of n)原则。在此配置中，可在每n个沟槽的一个中提供附加的源极场电极。
本发明也可应用于横向沟槽MOSFET。

Claims (14)

1.一种绝缘栅场效应晶体管，包括：
半导体主体(2)，所述半导体主体(2)包括：
第一主表面(4)；
源极区(14)，具有第一导电类型；
主体区(12)，具有与第一导电类型相反的第二导电类型，与所述源极区相邻；
漂移区(10)，具有第一导电类型，与所述主体区相邻；以及
漏极区(8)，具有第一导电类型，与所述漂移区相邻，以使主体区和漂移区布置在所述源极和漏极区之间，所述漏极区比所述漂移区具有更高的掺杂密度；以及
绝缘沟槽(20)，从所述半导体主体(2)的所述第一主表面(4)贯穿所述源极区(14)、贯穿所述主体区(12)并进入所述漂移区(10)，每个沟槽(20)具有侧壁(22)，且包括所述侧壁上的绝缘体(28)以及侧壁(22)之间的导电栅电极(32)，
其中每个沟槽(20)的底部填充有绝缘填料(30)，其基本与所述主体区(12)和漏极区(8)之间的所述漂移区(10)的全长相邻，且各自的栅电极(32)设置在所述填料(30)之上的所述沟槽(20)中，与所述源极区和主体区(14，12)相邻。
2.如权利要求1所述的绝缘栅场效应晶体管，其中与所述主体区相邻的所述漂移区(10)中的掺杂浓度比与所述漏极区相邻的要低。
3.如任一项上述权利要求所述的绝缘栅场效应晶体管，其中所述主体区(12)中的掺杂浓度在0.5×1017cm-3到3×1017cm-3的范围内，且所述漂移区(10)中的掺杂浓度在1015cm-3到2×1017cm-3的范围内。
4.如权利要求1或2所述的绝缘栅场效应晶体管，其中所述填料(30)是在与所述漂移区(10)相邻的所述侧壁(22)上所述绝缘体(28)之间填充所述沟槽的电介质填充物。
5.如权利要求3所述的绝缘栅场效应晶体管，其中所述填料(30)是在与所述漂移区(10)相邻的所述侧壁(22)上所述绝缘体(28)之间填充所述沟槽的电介质填充物。
6.如权利要求1、2或5所述的绝缘栅场效应晶体管，其中所述半导体主体(2)具有相对的第一(4)和第二主表面(6)，
其中所述源极区(14)在所述主体区(12)上的第一主表面，所述主体区(12)在所述漂移区(10)上，且所述漂移区(10)在所述漏极区(8)上，以及
所述沟槽从第一主表面向第二主表面延伸。
7.如权利要求3所述的绝缘栅场效应晶体管，其中所述半导体主体(2)具有相对的第一(4)和第二主表面(6)，
其中所述源极区(14)在所述主体区(12)上的第一主表面，所述主体区(12)在所述漂移区(10)上，且所述漂移区(10)在所述漏极区(8)上，以及
所述沟槽从第一主表面向第二主表面延伸。
8.如权利要求4所述的绝缘栅场效应晶体管，其中所述半导体主体(2)具有相对的第一(4)和第二主表面(6)，
其中所述源极区(14)在所述主体区(12)上的第一主表面，所述主体区(12)在所述漂移区(10)上，且所述漂移区(10)在所述漏极区(8)上，以及
所述沟槽从第一主表面向第二主表面延伸。
9.如权利要求6所述的绝缘栅场效应晶体管，具有多个单元(40)，
每个单元具有在所述单元中心由绝缘沟槽(20)包围的源极区(14)。
10.如权利要求9所述的绝缘栅场效应晶体管，其中所述单元(40)具有六边形的几何形状。
11.如权利要求9或10所述的绝缘栅场效应晶体管，其中所述沟槽(20)在所述侧壁上具有栅极氧化物(28)，并且与所述漂移区(10)相邻的所述沟槽的底部(24)在所述沟槽任一侧的侧壁(22)上所述栅极氧化物(24)之间填充有填充物氧化物(30)。
12.如权利要求6所述的绝缘栅场效应晶体管，具有多个单元(40)，在第一主表面(4)上排列成条带，其中沟槽(20)和源极区(14)交替，
13.如权利要求9、10、或12所述的绝缘栅场效应晶体管，其中单元间距在0.2到0.7微米的范围内。
14.如权利要求11所述的绝缘栅场效应晶体管，其中单元间距在0.2到0.7微米的范围内。
CNB2004800352236A 2003-11-29 2004-11-26 沟槽绝缘栅场效应晶体管 Active CN100546046C (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
GB0327793.6 2003-11-29
GBGB0327793.6A GB0327793D0 (en) 2003-11-29 2003-11-29 Trench mosfet

Publications (2)

Publication Number Publication Date
CN1886836A CN1886836A (zh) 2006-12-27
CN100546046C true CN100546046C (zh) 2009-09-30

Family

ID=29798072

Family Applications (1)

Application Number Title Priority Date Filing Date
CNB2004800352236A Active CN100546046C (zh) 2003-11-29 2004-11-26 沟槽绝缘栅场效应晶体管

Country Status (6)

Country Link
US (1) US7696599B2 (zh)
EP (1) EP1692727A2 (zh)
JP (1) JP2007512701A (zh)
CN (1) CN100546046C (zh)
GB (1) GB0327793D0 (zh)
WO (1) WO2005053033A2 (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6838722B2 (en) 2002-03-22 2005-01-04 Siliconix Incorporated Structures of and methods of fabricating trench-gated MIS devices
JP5452003B2 (ja) 2008-09-23 2014-03-26 三菱電機株式会社 半導体チップの製造方法および半導体モジュールの製造方法
US9425305B2 (en) 2009-10-20 2016-08-23 Vishay-Siliconix Structures of and methods of fabricating split gate MIS devices
US9419129B2 (en) 2009-10-21 2016-08-16 Vishay-Siliconix Split gate semiconductor device with curved gate oxide profile
US20120220092A1 (en) * 2009-10-21 2012-08-30 Vishay-Siliconix Method of forming a hybrid split gate simiconductor
US10026835B2 (en) * 2009-10-28 2018-07-17 Vishay-Siliconix Field boosted metal-oxide-semiconductor field effect transistor
WO2011109559A2 (en) 2010-03-02 2011-09-09 Kyle Terrill Structures and methods of fabricating dual gate devices
WO2012158977A2 (en) 2011-05-18 2012-11-22 Vishay-Siliconix Semiconductor device
US9508596B2 (en) 2014-06-20 2016-11-29 Vishay-Siliconix Processes used in fabricating a metal-insulator-semiconductor field effect transistor
KR102026543B1 (ko) 2014-08-19 2019-09-27 비쉐이-실리코닉스 전자 회로
US11217541B2 (en) 2019-05-08 2022-01-04 Vishay-Siliconix, LLC Transistors with electrically active chip seal ring and methods of manufacture
JP7247061B2 (ja) 2019-09-05 2023-03-28 株式会社東芝 半導体装置およびその製造方法
US11218144B2 (en) 2019-09-12 2022-01-04 Vishay-Siliconix, LLC Semiconductor device with multiple independent gates
US20230411510A1 (en) 2020-11-04 2023-12-21 Hitachi Energy Switzerland Ag Power field-effect transistor and manufacturing method

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5132753A (en) * 1990-03-23 1992-07-21 Siliconix Incorporated Optimization of BV and RDS-on by graded doping in LDD and other high voltage ICs
JP3291957B2 (ja) * 1995-02-17 2002-06-17 富士電機株式会社 縦型トレンチｍｉｓｆｅｔおよびその製造方法
US5637898A (en) 1995-12-22 1997-06-10 North Carolina State University Vertical field effect transistors having improved breakdown voltage capability and low on-state resistance
US5612567A (en) * 1996-05-13 1997-03-18 North Carolina State University Schottky barrier rectifiers and methods of forming same
GB9826041D0 (en) 1998-11-28 1999-01-20 Koninkl Philips Electronics Nv Trench-gate semiconductor devices and their manufacture
US6198127B1 (en) 1999-05-19 2001-03-06 Intersil Corporation MOS-gated power device having extended trench and doping zone and process for forming same
US6433385B1 (en) * 1999-05-19 2002-08-13 Fairchild Semiconductor Corporation MOS-gated power device having segmented trench and extended doping zone and process for forming same
US6191447B1 (en) * 1999-05-28 2001-02-20 Micro-Ohm Corporation Power semiconductor devices that utilize tapered trench-based insulating regions to improve electric field profiles in highly doped drift region mesas and methods of forming same
US6455378B1 (en) * 1999-10-26 2002-09-24 Hitachi, Ltd. Method of manufacturing a trench gate power transistor with a thick bottom insulator
JP4528460B2 (ja) * 2000-06-30 2010-08-18 株式会社東芝 半導体素子
US6849898B2 (en) * 2001-08-10 2005-02-01 Siliconix Incorporated Trench MIS device with active trench corners and thick bottom oxide
TWI241012B (en) * 2004-06-25 2005-10-01 Mosel Vitelic Inc Method of manufacturing power device

Also Published As

Publication number Publication date
US7696599B2 (en) 2010-04-13
JP2007512701A (ja) 2007-05-17
EP1692727A2 (en) 2006-08-23
WO2005053033A3 (en) 2006-03-09
US20070108515A1 (en) 2007-05-17
GB0327793D0 (en) 2003-12-31
WO2005053033A2 (en) 2005-06-09
CN1886836A (zh) 2006-12-27

Similar Documents

Publication Publication Date Title
US7408223B2 (en) Trench insulated gate field effect transistor
KR100607526B1 (ko) 연장된 트렌치와 도핑 영역을 갖는 모스-게이트 파워디바이스 및 그 성형공정
US7948033B2 (en) Semiconductor device having trench edge termination structure
CN104485359B (zh) 自对准电荷平衡的功率双扩散金属氧化物半导体制备方法
CN100546046C (zh) 沟槽绝缘栅场效应晶体管
JP4564793B2 (ja) 多層拡張ドレイン構造を有する高電圧縦型トランジスタ
US7465986B2 (en) Power semiconductor device including insulated source electrodes inside trenches
US6433385B1 (en) MOS-gated power device having segmented trench and extended doping zone and process for forming same
US6833583B2 (en) Edge termination in a trench-gate MOSFET
KR100900852B1 (ko) 반도체 디바이스
CN100546045C (zh) 沟槽绝缘栅场效应晶体管
WO2007129261A2 (en) Trench field effect transistors
US9391194B1 (en) High voltage vertical FPMOS fets
KR20000016027A (ko) 트렌치-게이트 제어된 파워 mosfet
CN107546274B (zh) 一种具有阶梯型沟槽的ldmos器件
CN215731731U (zh) 超结功率mosfet
CN107104149A (zh) 一种功率半导体器件
CN112864244A (zh) 超结器件
CN115763565A (zh) 一种具有高k介质的屏蔽栅沟槽型MOSFET结构
CN110034179A (zh) 沟槽金氧半导体元件
CN107768240A (zh) 一种沟槽式晶体管的源区结构及其制备方法

Legal Events

Date Code Title Description
C06 Publication
PB01 Publication
C10 Entry into substantive examination
SE01 Entry into force of request for substantive examination
ASS Succession or assignment of patent right

Owner name: NXP CO., LTD.

Free format text: FORMER OWNER: KONINKLIJKE PHILIPS ELECTRONICS N.V.

Effective date: 20070810

C41 Transfer of patent application or patent right or utility model
TA01 Transfer of patent application right

Effective date of registration: 20070810

Address after: Holland Ian Deho Finn

Applicant after: Koninkl Philips Electronics NV

Address before: Holland Ian Deho Finn

Applicant before: Koninklijke Philips Electronics N.V.

C14 Grant of patent or utility model
GR01 Patent grant
C41 Transfer of patent application or patent right or utility model
TR01 Transfer of patent right

Effective date of registration: 20160920

Address after: Holland Ian Deho Finn

Patentee after: Naizhiya Co., Ltd.

Address before: Holland Ian Deho Finn

Patentee before: Koninkl Philips Electronics NV

CP03 Change of name, title or address
CP03 Change of name, title or address

Address after: Nijmegen

Patentee after: Yasuyo Co. Ltd.

Address before: Holland Ian Deho Finn

Patentee before: Naizhiya Co., Ltd.