CN100547753C - Solid encapsulation structure and manufacture method thereof - Google Patents
Solid encapsulation structure and manufacture method thereof Download PDFInfo
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- CN100547753C CN100547753C CN200610127547.3A CN200610127547A CN100547753C CN 100547753 C CN100547753 C CN 100547753C CN 200610127547 A CN200610127547 A CN 200610127547A CN 100547753 C CN100547753 C CN 100547753C
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- conductive layer
- semiconductor body
- weld pad
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- hole
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16135—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip
- H01L2224/16145—Disposition the bump connector connecting between different semiconductor or solid-state bodies, i.e. chip-to-chip the bodies being stacked
Abstract
A kind of solid encapsulation structure and manufacture method thereof, manufacture method may further comprise the steps: a semiconduction body (a) is provided; (b) on the semiconduction body, form at least one blind hole; (c) on the sidewall of blind hole, form an insulating barrier; (d) on insulating barrier, form a conductive layer; (e) on conductive layer, form a dry film; (f) in blind hole, insert scolder; (g) remove dry film; (h) patterned conductive layer; (i) remove the part of semiconduction body lower surface and the some of insulating barrier, to expose the part of conductive layer; (j) a plurality of semiconduction bodies of storehouse, and carry out reflow; And (k) the semiconduction body of cutting behind the storehouse, to form a plurality of solid encapsulation structures.Thus, the lower end of conductive layer is in the scolder of the semiconduction body below " insertion ", thereby makes conductive layer more firm with engaging of scolder, and the whole height of the solid encapsulation structure after engaging can reduce effectively.
Description
Technical field
The present invention relates to a kind of encapsulating structure and manufacture method thereof, particularly a kind of solid encapsulation structure and manufacture method thereof.
Background technology
With reference to figure 1, be U.S. US4, the schematic diagram of solid encapsulation structure before reflow that 499, No. 655 patent disclosed.Solid encapsulation structure 1 comprises the first module 10 and second unit 20.First module 10 comprises first semiconductor body 11, at least one first hole 12, first conductive layer (conductivelayer) 13 and first scolder (solder) 14.First semiconductor body 11 has first surface 111 and second surface 112, and first surface 111 has at least one first weld pad (figure does not show) and first protective layer (protection layer), 113, the first protective layers 113 expose first weld pad.First semiconductor body 11 is run through in first hole 12.First conductive layer 13 is positioned on the sidewall in first hole 12, and covers first weld pad and first protective layer 113.First scolder 14 is positioned at first hole, 12, the first scolders 14 and electrically connects first weld pad by first conductive layer 13.First scolder, 14 upper ends extend to the top of the first surface 111 of first semiconductor body 11, and its lower end extends to the below of the second surface 112 of first semiconductor body 11.
Unit second 20 storehouses are on this first module 10.Second unit 20 comprises second semiconductor body 21, at least one second hole 22, second conductive layer 23 and second scolder 24.Second semiconductor body 21 has first surface 211 and second surface 212, and first surface 211 has at least one second weld pad (figure does not show) and second protective layer, 213, the second protective layers 213 expose second weld pad.Second semiconductor body 21 is run through in second hole 22.Second conductive layer 23 is positioned on the sidewall in second hole 22, and covers second weld pad and second protective layer 213.Second scolder 24 is positioned at second hole, 22, the second scolders 24 and electrically connects second weld pad by second conductive layer 23.Second scolder, 24 upper ends extend to the top of the first surface 211 of second semiconductor body 21, and its lower end extends to the below of the second surface 212 of second semiconductor body 21.The lower end aligned of second scolder 24 contacts the upper end of first scolder 14, after reflow (reflow), makes the first module 10 and second unit 20 engage and becomes solid encapsulation structure 1, as shown in Figure 2.
In solid encapsulation structure 1, the generation type of first scolder 14 and second scolder 24 is to place scolder to bathe the top of (solder bath) first semiconductor body 11 and second semiconductor body 21, utilize capillarity to make scolder enter first hole 12 and second hole 22, and form first scolder 14 and second scolder 24.
The shortcoming of solid encapsulation structure 1 is as follows, because first scolder 14 and second scolder 24 are to utilize capillarity to form, therefore its upper end and lower end all are semicircle spherical (Fig. 1), so when first module 10 and Unit second 20 aligning joints, the difficulty that can increase aim at, and the joint of 20 of reflow (reflow) back first module 10 and Unit second and built on the sand.In addition, the unnecessary spherical scolder of semicircle can't reduce whole height after making the first module 10 and second unit 20 engage effectively.
Therefore, be necessary to provide a kind of solid encapsulation structure and manufacture method thereof of innovating and having progressive, to address the above problem.
Summary of the invention
The object of the present invention is to provide a kind of solid encapsulation structure and manufacture method thereof, to solve the problem of above-mentioned prior art.
For realizing described purpose, the present invention includes following steps: provide semiconductor body (semiconductor body), semiconductor body has first surface and second surface, first surface has at least one weld pad and a protective layer (protection layer), and protective layer can expose weld pad; On the first surface of semiconductor body, form at least one blind hole; On the sidewall of blind hole, form insulating barrier (isolationlayer); Form conductive layer (conductive layer), conductive layer covers weld pad, protective layer and insulating barrier; Form a dry film (dry film) on conductive layer, dry film offers opening at the relative position of blind hole; In blind hole, insert scolder (solder); Remove dry film; Patterned conductive layer; Remove the part of semiconductor body second surface and the some of insulating barrier, to expose the part of conductive layer; The a plurality of semiconductor bodies of storehouse, and carry out reflow (reflow); And the semiconductor body behind the cutting storehouse, to form a plurality of solid encapsulation structures.
Another object of the present invention is to provide a kind of solid encapsulation structure, comprise: a first module, comprise: one first semiconductor body, have a first surface and a second surface, first surface has at least one first weld pad and one first protective layer (protection layer), and first protective layer exposes this first weld pad; This first semiconductor body is run through at least one first hole; One first insulating barrier (isolation layer) is positioned on the sidewall in this first hole; One first conductive layer (conductivelayer) covers first weld pad, part first protective layer and first insulating barrier, holds side under the second surface that extends to first semiconductor body under first conductive layer; And one first scolder, being positioned at first hole, first scolder sees through this first conductive layer and is electrically connected first weld pad; And Unit one second, be stacked on the first module, Unit second comprises: one second semiconductor body has a first surface and a second surface, first surface has at least one second weld pad and one second protective layer (protection layer), and second protective layer exposes second weld pad; Second semiconductor body is run through at least one second hole; One second insulating barrier (isolation layer) is positioned on the sidewall in second hole;
One second conductive layer (conductive layer), cover second weld pad, part second protective layer and second insulating barrier, hold under the second surface that extends to second semiconductor body under second conductive layer just to make this second hole become blind hole, and first scolder is inserted in the lower end of this second conductive layer; And one second scolder, being positioned at this second hole, second scolder sees through second conductive layer and is electrically connected second weld pad.
A kind of solid encapsulation structure and the manufacture method thereof that the invention provides, be exposed at outside the lower end of its conductive layer under the second surface of this semiconductor body, therefore in the back welding process behind storehouse, the conductive layer lower end can " insertion " in the scolder of semiconductor body of below, thereby make conductive layer more firm with engaging of scolder, and the whole height of solid encapsulation structure can reduce effectively after engaging.
The present invention's purpose feature and advantage will be elaborated in conjunction with the accompanying drawings with embodiment.
Description of drawings
Fig. 1 is U.S. US4, the schematic diagram of solid encapsulation structure before reflow of 499, No. 655 patent exposure.
Fig. 2 is U.S. US4, the schematic diagram of solid encapsulation structure after reflow of 499, No. 655 patent exposure.
Fig. 3 is the flow chart of first embodiment of the manufacture method of solid encapsulation structure of the present invention.
Fig. 4 to Figure 17 is the schematic diagram of each fabrication steps among first embodiment of the manufacture method of solid encapsulation structure of the present invention.
Figure 18 is the flow chart of second embodiment of the manufacture method of solid encapsulation structure of the present invention.
Figure 19 to Figure 21 is the schematic diagram of part fabrication steps among second embodiment of the manufacture method of solid encapsulation structure of the present invention.
Figure 22 is the profile of solid encapsulation structure of the present invention.
Embodiment
With reference to figure 3, be the schematic flow sheet of first embodiment of the manufacture method of solid encapsulation structure of the present invention.Cooperation to Figure 17, is each fabrication steps schematic diagram among first embodiment of the manufacture method of solid encapsulation structure of the present invention with reference to figure 4.At first, cooperate, shown in step S301, provide semiconductor body (semiconductor body) 31 with reference to figure 3 and Fig. 4.Semiconductor body 31 can be wafer or chip.Semiconductor body 31 has first surface 311 and second surface 312, and first surface 311 has at least one weld pad 32 and protective layer (protection layer) 33, and protective layer 33 exposes weld pad 32.
Then, cooperate, shown in step S302, in first surface 311 at least one blind hole 34 of formation of semiconductor body 31 with reference to figure 3 and Fig. 5.In the present embodiment, blind hole 34 is positioned at the next door of weld pad 32.Yet in other was used, blind hole 34 can run through weld pad 32.
Then, cooperate, shown in step S303, on the sidewall of blind hole 34, form insulating barrier (isolation layer) 35 with reference to figure 3 and Fig. 6.
Then, cooperate with reference to figure 3 and Fig. 7, shown in step S304, form conductive layer (conductivelayer) 36, conductive layer 36 covers weld pad 32, protective layer 33 and insulating barrier 35.The material of conductive layer 36 is titanium, copper, copper/titanium alloy or other metal.
Then, cooperate with reference to figure 3 and Fig. 8, shown in step S305, form dry film (dry film) 37 on conductive layer 36, dry film 37 offers opening 371 at the relative position of blind hole 34.
Then, cooperate, shown in step S306, in blind hole 34, insert scolder (solder) 38 with reference to figure 3 and Fig. 9.In the present embodiment, utilize plating mode (plating) that scolder 38 is inserted in the blind hole 34.Yet be understandable that, also can utilize alternate manner that scolder 38 is inserted in the blind hole 34.
Then, cooperate, shown in step S307, remove dry film 37 with reference to figure 3 and Figure 10, and patterned conductive layer 36.
Then, cooperate, preferably shown in step S308, on conductive layer 36, form passivation layer (passivation layer) 39, with the conductive layer 36 of protection patterning with reference to figure 3 and Figure 11.Passivation layer 39 can utilize any existing mode to form.In addition, be understandable that this step is the selectivity step.
Then, shown in step S309, remove the part of semiconductor body 31 second surfaces 312 and the some of insulating barrier 35, to expose the part of conductive layer 36.With reference to Figure 12, in the present embodiment, elder generation trims up to the lower end of second surface 312 with insulating barrier 35 with the second surface 312 of the mode grinding semiconductor body 31 of grinding back surface (backside grinding), and promptly the lower end of insulating barrier 35 manifests second surface 312.Then, the lower end of the second surface 312 of etching semiconductor body 31 and insulating barrier 35 again, exposing the lower end of conductive layer 36, this moment, the lower end of conductive layer 36 extended to the below of the second surface 312 of semiconductor body 31, as shown in figure 13.Yet be understandable that, in other is used, can not use the mode of grinding back surface, and direct second surface 312 with etching mode processing semiconductor body 31, to expose the lower end of conductive layer 36.
Then, cooperate with reference to figure 3 and Figure 14, preferably shown in step S310, form barrier layer (barrier layer) 40 in the lower end of conductive layer 36, barrier layer 40 covers the lower end of the conductive layer 36 that exposes.Barrier layer 40 can be nickel, chromium, chromium/copper alloy or other metal.Be understandable that this step is the selectivity step.In addition, preferably, the below of barrier layer 40 or conductive layer 36 further forms scolder 41 down, and following scolder 41 is attached to conductive layer 36 lower ends of barrier layer 40 or exposure.Be understandable that this step also is the selectivity step.
Then, cooperate with reference to figure 3 and Figure 15, shown in step S311, a plurality of semiconductor bodies 31 of storehouse, wherein the conductive layer 36 and the scolder 38 of two semiconductor bodies 31 are aligned with each other up and down.
Then, cooperate, shown in step S312, carry out reflow (reflow) processing procedure, make semiconductor body 31 see through the welding of conductive layer 36 and scolder 38 and be bonded together with reference to figure 3 and Figure 16.
At last, cooperate with reference to figure 3 and Figure 17, shown in step S313, the semiconductor body 31 behind the cutting storehouse is to form a plurality of solid encapsulation structures 42.Preferably, shown in step S314, form at least one soldered ball 43 below solid encapsulation structure 42, soldered ball 43 is positioned at the lower end of the conductive layer 36 of the semiconductor body 31 of below.Be understandable that this step is the selectivity step.
With reference to Figure 18, the schematic flow sheet of second embodiment of the manufacture method of demonstration solid encapsulation structure of the present invention.The step S401 to S410 of present embodiment and the step S301 to S310 of first embodiment are identical.The present embodiment and the first embodiment difference are as follows, and cutting semiconductor body 31 among the step S411 of present embodiment is to form a plurality of unit 44,45, as shown in figure 19.Then, stack cell 44,45 among the step S412, and wherein the conductive layer 36 and the scolder 38 of two semiconductor bodies 31 are aligned with each other up and down, as shown in figure 20.At last, step S413 is for carrying out reflow (reflow), to form a plurality of solid encapsulation structures 42, as shown in figure 21.The prepared solid encapsulation structure 42 of present embodiment (Figure 21) is identical with the prepared solid encapsulation structure 42 of first embodiment (Figure 17).
Preferably, step S414 forms at least one soldered ball 43 below solid encapsulation structure 42, and soldered ball 43 is positioned at the lower end of the conductive layer 36 of the semiconductor body 31 of below.Be understandable that this step is the selectivity step.
With reference to Figure 22, show the profile of solid encapsulation structure of the present invention.The solid encapsulation structure 5 of this figure and Figure 17 and solid encapsulation structure 42 shown in Figure 21 are identical, but for convenience of explanation, identical assembly is given different labels.Solid encapsulation structure 5 comprises the first module 50 and second unit 60.First module 50 comprises first semiconductor body 51, at least one first hole 52, first insulating barrier (isolation layer), 53, first conductive layer (conductive layer), 54 and first scolder 55.
Unit second 60 storehouses are on this first module 50.Second unit 60 comprises second semiconductor body 61, at least one second hole 62, second insulating barrier (isolation layer), 63, second conductive layer (conductive layer), 64 and second scolder 65.Second semiconductor body 61 is wafer or chip; it has first surface 611 and second surface 612; first surface 611 has at least one second weld pad 613 and second protective layer (protection layer), 614, the second protective layers 614 expose second weld pad 613.Second semiconductor body 61 is run through in second hole 62, and in the present embodiment, second hole 62 is positioned at the next door of second weld pad 613.Yet in other was used, second weld pad 613 can be run through in second hole 62.
Preferably, solid encapsulation structure 5 further comprises at least one soldered ball 43, is positioned at the lower end of first conductive layer 54.
In solid encapsulation structure 5, owing to be exposed under the second surface 612 of second unit 60 outside the lower end of second conductive layer 64, therefore in the processing procedure of reflow, the lower end of second conductive layer 64 can " insertion " first scolder 55 in, thereby make second conductive layer 64 more firm with engaging of first scolder 55.In addition, first hole 52 and second hole 62 can be designed to taper as shown in FIG., and more increase above-mentioned joint effect.In addition, because in lower end " insertion " first scolder 55 of second conductive layer 64, the whole height that therefore engages back solid encapsulation structure 5 can reduce effectively.
The above only is the present invention's preferred embodiment wherein, is not to be used for limiting practical range of the present invention; Be that all equalizations of doing according to claim of the present invention change and modification, be all claim of the present invention and contain.
Claims (10)
1, a kind of manufacture method of solid encapsulation structure is characterized in that may further comprise the steps:
(a) provide the semiconductor body, this semiconductor body has a first surface and a second surface, and this first surface has at least one weld pad and a protective layer, and this protective layer exposes this weld pad;
(b) first surface at this semiconductor body forms at least one blind hole;
(c) on the sidewall of this blind hole, form an insulating barrier;
(d) form a conductive layer, this conductive layer covers this weld pad, this protective layer and this insulating barrier;
(e) form a dry film on this conductive layer, the relative position of this dry film and this blind hole offers opening;
(f) in this blind hole, insert a scolder;
(g) remove this dry film;
(h) this conductive layer of patterning;
(i) remove the part of this semiconductor body second surface and the some of this insulating barrier, to expose the part of this conductive layer;
(j) a plurality of semiconductor bodies after step (a) to step (i) is handled of storehouse, and carry out reflow; And
(k) cut semiconductor body behind this storehouse, to form a plurality of solid encapsulation structures.
2, the manufacture method of solid encapsulation structure as claimed in claim 1 is characterized in that this semiconductor body is a wafer or a chip.
3, the manufacture method of solid encapsulation structure as claimed in claim 1 is characterized in that this blind hole runs through this weld pad.
4, the manufacture method of solid encapsulation structure as claimed in claim 1 is characterized in that this step (h) further is included on this conductive layer afterwards to form a passivation layer to protect this conductive layer.
5, the manufacture method of solid encapsulation structure as claimed in claim 1 is characterized in that this step (i) comprising:
(i1) grind the second surface of this semiconductor body; And
(i2) some of the second surface of this semiconductor body of etching and this insulating barrier is to expose the part of this conductive layer.
6, the manufacture method of solid encapsulation structure as claimed in claim 1 is characterized in that this step (i) comprises further that afterwards one forms the step of a barrier layer, and this barrier layer covers the conductive layer of this exposure.
7, the manufacture method of solid encapsulation structure as claimed in claim 1 is characterized in that this step (i) comprises further that afterwards one forms the step of scolder, and this time scolder connects the conductive layer of this exposure.
8, a kind of solid encapsulation structure is characterized in that, comprising:
One first module comprises:
One first semiconductor body has a first surface and a second surface, and this first surface has at least one first weld pad and one first protective layer, and this first protective layer exposes this first weld pad;
This first semiconductor body is run through at least one first hole;
One first insulating barrier is positioned on the sidewall in this first hole;
One first conductive layer covers this first weld pad, this first protective layer of part and this first insulating barrier, and the lower end of this first conductive layer extends to the below of the second surface of this first semiconductor body; And
One first scolder is positioned at this first hole, and this first scolder sees through this first conductive layer and is electrically connected this first weld pad; And
Unit one second is stacked on this first module, and this Unit second comprises:
One second semiconductor body has a first surface and a second surface, and this first surface has at least one second weld pad and one second protective layer, and this second protective layer exposes this second weld pad;
This second semiconductor body is run through at least one second hole;
One second insulating barrier is positioned on the sidewall in this second hole;
One second conductive layer, cover this second weld pad, this second protective layer of part and this second insulating barrier, the below that the lower end of this second conductive layer extends to the second surface of this second semiconductor body makes this second hole become blind hole, and insert in this first scolder the lower end of this second conductive layer; And
One second scolder is positioned at this second hole, and this second scolder sees through this second conductive layer and is electrically connected this second weld pad.
9, solid encapsulation structure as claimed in claim 8 is characterized in that this semiconductor body is a wafer or a chip.
10, solid encapsulation structure as claimed in claim 8 is characterized in that this first hole wherein runs through this first weld pad or this second hole and run through at least a in this second weld pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610127547.3A CN100547753C (en) | 2006-09-12 | 2006-09-12 | Solid encapsulation structure and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN200610127547.3A CN100547753C (en) | 2006-09-12 | 2006-09-12 | Solid encapsulation structure and manufacture method thereof |
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| CN101145531A CN101145531A (en) | 2008-03-19 |
| CN100547753C true CN100547753C (en) | 2009-10-07 |
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| CN200610127547.3A Active CN100547753C (en) | 2006-09-12 | 2006-09-12 | Solid encapsulation structure and manufacture method thereof |
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| CN102130042B (en) * | 2010-12-14 | 2013-06-26 | 北京大学 | Method for manufacturing through hole interconnection structure |
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| CN101145531A (en) | 2008-03-19 |
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