CN100557512C - Thin film transistor (TFT) and manufacture method thereof - Google Patents
Thin film transistor (TFT) and manufacture method thereof Download PDFInfo
- Publication number
- CN100557512C CN100557512C CNB2004100971810A CN200410097181A CN100557512C CN 100557512 C CN100557512 C CN 100557512C CN B2004100971810 A CNB2004100971810 A CN B2004100971810A CN 200410097181 A CN200410097181 A CN 200410097181A CN 100557512 C CN100557512 C CN 100557512C
- Authority
- CN
- China
- Prior art keywords
- patterning
- layer
- partly
- photoresist layer
- gate dielectric
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
A kind of thin film transistor (TFT) is made of gate dielectric layer, grid layer, source area, drain region and the lightly mixed drain area of substrate, polysilicon layer, patterning.Wherein, polysilicon layer is arranged in the substrate.In addition, the gate dielectric layer of patterning is arranged on the polysilicon layer, and the gate dielectric layer of patterning has the 3rd partly and the 4th partly, and wherein the 4th partly thickness is less than the 3rd partly thickness.In addition, grid layer is arranged on the gate dielectric layer of patterning partly.In addition, source area and drain region be arranged on patterning gate dielectric layer the 4th partly institute corresponding more than in the crystal silicon layer, and crystal silicon layer is a channel region more than the grid layer institute correspondence.In addition, lightly mixed drain area is arranged on not the 3rd partly more than institute's correspondence in the crystal silicon layer of gate dielectric layer of the patterning that is covered by grid layer.
Description
Technical field
The invention relates to a kind of semiconductor element and manufacture method thereof, and particularly about the invention of a kind of thin film transistor (TFT) and manufacture method thereof.
Background technology
In general element, the running of switch with driving element need be set all.With the active display element is example, and normally (Thin Film Transistor TFT) is used as driving switch with thin film transistor (TFT) for it.And thin film transistor (TFT) can be divided into amorphous silicon (Amorphous Silicon is called for short a-Si) thin film transistor (TFT) and polysilicon (Poly-Silicon) thin film transistor (TFT) according to the material of channel region.Wherein, polycrystalline SiTFT is compared with amorphous silicon film transistor and is had lower consumed power and higher electron mobility.And owing to the development of laser technology, polycrystalline SiTFT manufacturing process temperature is reduced to below 600 degree Celsius, so polycrystalline SiTFT is subjected to the attention in market gradually recently.
Fig. 1 is a kind of diagrammatic cross-section of known thin film transistor (TFT).Please refer to Fig. 1, the method that tradition forms thin film transistor (TFT) is to form cushion 102 prior to substrate 100.Afterwards, on cushion 102, form polysilicon layer 104 and gate dielectric layer 106 successively.Then, on gate dielectric layer 106, form grid layer 108.Then, utilize and implant mask (not expressing among the figure), carry out the ion implantation step,, and more than 108 correspondences of grid layer, form channel region 112 in the crystal silicon layer 104 with formation source area 110a and drain region 110b.Particularly, the thin film transistor (TFT) that comes out for fear of manufacturing has the problem of leakage current (Leakage Current) and hot carrier's effect (Hot CarrierEffect), generally also can be in forming lightly mixed drain area (LightlyDoped Drain, LDD) 114a, 114b between source area 110a and the channel region 112 and between drain region 110b and the channel region 112.Afterwards, form dielectric layer 116 cover gate layers 108 and gate dielectric layer 106.Then, form source electrode conductive layer 118a and drain electrode conductive layer 118b in dielectric layer 116 and gate dielectric layer 106, wherein source electrode conductive layer 118a is electrically connected with source area 110a, and drain electrode conductive layer 118b is electrically connected with drain region 110b.
Yet in above-mentioned manufacturing process, though can be by forming the problem that lightly mixed drain area solves element leakage current and hot carrier's effect or the like, but the formation of this lightly mixed drain area need be implanted mask by another, and the ion implantation step that carries out another time is finished.In other words, in order to form the implantation mask of source/drain region and lightly mixed drain area, need to finish by different light shield manufacturing process separately, but also need carry out the ion implantation step individually.Therefore, making this thin film transistor (TFT) with lightly mixed drain area can say so considerably loaded down with trivial details and time-consuming.And, when successively making the implantation mask of these two differences, the problem of light shield aligning mistake also takes place easily.
Summary of the invention
In view of this, purpose of the present invention just provides a kind of method of manufacturing thin film transistor, to solve the loaded down with trivial details time-consuming problem of known manufacturing technology steps.
Another object of the present invention just provides a kind of thin-film transistor structure, more effectively to improve the problem of leakage current and hot carrier's effect.
The present invention proposes a kind of method of manufacturing thin film transistor, and the method is prior to forming polysilicon layer and gate dielectric layer in the substrate successively.Then, form the photoresist layer of patterning on gate dielectric layer, and the photoresist layer of patterning has first partly and second partly, wherein second partly the thickness is less than first partly the thickness.Afterwards, be mask with the photoresist layer of patterning, the etch-gate dielectric layer, to form the gate dielectric layer of patterning, and the gate dielectric layer of this patterning has the 3rd part and the 4th part, and wherein the 4th part is positioned at the dual-side of the 3rd part, and its thickness is less than the thickness of the 3rd part.Then, with the gate dielectric layer of patterning and the photoresist layer of this patterning is mask, carry out the ion implantation step, partly to form source area and drain region in the crystal silicon layer more than institute's correspondence in the 4th of the gate dielectric layer of patterning, and partly form channel region in the crystal silicon layer more than institute's correspondence in first of the photoresist layer of patterning, and between between channel region and the source area or channel region and drain region, form corresponding lightly mixed drain area.Then, remove the photoresist layer of patterning.Then, on the gate dielectric layer of the patterning of channel region correspondence, form grid layer.
The present invention proposes another kind of method of manufacturing thin film transistor, and the method is prior to forming polysilicon layer, gate dielectric layer and grid layer in the substrate successively.Then, form the photoresist layer of patterning on grid layer, and the photoresist layer of this patterning has first partly and second partly, wherein second partly the thickness is less than first partly the thickness.Afterwards, photoresist layer with patterning is a mask, etching grid layer and gate dielectric layer successively, with the grid layer of formation patterning and the gate dielectric layer of patterning, wherein the gate dielectric layer of patterning has the 3rd part and the 4th part, and the 4th partly is positioned at the dual-side of the 3rd part, and its thickness is less than the thickness of the 3rd part.Then, remove the photoresist layer of patterning.Then, gate dielectric layer with patterning is a mask, carry out the ion implantation step, partly to form source area and drain region in the crystal silicon layer more than institute's correspondence in the 4th of the gate dielectric layer of patterning, and more than the grid layer institute correspondence of patterning, form channel region in the crystal silicon layer, and between between channel region and the source area or channel region and drain region, form corresponding lightly mixed drain area.Particularly, the above-mentioned photoresist layer that removes patterning also can carry out after the ion implantation step.
The present invention proposes a kind of thin film transistor (TFT), is made of gate dielectric layer, grid layer, source area, drain region and the lightly mixed drain area of substrate, polysilicon layer, patterning.Wherein polysilicon layer is arranged in the substrate.In addition, the gate dielectric layer of patterning is arranged on the polysilicon layer, and the gate dielectric layer of patterning has the 3rd partly and the 4th partly, and wherein the 4th partly thickness is less than the 3rd partly thickness.In addition, grid layer is arranged on the gate dielectric layer of patterning partly.In addition, source area and drain region be arranged on patterning gate dielectric layer the 4th partly institute corresponding more than in the crystal silicon layer, and crystal silicon layer is a channel region more than the grid layer institute correspondence.In addition, lightly mixed drain area is arranged on not the 3rd partly more than institute's correspondence in the crystal silicon layer of gate dielectric layer of the patterning that is covered by grid layer.
Since the manufacturing of above-mentioned source/drain region and lightly mixed drain area be gate dielectric layer by single patterning as the implantation mask, and the ion implantation step that carries out taking second place is finished.Therefore, manufacture method of the present invention is compared with known, and is comparatively easy, but also can solve the problem of the aligning mistake that known priority twice light shield manufacturing process produced.
The present invention proposes another method of manufacturing thin film transistor, and the method is prior to forming polysilicon layer, gate dielectric layer and grid layer in the substrate successively.Then, form the photoresist layer of patterning on grid layer, and the photoresist layer of this patterning has first partly and second partly, wherein second partly the thickness is less than first partly the thickness.Afterwards, be mask with the photoresist layer of patterning, the etching grid layer, forming the grid layer of patterning, and the grid layer of patterning has the 5th partly and the 6th partly, and wherein the 6th partly thickness is less than the 5th partly thickness.Afterwards, remove the photoresist layer of patterning.Then, grid layer with patterning is a mask, carry out the first ion implantation step, forming source area and drain region in the crystal silicon layer more than the grid layer that is not patterned covers, and partly form channel region in the crystal silicon layer more than institute's correspondence in the 5th of the grid layer of patterning.Then, remove the 6th part of the grid layer of patterning.Then, be mask with the grid layer of the patterning that remains, carry out the second ion implantation step, between between channel region and the source area or channel region and drain region, to form corresponding lightly mixed drain area.Particularly, the above-mentioned photoresist layer that removes patterning also can carry out after the second ion implantation step.
Since the manufacturing of above-mentioned source/drain region and lightly mixed drain area be gate dielectric layer by single patterning as implanting mask, and priority is carried out the two ion implantation steps that take second place and is finished.Therefore, manufacture method of the present invention is compared with known, and is comparatively easy, but also can solve the problem of the aligning mistake that known priority twice light shield manufacturing process produced.
State with other purpose, feature and advantage and can become apparent on the present invention for allowing, preferred embodiment cited below particularly, and conjunction with figs. are described in detail below.
Embodiment
[first embodiment]
Fig. 2 A to Fig. 2 C is the manufacturing process diagrammatic cross-section according to a kind of thin film transistor (TFT) of a preferred embodiment of the present invention.
At first, please refer to Fig. 2 A, in substrate 200, form polysilicon layer 204 and gate dielectric layer 206 successively.Wherein, substrate 200 for example is a transparent base, for example is glass.In addition, the formation method of polysilicon layer 204 for example is prior to forming amorphous silicon layer (not expressing among the figure) in the substrate 200, carry out excite state atom laser annealing (Excimer Laser Annealing then, ELA) technology, so that amorphous silicon layer fusion (Melting), and form this polysilicon layer 204 by crystallization again (recrystallization).In addition, the material of gate dielectric layer 206 for example is silicon nitride, monox, silicon oxynitride or other suitable material, and its formation method for example is to carry out the long-pending manufacturing process in chemical gaseous phase Shen.In addition, in a preferred embodiment, before forming polysilicon layer 204, also be included in and form cushion 202 in the substrate 200.Wherein, the material of cushion 202 for example is monox or other suitable padded coaming.
Then, on gate dielectric layer 206, form the photoresist layer 208 of patterning.Wherein, the photoresist layer 208 of patterning has the first partly 210a and second 210b partly, and second partly 210b be positioned at first dual-side of 210a partly, and its thickness is less than the thickness of the first part 210a.And the formation method of the photoresist layer 208 of patterning for example is prior to forming photoresist layer (not expressing among the figure) on the gate dielectric layer 206.Afterwards, utilize 212 pairs of photoresist layers of light shield to carry out exposure technology, wherein light shield 212 has at least one half penetrating region 214a, and the second part 210b of the photoresist layer 208 of half penetrating region 214a corresponding patternization.In addition, be example with positive photoresistance, light shield 212 also includes penetrating region 214b and light tight district 214c, the first part 210a of the photoresist layer 208 of wherein light tight district 214c corresponding patternization.Then, the photoresist layer is carried out developing process, with the photoresist layer 208 that forms this patterning.
Afterwards, please refer to Fig. 2 B, is mask with the photoresist layer 208 of patterning, and etch-gate dielectric layer 206 is to form the gate dielectric layer 206a of patterning.Wherein, the gate dielectric layer 206a of patterning has the 3rd partly 216a and the 4th 216b partly, and the 4th partly 216b be positioned at the 3rd dual-side of 216a partly, and its thickness is less than the thickness of the 3rd part 216a.Particularly, when utilizing the photoresist layer 208 of this patterning to come etch-gate dielectric layer 206, can remove the second part 210b of the photoresist layer 208 of patterning, and remove the gate dielectric layer 206 that most of photoresist layer that is not patterned 208 covers, and form the 4th part 216b of the gate dielectric layer 206a of patterning.In addition, second gate dielectric layer 206 of 210b coverings partly of the photoresist layer 208 that is patterned then can not be removed or only has small part to be removed, and behind this etch process, the first part 210a of the photoresist layer 208 that can be patterned comes out.
Then, implant mask, carry out ion implantation step 218, to form source area 220a, drain region 220b, channel region 222 and lightly mixed drain area 224a, 224b with the photoresist layer 208 of patterning and the gate dielectric layer 206a of patterning.Because the thickness that above-mentioned implantation mask has difference therefore for ion implantation step 218, has screening effect in various degree, thereby can form the different zone of impurity concentration by primary ions implantation step 218.Detailed explanation is, the photoresist layer 208 of patterning first partly 210a and patterning gate dielectric layer 206a the 3rd partly the gross thickness of 216a is the thickest, can formation channel region 222 in the crystal silicon layer 204 more than its correspondence.And the thickness of the 3rd part 216a of the gate dielectric layer 206a of the patterning that the first part 210a of the photoresist layer 208 that is patterned comes out takes second place, can be in forming lightly mixed drain area 224a, 224b between channel region 222 and the source area 220a and between channel region 222 and the drain region 220b.In addition, the 4th part 216b thickness of the gate dielectric layer 206a of patterning is the thinnest, so can form denseer source area 220a and the drain region 220b of impurity in the crystal silicon layer 204 more than its correspondence.
In addition, in a preferred embodiment, gross thickness as if the gate dielectric layer 206 that is formed in Fig. 2 A is about 1000 dusts, and the thin film transistor (TFT) of predetermined formation is the thin film transistor (TFT) of P type, then the impurity of being implanted in ion implantation step 218 for example is p type impurities such as boron atom, and the concentration of being implanted for example is 1*10
11~ 1*10
16Atom/square centimeter, and its implantation energy for example is 30keV (keV).In another preferred embodiment, gross thickness as if the gate dielectric layer 206 that is formed in Fig. 2 A is about 1000 dusts, and the thin film transistor (TFT) of predetermined formation is the thin film transistor (TFT) of N type, then the impurity of being implanted in ion implantation step 218 for example is N type impurity such as phosphorus atoms, and the concentration of being implanted for example is 1*10
14~ 1*10
16Atom/square centimeter, and its implantation energy for example is 70keV (keV).
Then, please refer to Fig. 2 C, remove the photoresist layer 208 of patterning.Then, go up in the gate dielectric layer 206a of the patterning of 222 correspondences of channel region and form grid layer 226.
In a preferred embodiment, manufacturings such as conductive layer and drain electrode conductive layer can also drain after forming grid layer 226.Its detailed explanation is to form dielectric layer 228, the gate dielectric layer 206a of cover gate layer 226 and patterning in substrate 200.Then, in the gate dielectric layer 206a of dielectric layer 228 and patterning, define source electrode contact window 230a and drain electrode contact window 230b, to expose source area 220a and drain region 220b.Then, on the dielectric layer 228 of source electrode contact window 230a and drain electrode contact window 230b and part, form conductive layer, to form source electrode conductive layer 232a and drain electrode conductive layer 232b, wherein source electrode conductive layer 232a is electrically connected with source area 220a, and drain electrode conductive layer 232b is electrically connected with drain region 220b.
What deserves to be mentioned is, be positioned at patterning photoresist layer first partly the 210a dual-side second partly its width of 210b w1, w2 there is no special restriction, can identical (shown in Fig. 2 A) or inequality.In a preferred embodiment, if partly width w1, the w2 of the second part 210b of 210a dual-side differ from one another (as shown in Figure 3A) to be positioned at first, then after carrying out steps such as etched film, ion implantation, the width of its lightly mixed drain area of the thin film transistor (TFT) that is formed 224a, 224b also can unequal (shown in Fig. 3 B), promptly forms asymmetric lightly mixed drain area 224a, 224b.In another preferred embodiment, if the second part 210b only is positioned at the side (shown in Fig. 4 A) of the first part 210a, then after carrying out steps such as etched film, ion implantation, only can channel region 222 with form corresponding single lightly mixed drain area 224a or 224b (shown in Fig. 4 B) between the source area 220a or between channel region 222 and the drain region 220b.
In addition, in the above-described embodiment, though only illustrate with single gate dielectric layer 206, non-in order to limit the present invention.In other words, it also can be shown in Fig. 5 A, forms on polysilicon layer 204 by two-layer grid dielectric materials layer 207a, gate dielectric layer 206 that 207b constituted, and wherein the material of this two grid dielectric materials layer 207a, 207b for example is identical or inequality.And, when carrying out gate dielectric layer 206 etchings, the grid dielectric materials layer 207b that covered of the photoresist layer 208 that is not patterned of etching only, and make grid dielectric materials layer 207a come out (shown in Fig. 5 B).
[second embodiment]
In following explanation, mark same as the previously described embodiments part will not given unnecessary details.
Fig. 6 A to Fig. 6 D is the manufacturing process diagrammatic cross-section according to the another kind of thin film transistor (TFT) of a preferred embodiment of the present invention.
At first, please refer to Fig. 6 A, in substrate 200, form polysilicon layer 204, gate dielectric layer 206 and grid layer 226 successively.In a preferred embodiment, before forming polysilicon layer 204, also be included in and form cushion 202 in the substrate 200.
Then, on grid layer 226, form the photoresist layer 208 of patterning.Wherein, the photoresist layer 208 of patterning has the first partly 210a and second 210b partly, and second partly 210b be positioned at first dual-side of 210a partly, and its thickness is less than the thickness of the first part 210a.In addition, the formation method of the photoresist layer 208 of patterning for example is formed by the light shield 212 with at least one half penetrating region 214a, and the second part 210b of the photoresist layer 208 of half penetrating region 214a corresponding patternization.In addition, be example with positive photoresistance, light shield 212 also includes penetrating region 214b and light tight district 214c, the first part 210a of the photoresist layer 208 of wherein light tight district 214c corresponding patternization.
Then, please refer to Fig. 6 B, is mask with the photoresist layer 208 of patterning, and etching grid layer 226 is to form the grid layer 226a of patterning.Wherein, the grid layer 226a of patterning has the 5th partly 300a and the 6th 300b partly, and the 6th partly 300b be positioned at the 5th dual-side of 300a partly, and its thickness is less than the thickness of the 5th part 300a.Formation about the gate dielectric layer 206a of the formation of the grid layer 226a of patterning and the patterning among above-mentioned first embodiment is similar, repeats no more in this.
Afterwards, please refer to Fig. 6 C, is mask with the photoresist layer 208 of patterning and the grid layer 226a of patterning, and etch-gate dielectric layer 206 is with the grid layer 226b of formation patterning and the gate dielectric layer 206a of patterning.Wherein, the first part 210a of the photoresist layer 208 of the grid layer 226b corresponding patternization of patterning, and the gate dielectric layer 206a of patterning has partly 216b of the 3rd part 216a and the 4th, and the 4th part 216b is positioned at the dual-side of the 3rd part 216a, and its thickness is less than the thickness of the 3rd part 216a.Formation about the gate dielectric layer 206a of the formation of the gate dielectric layer 206a of patterning and the patterning among above-mentioned first embodiment is similar, repeats no more in this.
Then, implant mask with the photoresist layer 208 of patterning, the grid layer 226b of patterning and the gate dielectric layer 206a of patterning, carry out ion implantation step 218, partly to form source area 220a and drain region 220b in the crystal silicon layer 204 more than the 216b institute correspondence in the 4th of the gate dielectric layer 206a of patterning, and first of the photoresist layer 208 of patterning partly forms channel region 222 in the crystal silicon layer 204 more than the 210a institute correspondence, and in corresponding lightly mixed drain area 224a, the 224b of formation between channel region 222 and the source area 220a and between channel region 222 and the drain region 220b.Similar with the formation of source area 220a, drain region 220b among above-mentioned first embodiment, channel region 222 and lightly mixed drain area 224a, 224b about source area 220a, drain region 220b, channel region 222 with the formation of lightly mixed drain area 224a, 224b, repeat no more in this.
Then, please refer to Fig. 6 D, remove the photoresist layer 208 of patterning.In a better embodiment, also can and carry out carrying out before the ion implantation step 218 after the gate dielectric layer 206a that forms patterning in the step of the photoresist layer that removes patterning 208 that this carried out.In addition, in a preferred embodiment, manufacturings such as conductive layer and drain electrode conductive layer can also drain after the photoresist layer 208 that removes patterning.Its detailed explanation is to form dielectric layer 228, the gate dielectric layer 206a of cover gate layer 226b and patterning in substrate 200.Then, in the gate dielectric layer 206a of dielectric layer 228 and patterning, define the source electrode contact hole and open 230a and drain electrode contact window 230b, to expose source area 220a and drain region 220b.Then, open on the dielectric layer 228 of 230b and part with the drain electrode contact hole in source electrode contact window 230a and to form conductive layer, to form source electrode conductive layer 232a and drain electrode conductive layer 232b, wherein source electrode conductive layer 232a is electrically connected with source area 220a, and drain electrode conductive layer 232b is electrically connected with drain region 220b.
What deserves to be mentioned is, be positioned at patterning photoresist layer first partly the 210a dual-side second partly its width of 210b w1, w2 there is no special restriction, can identical (as shown in Figure 6A) or inequality.In a preferred embodiment, if be positioned at first second partly its width of 210b w1, the w2 differ from one another (shown in Fig. 7 A) of 210a dual-side partly, then after carrying out steps such as etched film, ion implantation, the width of its lightly mixed drain area of the thin film transistor (TFT) that is formed 224a, 224b also can unequal (shown in Fig. 7 B), promptly forms asymmetric lightly mixed drain area 224a, 224b.In another preferred embodiment, if the second part 210b only is positioned at the side (shown in Fig. 8 A) of the first part 210a, then after carrying out steps such as etched film, ion implantation, only can channel region 222 with form corresponding single lightly mixed drain area 224a or 224b (shown in Fig. 8 B) between the source area 220a or between channel region 222 and the drain region 220b.
In addition, in the above-described embodiment, though only illustrate with single gate dielectric layer 206, non-in order to limit the present invention.In other words, it also can be shown in Fig. 9 A, forms on polysilicon layer 204 by two-layer grid dielectric materials layer 207a, gate dielectric layer 206 that 207b constituted, and wherein the material of this two grid dielectric materials layer 207a, 207b for example is identical or inequality.And, when carrying out gate dielectric layer 206 etchings, the grid dielectric materials layer 207b that covered of the grid layer 226a that is not patterned of etching only, and make grid dielectric materials layer 207a come out (shown in Fig. 9 B).
Utilize above-mentioned first embodiment, second embodiment or the thin film transistor (TFT) of other suitable embodiment gained as shown in figure 10, constituted by gate dielectric layer 504, grid layer 506, source area 508a, drain region 508b and lightly mixed drain area 510a, the 510b of substrate 500, polysilicon layer 502, patterning.
Wherein, polysilicon layer 502 is arranged in the substrate 500.In addition, the gate dielectric layer 504 of patterning is arranged on the polysilicon layer 502, and the gate dielectric layer 504 of patterning has partly 512b of the 3rd part 512a and the 4th, and wherein the 4th part 512b is positioned at the dual-side of the 3rd part 512a, and its thickness is less than the thickness of the 3rd part 512a.
In addition, grid layer 506 is arranged on the 3rd partly on the 512a of gate dielectric layer 504 of the patterning of part.In addition, source area 508a and drain region 508b be arranged on patterning gate dielectric layer 504 the 4th partly 512b institute corresponding more than in the crystal silicon layer 502, and crystal silicon layer 502 is a channel region 514 more than 504 correspondences of gate dielectric layer.In addition, lightly mixed drain area 510a is arranged on not the 3rd partly more than the 512a institute correspondence in the crystal silicon layer 502 of gate dielectric layer 504 of the patterning that is covered by grid layer 506.
In a preferred embodiment, this thin film transistor (TFT) also comprises dielectric layer 516, source electrode conductive layer 518a and drain electrode conductive layer 518b.Wherein, the gate dielectric layer 504 and grid layer 506 of dielectric layer 516 overlay patternization.In addition, source electrode conductive layer 518a is arranged in dielectric layer 516 and the gate dielectric layer 504 and on the dielectric layer 516 of part, and source electrode conductive layer 518a is electrically connected with source area 508a.In addition, drain electrode conductive layer 518b is arranged in dielectric layer 516 and the gate dielectric layer 504 and on the dielectric layer 516 of part, and drain electrode conductive layer 518b is electrically connected with drain region 508b.
In addition, in another preferred embodiment, this thin film transistor (TFT) also comprises cushion 520, is arranged between substrate 500 and the polysilicon layer 502.
Particularly, in another preferred embodiment, the width w3 that is arranged at the lightly mixed drain area 510a between channel region 514 and the source area a08a equals to be arranged at the width w4 (as shown in figure 10) of the lightly mixed drain area 510b between channel region 514 and the drain region 508b.In another embodiment, the width w3 that is arranged at the lightly mixed drain area 510a between channel region 514 and the source area 508a is not equal to the width w4 (as shown in figure 11) that is arranged at the lightly mixed drain area 510b between channel region 514 and the drain region 508b.In another embodiment, lightly mixed drain area 510a or 510b only are arranged between channel region 514 and the source area 508a or between channel region 514 and the drain region 508b (as shown in figure 12).
In sum, in the present invention, can be according to the user demand of difference, utilize light shield to form the photoresist layer of the patterning of variable thickness, thereby the gate dielectric layer that forms variable thickness is used as implanting mask with half penetrating region.Therefore, can take second place in one and finish the manufacturing of source/drain region and lightly mixed drain area in the ion implantation step.In other words, the present invention only need carry out one the light shield manufacturing process, can form the photoresist layer of the patterning of variable thickness, and carrying out steps such as follow-up etched film and ion implantation, so the present invention's method compares with known, and is comparatively easy.In addition, utilize the present invention's method therefore can more effectively improve leakage current and hot carrier's effect according to the lightly mixed drain area not of uniform size of different user demand formation.
[the 3rd embodiment]
In following explanation, mark same as the previously described embodiments part will not given unnecessary details.
Figure 13 A to Figure 13 D is the manufacturing process diagrammatic cross-section according to another thin film transistor (TFT) of a preferred embodiment of the present invention.
At first, please refer to Figure 13 A, in substrate 200, form polysilicon layer 204, gate dielectric layer 206 and grid layer 226 successively.In a preferred embodiment, before forming polysilicon layer 204, also be included in and form cushion 202 in the substrate 200.
Then, on grid layer 226, form the photoresist layer 208 of patterning.Wherein, the photoresist layer 208 of patterning has the first partly 210a and second 210b partly, and second partly 210b be positioned at first dual-side of 210a partly, and its thickness is less than the thickness of the first part 210a.In addition, the formation method of the photoresist layer 208 of patterning for example is formed by the light shield 212 with at least one half penetrating region 214a, and the second part 210b of the photoresist layer 208 of half penetrating region 214a corresponding patternization.In addition, be example with positive photoresistance, light shield 212 also includes penetrating region 214b and light tight district 214c, the first part 210a of the photoresist layer 208 of wherein light tight district 214c corresponding patternization.
Then, please refer to Figure 13 B, is mask with the photoresist layer 208 of patterning, and etching grid layer 226 is to form the grid layer 226a of patterning.Wherein, the grid layer 226a of patterning has the 5th partly 300a and the 6th 300b partly, and the 6th partly 300b be positioned at the 5th dual-side of 300a partly, and its thickness is less than the thickness of the 5th part 300a.Formation about the gate dielectric layer 206a of the formation of the grid layer 226a of patterning and the patterning among above-mentioned first embodiment is similar, repeats no more in this.
Afterwards, grid layer 226a with patterning implants mask, carry out ion implantation step 600, forming source area 220a and drain region 220b in the crystal silicon layer 204 more than the grid layer 226a that is not patterned covers, and in the 5th formation channel region 222 in the crystal silicon layer 204 more than the 300a institute correspondence partly of the grid layer 226a of patterning.
In a preferred embodiment, if the thin film transistor (TFT) of predetermined formation is the thin film transistor (TFT) of P type, then the impurity of being implanted in ion implantation step 600 for example is p type impurities such as boron atom, and the concentration of being implanted for example is 1*10
11~ 1*10
16Atom/square centimeter, and its implantation energy for example is 30keV (keV).In another preferred embodiment, if the thin film transistor (TFT) of predetermined formation is the thin film transistor (TFT) of N type, then the impurity of being implanted in ion implantation step 600 for example is N type impurity such as phosphorus atoms, and the concentration of being implanted for example is 1*10
11~ 1*10
16Atom/square centimeter, and its implantation energy for example is 70keV (keV).
Afterwards, please refer to Figure 13 C, after the 6th part 300b of the grid layer 226a that removes patterning, grid layer 226c with the patterning that remains implants mask, carry out another ion implantation step 602 that takes second place, with in forming lightly mixed drain area 224a, 224b between channel region 222 and the source area 220a and between channel region 222 and the drain region 220b.
In a preferred embodiment, if the thin film transistor (TFT) of predetermined formation is the thin film transistor (TFT) of P type, then the impurity of being implanted in ion implantation step 602 for example is p type impurities such as boron atom, and the concentration of being implanted for example is 1*10
13~ 1*10
15Atom/square centimeter, and its implantation energy for example is 30keV (keV).In another preferred embodiment, if the thin film transistor (TFT) of predetermined formation is the thin film transistor (TFT) of N type, then the impurity of being implanted in ion implantation step 602 for example is N type impurity such as phosphorus atoms, and the concentration of being implanted for example is 1*10
13~ 1*10
15Atom/square centimeter, and its implantation energy for example is 70keV (keV).
Then, please refer to Figure 13 D, remove the photoresist layer 208 of patterning.In a better embodiment, also can and carry out carrying out before the ion implantation step 600 after the grid layer 226a that forms patterning in the step of the photoresist layer that removes patterning 208 that this carried out.In addition, in a preferred embodiment, manufacturings such as conductive layer and drain electrode conductive layer can also drain after the photoresist layer 208 that removes patterning.Its detailed explanation is to form dielectric layer 228, cover gate layer 226c and gate dielectric layer 206 in substrate 200.Then, in dielectric layer 228 and gate dielectric layer 206, define source electrode contact window 230a and drain electrode contact window 230b, to expose source area 220a and drain region 220b.Then, on the dielectric layer 228 of source electrode contact window 230a and drain electrode contact window 230b and part, form conductive layer, to form source electrode conductive layer 232a drain electrode conductive layer 232b, wherein source electrode conductive layer 232a is electrically connected with source area 220a, and drain electrode conductive layer 232b is electrically connected with drain region 220b.
What deserves to be mentioned is, be positioned at patterning photoresist layer first partly the 210a dual-side second partly width w1, the w2 of 210b there is no special restriction, can identical (as shown in FIG. 13A) or inequality.In a preferred embodiment, if be positioned at first second partly width w1, the w2 of 210b differ from one another (shown in Figure 14 A) of 210a dual-side partly, then after carrying out steps such as etched film, ion implantation, its lightly mixed drain area of the thin film transistor (TFT) that is formed 224a, its width of 224b also can unequal (as shown in Figure 14B), promptly form asymmetric lightly mixed drain area 224a, 224b.In another preferred embodiment, if the second part 210b only is positioned at the side (shown in Figure 15 A) of the first part 210a, then after carrying out steps such as etched film, ion implantation, only can channel region 222 with form corresponding single lightly mixed drain area 224a or 224b (shown in Figure 15 B) between the source area 220a or between channel region 222 and the drain region 220b.
In sum, in the present invention, can be according to the user demand of difference, the light shield that utilization has half penetrating region forms the grid layer of the patterning of variable thickness, and the grid layer by this patterning successively carries out the two ion etching steps of taking second place, and finishes the manufacturing of source/drain region and lightly mixed drain area.In other words, only need carry out one the light shield manufacturing process in the present invention, can form the grid layer of the patterning of variable thickness, and utilize it to carry out follow-up ion implantation step as implanting mask.Therefore, the present invention's method is compared with known, and is comparatively easy.In addition, utilize the present invention's method therefore can more effectively improve leakage current and hot carrier's effect according to the lightly mixed drain area not of uniform size of different user demand formation.
Though the present invention with preferred embodiment openly as above; right its is not in order to limit the present invention; the ordinary skill of any technical field that the present invention belongs to; in thought that does not break away from the present invention and scope; when can doing a little change and improvement, so the present invention's protection domain is as the criterion when looking claims person of defining.
Description of drawings
Fig. 1 is a kind of diagrammatic cross-section of known thin film transistor (TFT).
Fig. 2 A to Fig. 2 C is the manufacturing process diagrammatic cross-section according to a kind of thin film transistor (TFT) of the present invention's first preferred embodiment.
Fig. 3 A to Fig. 3 B is the manufacturing process diagrammatic cross-section according to the another kind of thin film transistor (TFT) of the present invention's first preferred embodiment.
Fig. 4 A to Fig. 4 B is the manufacturing process diagrammatic cross-section according to another thin film transistor (TFT) of the present invention's first preferred embodiment.
Fig. 5 A to Fig. 5 B is the manufacturing process diagrammatic cross-section according to another thin film transistor (TFT) of the present invention's first preferred embodiment.
Fig. 6 A to Fig. 6 D is the manufacturing process diagrammatic cross-section according to a kind of thin film transistor (TFT) of the present invention's second preferred embodiment.
Fig. 7 A to Fig. 7 B is the manufacturing process diagrammatic cross-section according to the another kind of thin film transistor (TFT) of the present invention's second preferred embodiment.
Fig. 8 A to Fig. 8 B is the manufacturing process diagrammatic cross-section according to another thin film transistor (TFT) of the present invention's second preferred embodiment.
Fig. 9 A to Fig. 9 B is the manufacturing process diagrammatic cross-section according to another thin film transistor (TFT) of the present invention's second preferred embodiment.
Figure 10 is the diagrammatic cross-section according to a kind of thin film transistor (TFT) of the present invention's preferred embodiment.
Figure 11 is the diagrammatic cross-section according to the another kind of thin film transistor (TFT) of the present invention's preferred embodiment.
Figure 12 is the diagrammatic cross-section according to another thin film transistor (TFT) of the present invention's preferred embodiment.
Figure 13 A to Figure 13 D is the manufacturing process diagrammatic cross-section according to a kind of thin film transistor (TFT) of the present invention's the 3rd preferred embodiment.
Figure 14 A to Figure 14 B is the manufacturing process diagrammatic cross-section according to the another kind of thin film transistor (TFT) of the present invention's the 3rd preferred embodiment.
Figure 15 A to Figure 15 B is the manufacturing process diagrammatic cross-section according to another thin film transistor (TFT) of the present invention's the 3rd preferred embodiment.
The main element description of symbols
100,200,500: substrate
102,202,520:: cushion
104,204,502: polysilicon layer
106,206,206a, 504: gate dielectric layer
108,226,226a, 226b, 226c, 506: grid layer
110a, 220a, 508a: source area
110b, 220b, 508b: drain region
112,222,514: channel region
114a, 114b, 224a, 224b, 510a, 510b: lightly mixed drain area
116,228,516: dielectric layer
118a, 232a, 518a: source electrode conductive layer
118b, 232b, 518b: drain electrode conductive layer
207a, 207b: grid dielectric materials layer
208: the photoresist layer of patterning
210a, 210b: the photoresist layer of the patterning of part
212: light shield
214a: half penetrating region of light shield
214b: the penetrating region of light shield
214c: the light tight district of light shield
216a, 216b, 512a, 512b: the gate dielectric layer of the patterning of part
218,600,602: the ion implantation step
230a: source electrode contact window
230b: drain electrode contact window
300a, 300b: the grid layer of the patterning of part
W1, w2, w3, w4: width
Claims (23)
1. method of manufacturing thin film transistor is characterized in that comprising:
In substrate, form polysilicon layer and gate dielectric layer successively;
Form the photoresist layer of patterning on this gate dielectric layer, and the photoresist layer of this patterning has first partly and second partly, wherein this second partly is positioned at this first partly dual-side, and this second partly thickness is less than this first partly thickness;
Photoresist layer with this patterning is a mask, this gate dielectric layer of etching, to form the gate dielectric layer of patterning, and the gate dielectric layer of this patterning has the 3rd part and the 4th part, wherein, the 3rd part is corresponding to first part and second part of the photoresist layer of this patterning, the 4th partly is positioned at the dual-side of the 3rd part, and the 4th partly thickness is less than the 3rd partly thickness, the photoresist layer of this patterning this second partly in the process of this gate dielectric layer of etching, be removed and the photoresist layer of residual this patterning this first partly;
With this of the photoresist layer of the gate dielectric layer of this patterning and this patterning first is mask partly, carry out the ion implantation step, with in the 4th partly formation source area and drain region in this polysilicon layer of institute's correspondence of the gate dielectric layer of this patterning, and first partly form channel region in this polysilicon layer of correspondence in this of the photoresist layer of this patterning, and between between this channel region and this source area or this channel region and this drain region the corresponding lightly mixed drain area of formation;
Remove this first part of the photoresist layer of this patterning; And
On the gate dielectric layer of this patterning of this channel region correspondence, form grid layer.
2. the method for manufacturing thin film transistor according to claim 1 is characterized in that the formation method of the photoresist layer of this patterning comprises:
On this gate dielectric layer, form the photoresist layer;
Utilize light shield that this photoresist layer is carried out exposure technology, wherein this light shield has at least one half penetrating region, and this half penetrating region to photoresist layer that should patterning this second partly; And
This photoresist layer is carried out developing process.
3. the method for manufacturing thin film transistor according to claim 1 is characterized in that this lightly mixed drain area is formed between this channel region and this source area and between this channel region and this drain region.
4. the method for manufacturing thin film transistor according to claim 3, it is characterized in that being positioned at this of photoresist layer of this patterning, first partly this second partly width of dual-side is identical, and the width that is formed at this lightly mixed drain area between this channel region and this source area equals to be formed at the width of this lightly mixed drain area between this channel region and this drain region.
5. the method for manufacturing thin film transistor according to claim 3, it is characterized in that being positioned at this of photoresist layer of this patterning, first partly this second partly width of dual-side is inequality, and the width that is formed at this lightly mixed drain area between this channel region and this source area is not equal to the width that is formed at this lightly mixed drain area between this channel region and this drain region.
6. the method for manufacturing thin film transistor according to claim 1 is characterized in that also being included in this substrate and forming cushion before forming this polysilicon layer.
7. the method for manufacturing thin film transistor according to claim 1 is characterized in that also comprising after forming this grid layer:
In this substrate, form dielectric layer, cover the gate dielectric layer of this grid layer and this patterning;
In the gate dielectric layer of this dielectric layer and this patterning, define source electrode contact window and drain electrode contact window, to expose this source area and this drain region; And
Formation source electrode conductive layer and drain electrode conductive layer in this source electrode contact window and this drain electrode contact window and on this dielectric layer of part, wherein this source electrode conductive layer is electrically connected with this source area, and should be electrically connected with this drain region by the drain electrode conductive layer.
8. method of manufacturing thin film transistor is characterized in that comprising:
In substrate, form polysilicon layer, gate dielectric layer and grid layer successively;
Form the photoresist layer of patterning on this grid layer, and the photoresist layer of this patterning has first partly and second partly, wherein this second partly is positioned at this first partly dual-side, and this second partly thickness is less than this first partly thickness;
Photoresist layer with this patterning is a mask, this grid layer of etching is to form the grid layer of patterning, wherein the grid layer of this patterning has the 5th part and the 6th part, the 5th part is corresponding to first part of the photoresist layer of this patterning, and the 6th part is corresponding to second part of the photoresist layer of this patterning, the 6th partly thickness is less than the 5th partly thickness, the photoresist layer of this patterning this second partly in the process of this grid layer of etching, be removed and the photoresist layer of residual this patterning this first partly;
With first of the photoresist layer of the grid layer of this patterning and this patterning is mask partly, this gate dielectric layer of etching and form the gate dielectric layer of patterning, the gate dielectric layer of this patterning has the 3rd part and the 4th part, the 3rd part is corresponding to the 5th part and the 6th part of the grid layer of this patterning, and the 4th partly is positioned at the dual-side of the 3rd part, and the 4th partly thickness less than the 3rd partly thickness, the 6th of the grid layer of this patterning partly in the process of this gate dielectric layer of etching, be removed and the grid layer of residual this patterning the 5th partly; And
With the 5th of the grid layer of the gate dielectric layer of this patterning and this patterning is mask partly, carry out the ion implantation step, with in the 4th partly formation source area and drain region in this polysilicon layer of institute's correspondence of the gate dielectric layer of this patterning, and partly form channel region in this polysilicon layer of correspondence in the 5th of the grid layer of this patterning, and between between this channel region and this source area or this channel region and this drain region the corresponding lightly mixed drain area of formation.
9. described according to Claim 8 method of manufacturing thin film transistor is characterized in that the formation method of the photoresist layer of this patterning comprises:
On this grid layer, form the photoresist layer;
Utilize light shield that this photoresist layer is carried out exposure technology, wherein this light shield has one and half penetrating regions at least, and this half penetrating region to photoresist layer that should patterning this second partly; And
This photoresist layer is carried out developing process.
10. described according to Claim 8 method of manufacturing thin film transistor, this lightly mixed drain area of its feature are formed between this channel region and this source area and between this channel region and this drain region.
11. the method for manufacturing thin film transistor according to claim 10, it is characterized in that being positioned at this of photoresist layer of this patterning, first partly this second partly width of dual-side is identical, and the width that is formed at this lightly mixed drain area between this channel region and this source area equals to be formed at the width of this lightly mixed drain area between this channel region and this drain region.
12. the method for manufacturing thin film transistor according to claim 10, it is characterized in that being positioned at this of photoresist layer of this patterning, first partly this second partly width of dual-side is inequality, and the width that is formed at this lightly mixed drain area between this channel region and this source area is not equal to the width that is formed at this lightly mixed drain area between this channel region and this drain region.
13. described according to Claim 8 method of manufacturing thin film transistor is characterized in that also being included in this substrate and forming cushion before forming this polysilicon layer.
14. described according to Claim 8 method of manufacturing thin film transistor, it is characterized in that also comprising the step of this first part of the photoresist layer that removes this patterning, and this step is carried out at after the gate dielectric layer that forms this patterning and carries out before this ion implantation step, or is carried out at after this ion implantation step.
15. the method for manufacturing thin film transistor according to claim 14 is characterized in that carrying out this ion implantation step, and after the photoresist layer that removes this patterning thereafter, also comprises:
In this substrate, form dielectric layer, cover the gate dielectric layer of this grid layer and this patterning;
In the gate dielectric layer of this dielectric layer and this patterning, define source electrode contact window and drain electrode contact window, to expose this source area and this drain region; And
Formation source electrode conductive layer and drain electrode conductive layer in this source electrode contact window and this drain electrode contact window and on this dielectric layer of part, wherein this source electrode conductive layer is electrically connected with this source area, and should be electrically connected with this drain region by the drain electrode conductive layer.
16. a method of manufacturing thin film transistor is characterized in that comprising:
In substrate, form polysilicon layer, gate dielectric layer and grid layer successively;
Form the photoresist layer of patterning on this grid layer, and the photoresist layer of this patterning has first partly and second partly, wherein this second partly is positioned at this first partly dual-side, and this second partly thickness is less than this first partly thickness;
Photoresist layer with this patterning is a mask, this grid layer of etching, to form the grid layer of patterning, and the grid layer of this patterning has the 5th part and the 6th part, wherein, the 5th part is corresponding to first part of the photoresist layer of this patterning, and the 6th part is corresponding to second part of the photoresist layer of this patterning, the 6th partly thickness is less than the 5th partly thickness, the photoresist layer of this patterning this second partly in the process of this grid layer of etching and be removed and the photoresist layer of residual this patterning this first partly;
Grid layer with this patterning is a mask, carry out the first ion implantation step, in not by this polysilicon layer of the grid layer covering of this patterning, forming source area and drain region, and partly form channel region in this polysilicon layer of correspondence in the 5th of the grid layer of this patterning;
Remove the 6th part of the grid layer of this patterning; And
Grid layer with this patterning of remaining is a mask, carries out the second ion implantation step, to form corresponding lightly mixed drain area between between this channel region and this source area or this channel region and this drain region.
17. the method for manufacturing thin film transistor according to claim 16 is characterized in that the formation method of the photoresist layer of this patterning comprises:
On this grid layer, form the photoresist layer;
Utilize light shield that this photoresist layer is carried out exposure technology, wherein this light shield has one and half penetrating regions at least, and this half penetrating region to photoresist layer that should patterning this second partly; And
This photoresist layer is carried out developing process.
18. the method for manufacturing thin film transistor according to claim 16, this lightly mixed drain area of its feature are formed between this channel region and this source area and between this channel region and this drain region.
19. the method for manufacturing thin film transistor according to claim 18, it is characterized in that being positioned at this of photoresist layer of this patterning, first partly this second partly width of dual-side is identical, and the width that is formed at this lightly mixed drain area between this channel region and this source area equals to be formed at the width of this lightly mixed drain area between this channel region and this drain region.
20. the method for manufacturing thin film transistor according to claim 18, it is characterized in that being positioned at this of photoresist layer of this patterning, first partly this second partly width of dual-side is inequality, and the width that is formed at this lightly mixed drain area between this channel region and this source area is not equal to the width that is formed at this lightly mixed drain area between this channel region and this drain region.
21. the method for manufacturing thin film transistor according to claim 16 is characterized in that also being included in this substrate and forming cushion before forming this polysilicon layer.
22. the method for manufacturing thin film transistor according to claim 16, it is characterized in that also comprising the step of the photoresist layer that removes this patterning, and this step is carried out at after the grid layer that forms this patterning and carries out before this first ion implantation step, or is carried out at after this second ion implantation step.
23. the method for manufacturing thin film transistor according to claim 22 is characterized in that carrying out this second ion implantation step, and after the photoresist layer that removes this patterning thereafter, also comprises:
In this substrate, form dielectric layer, cover the gate dielectric layer of this grid layer and this patterning;
In the gate dielectric layer of this dielectric layer and this patterning, define source electrode contact window and drain electrode contact window, to expose this source area and this drain region; And
Formation source electrode conductive layer and drain electrode conductive layer in this source electrode contact window and this drain electrode contact window and on this dielectric layer of part, wherein this source electrode conductive layer is electrically connected with this source area, and should be electrically connected with this drain region by the drain electrode conductive layer.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100971810A CN100557512C (en) | 2004-12-14 | 2004-12-14 | Thin film transistor (TFT) and manufacture method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CNB2004100971810A CN100557512C (en) | 2004-12-14 | 2004-12-14 | Thin film transistor (TFT) and manufacture method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN1790164A CN1790164A (en) | 2006-06-21 |
| CN100557512C true CN100557512C (en) | 2009-11-04 |
Family
ID=36788102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CNB2004100971810A Expired - Fee Related CN100557512C (en) | 2004-12-14 | 2004-12-14 | Thin film transistor (TFT) and manufacture method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN100557512C (en) |
Families Citing this family (10)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100796609B1 (en) | 2006-08-17 | 2008-01-22 | 삼성에스디아이 주식회사 | Fabricating method for cmos thin film transistor and cmos thin film transistor using the same |
| KR101117739B1 (en) * | 2010-03-15 | 2012-02-24 | 삼성모바일디스플레이주식회사 | Thin film transistor and method for fabrication thereof |
| CN104409416B (en) * | 2014-12-11 | 2018-01-23 | 深圳市华星光电技术有限公司 | For making the method and array base palte of array base palte |
| CN104409518B (en) * | 2014-12-11 | 2018-11-09 | 昆山国显光电有限公司 | Thin film transistor (TFT) and preparation method thereof |
| CN104465405B (en) * | 2014-12-30 | 2017-09-22 | 京东方科技集团股份有限公司 | The preparation method of thin film transistor (TFT) and the preparation method of array base palte |
| CN105810573A (en) * | 2016-03-15 | 2016-07-27 | 深圳市华星光电技术有限公司 | Manufacturing method of thin-film transistor |
| CN105870199A (en) * | 2016-05-26 | 2016-08-17 | 深圳市华星光电技术有限公司 | Thin film transistor, preparation method thereof and CMOS (complementary metal oxide semiconductor) device |
| CN110197851A (en) | 2018-02-27 | 2019-09-03 | 京东方科技集团股份有限公司 | Thin film transistor (TFT) and its manufacturing method, array substrate and electronic device |
| CN114730806A (en) * | 2019-12-31 | 2022-07-08 | 广州新视界光电科技有限公司 | Manufacturing method of thin film transistor |
| CN111129162B (en) * | 2019-12-31 | 2022-10-04 | 华南理工大学 | Thin film transistor, display substrate, display panel and display device |
-
2004
- 2004-12-14 CN CNB2004100971810A patent/CN100557512C/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| CN1790164A (en) | 2006-06-21 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US5861334A (en) | Method for fabricating semiconductor device having a buried channel | |
| US7041540B1 (en) | Thin film transistor and method for fabricating the same | |
| KR20000068441A (en) | Asymmetrical transist0r with lightly and heavily doped drain regions and ultra-heavily doped source region | |
| US5917218A (en) | Peripheral circuits including high voltage transistors with LDD structures for nonvolatile memories | |
| US6071775A (en) | Methods for forming peripheral circuits including high voltage transistors with LDD structures | |
| CN100557512C (en) | Thin film transistor (TFT) and manufacture method thereof | |
| JPH10178104A (en) | Method of manufacturing cmosfet | |
| JPH11265987A (en) | Nonvolatile memory and its manufacture | |
| KR960035908A (en) | Manufacturing method of MOS field effect transistor | |
| JP2002124677A (en) | Substrate for liquid crystal displays and its manufacturing method | |
| JP2836515B2 (en) | Method for manufacturing semiconductor device | |
| KR100297731B1 (en) | Method for fabricating a semiconduction device | |
| US6124159A (en) | Method for integrating high-voltage device and low-voltage device | |
| US7351627B2 (en) | Method of manufacturing semiconductor device using gate-through ion implantation | |
| US6171914B1 (en) | Synchronized implant process to simplify NLDD/PLDD stage and N+/P+stage into one implant | |
| JP2896365B2 (en) | Thin film transistor and method of manufacturing the same | |
| JP4510396B2 (en) | Thin film transistor manufacturing method | |
| JPH11186544A (en) | Mos transistor having shallow junction source/drain and manufacture thereof | |
| JPH1131750A (en) | Manufacture of semiconductor element | |
| KR100538100B1 (en) | method of forming high voltage transistor | |
| JPH11220128A (en) | Mosfet and manufacture thereof | |
| JPH05335332A (en) | Thin-film transistor and manufacture thereof | |
| KR100671662B1 (en) | Method of manufacturing a transistor in a flash memory device | |
| KR960006079A (en) | Method of manufacturing thin film transistor | |
| JP4309624B2 (en) | Nonvolatile semiconductor memory device and manufacturing method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20091104 Termination date: 20191214 |
|
| CF01 | Termination of patent right due to non-payment of annual fee |