CN100557819C - Insulated-gate semiconductor device and manufacture method thereof - Google Patents
Insulated-gate semiconductor device and manufacture method thereof Download PDFInfo
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- CN100557819C CN100557819C CNB2004800295286A CN200480029528A CN100557819C CN 100557819 C CN100557819 C CN 100557819C CN B2004800295286 A CNB2004800295286 A CN B2004800295286A CN 200480029528 A CN200480029528 A CN 200480029528A CN 100557819 C CN100557819 C CN 100557819C
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Abstract
The present invention aims to provide a kind of insulated-gate semiconductor device that can easily make and manufacture method thereof, realizes higher withstand voltage design and lower connection resistive arrangement simultaneously.Described semiconductor device comprises N
+Source area 31, N
+Drain region 11, P
-Tagma 41 and N
-Drift region 12.By digging out the subregion on described semiconductor device top, form gate trench 21.Described gate trench 21 comprises gate electrode 22.P floating region 51 is arranged on the below of described gate trench 21.Can form another groove 25 that has different depth with gate trench 21, P floating region 54 is arranged on the below of described groove 25.
Description
Technical field
The present invention relates to a kind of insulated-gate semiconductor device and manufacture method thereof that comprises trench gate structure.More particularly, the present invention relates to a kind ofly be intended to realize the insulated-gate semiconductor device and the manufacture method thereof of high withstand voltage design and low on-resistance design by alleviating electric field on semiconductor layer.
Background technology
Usually suggestion will comprise the insulated-gate semiconductor device of the trench gate type semiconductor device of trench gate structure as the power device special use.In general, for conventional trench gate type semiconductor device, be the balance relation between high withstand voltage design and the low on-resistance design.
For example, patent documentation 1 discloses a kind of trench gate type semiconductor device, has wherein noticed above balance relation.The trench gate type semiconductor device of patent documentation 1 has the structure that Figure 30 schematically shows.That is to say N
+Source area 31 is arranged on the upper surface side of Figure 30, and N
+Drain region 11 is at bottom side.At N
+Source area 31 and N
+Between the drain region 11, set gradually P tagma 41 and N from top
-Drift region 12.In addition, to the boring of part upper surface, and in the boring part, form gate trench 21.And, in gate trench 21, form gate electrode 22.In addition, be close to gate trench 21 belows P floating region 50 is set.In addition, by the gate-dielectric 24 that on the wall of gate trench 21, forms, make gate electrode 22 and 41 insulation of P tagma.
In this trench gate type semiconductor device, when grid voltage turn-offed, depletion layer was from P tagma 41 and N
-The PN junction part of drift region 12 is to N
+Drain region 11 expansion, and another depletion layer from the bottom of P floating region 50 to N
+Drain region 11 expansions.That is to say that P floating region 50 promotes to make N
-Drift region 12 exhausts.Thereby, according to patent documentation 1, can realize draining-the higher withstand voltage design of source electrode portion.
In addition, patent documentation 2 discloses another example of trench gate type semiconductor device.In the trench gate type semiconductor device of patent documentation, P floating region 59 is arranged on the position away from gate trench 21, as shown in figure 31.According to patent documentation 2, P floating region 59 can realize draining-the higher withstand voltage design of source electrode portion, and the insulated-gate semiconductor device of this and Figure 30 is similar.
Make the semiconductor device of Figure 31 by the following method.Be grown to N by epitaxial growth method
+The N of drain region 11
+Be formed for N on the substrate
-The N of drift region 12
-Silicon layer.As shown in figure 31, form N
-Silicon layer is up to plane Z.Then, adopt method such as ion injection to form P floating region 59.In addition, adopt epitaxial growth method to form N once more
-The other parts of silicon layer.Thereby, formed such semiconductor device, wherein P floating region 59 is by N
-The silicon of drift region 12 surrounds fully.It should be noted that by repeating above method, can form a plurality of P floating regions 59 with different depth.
In addition, the terminal area of above-mentioned trench gate type semiconductor device has structure shown in figure 32 usually.That is to say that form P terminals diffusion region 61 in terminal area, its degree of depth is similar to or is deeper than the degree of depth of gate trench 21.Thereby when grid voltage turn-offed, depletion region expansion around the P terminals diffusion region 61 was to alleviate concentrating at the electric field of terminal area.
[patent documentation 1] Japanese Unexamined Patent Publication No 10-98188
[patent documentation 2] Japanese Unexamined Patent Publication No 9-191109
Yet the semiconductor device of Figure 30 has following problem.That is to say the method formation P floating region 50 that injects by ion from the bottom of gate trench 21.So the bottom of gate trench 21 is damage a bit.Therefore, form if gate-dielectric 24 remains under the situation of damaging gate trench 21, Devices Characteristics and reliability may be lower.And gate electrode 22 is facing to P floating region 50.So when grid voltage was connected, in gate electrode 22 inside, specifically, in the part that gate electrode 22 is faced P floating region 50 in the face of the zone and the gate electrode 22 in P tagma 41, electric charge disperseed.As a result, connect resistance and become very big.
On the other hand, with regard to the semiconductor device of Figure 31, P floating region 59 forms away from gate trench 21.So, be intended to realize higher withstand voltage design by avoiding the problem of connecting resistance.Yet, need at least twice epitaxial growth technology to form by N
-The P floating region 54 that drift region 12 surrounds fully, this need spend the suitable time and finish.
In addition, to concentrate in order alleviating at the electric field of terminal area, to need such technology, to form P terminals diffusion region 61, its thickness is different from the thickness of each the P floating region that forms in element area.So the quantity of manufacturing process is bigger, spended time to finish.In addition, because heat load is very big, N
-The diffusion of impurities of drift region 12 (epitaxial loayer), it is inhomogeneous that impurity concentration becomes.For the inhomogeneities of compensated impurity concentration, must increase N
-The thickness of drift region 12, this causes connecting greatly resistance.
For solving at least one in the problems referred to above that conventional trench gate type semiconductor device has, form the present invention.That is to say that the present invention aims to provide and a kind ofly realizes higher withstand voltage design and than low on-resistance design, and insulated-gate semiconductor device and the manufacture method thereof made easily.
Summary of the invention
In order to address the above problem, the invention provides a kind of insulated-gate semiconductor device, comprising: the tagma, be arranged on the upper surface side in the Semiconductor substrate, described tagma is corresponding to the semiconductor of first conduction type; The drift region contacts with the bottom surface in described tagma, and described drift region is corresponding to the semiconductor of second conduction type; And trench portions, be set to penetrate described tagma from the upper surface of described Semiconductor substrate, the bottom surface that arrives described tagma is the plane of below more, wherein said insulated-gate semiconductor device also comprises the floating region that is surrounded by described drift region, described floating region is corresponding to the semiconductor of first conduction type, the bottom of described trench portions is arranged in the described floating region, in described trench portions, be formed with the depositing insulating layer that constitutes by deposition of insulative material and be arranged on described depositing insulating layer top and in the face of the gate electrode in described tagma, and the top of described depositing insulating layer the top of described floating region more above.
That is to say that the insulated-gate semiconductor device of invention has the floating region that is surrounded by the drift region.Because floating region, the drift region exhausts in the time of can promoting to turn-off.In addition, floating region makes and can form the electric field peak in a plurality of parts, thereby can reduce peak-peak.And the insulated-gate semiconductor device of invention has depositing insulating layer in trench portions.Thereby gate-dielectric and gate electrode are not subjected to the influence of trench portions damage.As a result, the deterioration that can the suppression device characteristic and the reduction of reliability.In addition, the top of depositing insulating layer the floating region top more above.Such location prevents that gate electrode and floating region from facing mutually, thus the increase that can suppress to connect resistance.
Floating region in the middle of the insulated-gate semiconductor device of preferred invention also comprises, the top that is arranged on described floating region is top and surrounded by described drift region more, floating region is corresponding to the semiconductor of first conduction type in the middle of described, wherein said trench portions penetrate described in the middle of floating region, and the top of described depositing insulating layer be arranged on described in the middle of floating region the top more the top.
That is to say, and floating region is arranged between tagma and the floating region in the middle of the above-mentioned floating region effect similarly.Thereby, can form the electric field peak three parts at least, thereby can further reduce peak-peak.As a result, can realize higher withstand voltage design and design than low on-resistance.The number of floating region is not limited to one in the middle of it should be noted that, and can be more than two.The number of middle floating region is big more, can form many more electric field peaks, to realize reducing peak-peak.
Preferably the insulated-gate semiconductor device according to the invention of claim 1 also comprises: the secondary trenches part, be set to penetrate described tagma from the upper surface of described Semiconductor substrate, the bottom surface that arrives described tagma is the plane of below more, the inside filling insulating material of described secondary trenches part; And auxiliary floating region, being surrounded by described drift region, described auxiliary floating region is corresponding to the semiconductor of first conduction type, and the bottom of wherein said secondary trenches part is arranged in the described auxiliary floating region.That is to say, in the drift region, form a plurality of floating regions (comprising auxiliary floating region).Because this structure makes that the density of the floating region in the drift region is very high, so can make the manufacturing surplus, for example increases such as size of floating region.
In addition, preferably in the insulated-gate semiconductor device of invention, the degree of depth of described trench portions is different with the degree of depth of described secondary trenches part.Thereby floating region and auxiliary floating region can differently be provided with on thickness direction.Therefore, can form the electric field peak three parts, thereby can further reduce peak-peak.
On the other hand, also the degree of depth of preferred described trench portions is identical with the degree of depth of described secondary trenches part.If the degree of depth of trench portions is identical with the degree of depth of secondary trenches part, then these two parts can form in same manufacturing step.Therefore can reduce the number of manufacturing step.And because adjacent distance of floating between the part is short, even the density height of drift region, depletion layer also can guarantee to connect these parts of floating.So can realize designing than low on-resistance.And, can be taken as the size of floating region very little.In addition, because heat diffusion treatment can be carried out in same manufacturing step, the diffusion of impurity is very little, thereby can suppress because the increase of the connection resistance that heat diffusion treatment causes.The degree of depth and the secondary trenches degree of depth partly that it should be noted that trench portions needn't accurately be coincide mutually.That is to say that the small depth difference that occurs can be considered in the same depth scope when forming groove.
In addition, according to a further aspect in the invention, provide a kind of insulated-gate semiconductor device, having comprised: the tagma, be arranged on the upper surface side in the Semiconductor substrate, described tagma is corresponding to the semiconductor of first conduction type; The drift region contacts with the bottom surface in described tagma, and described drift region is corresponding to the semiconductor of second conduction type; Trench portions is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more; And gate electrode, be arranged in the described trench portions and in the face of described tagma, wherein said insulated-gate semiconductor device also comprises: the secondary trenches part, be set to penetrate described tagma from the upper surface of described Semiconductor substrate, the bottom surface that arrives described tagma is the plane of below more, the inside filling insulating material of described secondary trenches part; And auxiliary floating region, being surrounded by described drift region, described auxiliary floating region is corresponding to the semiconductor of first conduction type, and the bottom of wherein said secondary trenches part is arranged in the described auxiliary floating region.
That is to say that insulated-gate semiconductor device according to a further aspect of the invention has the auxiliary floating region that is surrounded by the drift region.Auxiliary floating region can promote to make the drift region that is in off state to exhaust.And auxiliary floating region is arranged on the below of the secondary trenches part that is used for auxiliary floating region.So, needn't consider the location and the size of gate electrode.Therefore, the design flexibility of auxiliary floating region is very high.On the other hand, that floating region is set is always necessary in the bottom that forms the trench portions of gate electrode therein.So short of ion from the bottom injects, for example the problem of device property deterioration and reliability reduction just can not take place.
The insulated-gate semiconductor device of preferred invention also comprises auxiliary middle floating region, the top that is arranged on described auxiliary floating region is top and surrounded by described drift region more, described auxiliary middle floating region is corresponding to the semiconductor of first conduction type, wherein said secondary trenches partial penetration described auxiliary in the middle of floating region, and the top of described depositing insulating layer be arranged on described auxiliary in the middle of floating region the top more the top.Thereby, can form the electric field peak three parts at least, thereby can reduce peak-peak.Therefore, can realize higher withstand voltage design and design than low on-resistance.
The insulated-gate semiconductor device of preferred invention comprises: the second secondary trenches part, in the face of described secondary trenches part, wherein said gate electrode inserts between the two, described second secondary trenches partly is set to penetrate described tagma from the upper surface of described Semiconductor substrate, the bottom surface that arrives described tagma is the plane of below more, the inside filling insulating material of described second secondary trenches part; And the second auxiliary floating region, being surrounded by described drift region, the described second auxiliary floating region is corresponding to the semiconductor of first conduction type, and the degree of depth of wherein said secondary trenches part is different with the degree of depth of described second secondary trenches part.
That is to say that because the degree of depth of secondary trenches part is different with the degree of depth of second secondary trenches part, floating region can be set on thickness direction different with the second auxiliary floating region.Therefore, can form the electric field peak three parts, thereby can reduce peak-peak.And,, can be taken as heat load very little because the auxiliary floating region and the second auxiliary floating region can form in same heat diffusion treatment.
Preferably in the insulated-gate semiconductor device of invention, observe from the top side of described Semiconductor substrate, the structure of described secondary trenches part is a dot pattern.Thereby current path can be taken as very wide and can realize designing than low on-resistance.
Preferred so formation insulated-gate semiconductor device of the present invention is so that in the zone around the element region, be provided with: terminals trench portions, its inner filling insulating material of using; And the terminals floating region, being surrounded by described drift region, described terminals floating region is corresponding to the semiconductor of first conduction type, and the bottom of described terminals trench portions is arranged in the described terminals floating region.
That is to say, also be arranged on terminal area with the similar floating region of described floating region effect.Thereby, but the butted line end regions is realized higher withstand voltage design.And the size of terminals floating region and floating region is measure-alike in the element area.So determining dimensions is compact and flexibly.And, because terminals floating region and floating region can form in same manufacturing step, so they can easily form.In addition, because these districts form in same manufacturing step, compare with the situation of conventional semiconductor device, heat load is less.
According to the present invention, a kind of manufacture method of insulated-gate semiconductor device also is provided, described insulated-gate semiconductor device comprises: the tagma, be arranged on the upper surface side in the Semiconductor substrate, described tagma is corresponding to the semiconductor of first conduction type; The drift region contacts with the bottom surface in described tagma, and described drift region is corresponding to the semiconductor of second conduction type; Trench portions is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more; And gate electrode, be arranged in the described trench portions and in the face of described tagma, described manufacture method may further comprise the steps: trench portions forms step, has formed thereon in the described Semiconductor substrate in described drift region and described tagma and has formed described trench portions; The impurity implantation step is from forming the bottom implanted dopant of the trench portions that forms the step in described trench portions; The insulating material deposition step, after passing through described impurity implantation step implanted dopant, deposition of insulative material in described trench portions; And floating region formation step, in described insulating material deposition step, behind the implanted dopant, form floating region by carrying out heat diffusion treatment.
In this manufacture method, initial substrate is corresponding to the Semiconductor substrate that so forms, so that the drift region is by formation such as epitaxial growths, and after this introducing technology by the impurity of for example ion injection etc. and heat diffusion treatment forms the tagma thereon.After this, the top from its parent material penetrates tagma formation trench portions in trench portions formation step.Then, form in the step, by forming floating region from the trench portions implanted dopant at floating region.That is to say, after drift region and tagma formation, form floating region.So, after floating region forms, do not need to form the step of monocrystalline silicon layer by epitaxial growth once more.Therefore, available simple manufacturing step manufacturing comprises the insulated-gate semiconductor device of floating region.
The invention manufacture method of the insulated-gate semiconductor device of preferred invention also comprises: trench portions boring step, in described impurity implantation step behind the implanted dopant, further downwards to the bottom hole of described trench portions; And the impurity step of reinjecting, re-inject impurity from the bottom of the described trench portions of described trench portions boring step, further being holed.Thereby, on the thickness direction of the described Semiconductor substrate that forms by epitaxial growth for the first time, form multistage floating region.
Preferably in the manufacture method of the insulated-gate semiconductor device of inventing, form in the step in described trench portions, in the neighboring area of element region and described element region, form described trench portions, and described insulating material deposition step may further comprise the steps: the filling insulating material step forms the inside of the described trench portions that forms in the step with filling insulating material in described trench portions; And deposition materials set-up procedure, in described filling insulating material step, use in the described trench portions of filling insulating material by removing, specifically, the SI semi-insulation material in the described trench portions in described element region, the height of adjustment depositing insulating layer.
That is to say, preferably form in the step, in the neighboring area of element area and terminal area, form trench portions in trench portions.Thereby, under the situation that does not increase the special manufacturing that forms terminal area, can form in the step by the floating region after trench portions forms, in zone, form floating region except element region.And, in the filling insulating material step, with the inside of filling insulating material trench portions.Subsequently, in the deposition materials set-up procedure, after only the trench portions element region is removed the SI semi-insulation material, in gate electrode formation step, in the removal part of trench portions, form gate electrode.Thereby, in element region, form the trench portions that wherein is formed with gate electrode, and in the neighboring area of element region, form its whole trench portions with filling insulating material.
Description of drawings
Fig. 1 shows the sectional view according to the insulated-gate semiconductor device structure of first embodiment;
Fig. 2 shows the sectional view of the insulated-gate semiconductor device structure (the P floating region of two-stage structure) according to first embodiment;
Fig. 3 shows the manufacture method according to the insulated-gate semiconductor device of Fig. 1;
Fig. 4 shows the manufacture method according to the insulated-gate semiconductor device of Fig. 2;
Fig. 5 shows the relation (grid voltage is constant) of the voltage and current of part between drain electrode and the source electrode;
Fig. 6 shows the relation for the voltage and current of part between each grid voltage drain electrode and the source electrode;
Fig. 7 shows the sectional view according to the insulated-gate semiconductor device structure of second embodiment;
Fig. 8 shows the sectional view of the insulated-gate semiconductor device structure (the P floating region of two-stage structure) according to second embodiment;
Fig. 9 shows the sectional view of the insulated-gate semiconductor device structure (the position difference of the thickness direction of P floating region) according to second embodiment;
Figure 10 shows the top view of the insulated-gate semiconductor device array with bar shaped patterned trench;
Figure 11 shows the top view of the insulated-gate semiconductor device array with netted patterned trench;
Figure 12 shows the manufacture method according to the insulated-gate semiconductor device of Fig. 8;
Figure 13 shows the sectional view according to the insulated-gate semiconductor device structure of the 3rd embodiment;
Figure 14 shows the sectional view of the insulated-gate semiconductor device structure (the position difference of the thickness direction of P floating region) according to the 3rd embodiment;
Figure 15 shows the sectional view of the insulated-gate semiconductor device structure (position of the thickness direction of P floating region is identical) according to the 3rd embodiment;
Figure 16 shows the top view of the insulated-gate semiconductor device array (1) with point-like patterned trench;
Figure 17 shows the top view of the insulated-gate semiconductor device array (2) with point-like patterned trench;
Figure 18 shows the manufacture method according to the insulated-gate semiconductor device of Figure 13;
Figure 19 shows the manufacture method according to the insulated-gate semiconductor device of Figure 15;
Figure 20 shows the sectional view according to the insulated-gate semiconductor device terminal structure of the 4th embodiment;
Figure 21 shows the layout according to the semiconductor device of Figure 20 from top view;
Figure 22 shows the manufacture method according to the insulated-gate semiconductor device of Figure 20;
The gesture that Figure 23 shows X-X cross section in according to the semiconductor device of Figure 21 distributes;
Figure 24 shows the field intensity in Y-Y cross section in according to the semiconductor device of Figure 20;
Figure 25 shows the sectional view of conductivity modulation N-type semiconductor N device architecture;
Current path when Figure 26 shows load short circuits in the conventional insulated-gate semiconductor device;
Current path in the insulated-gate semiconductor device among embodiment when Figure 27 shows load short circuits;
Figure 28 shows the sectional view of the insulated-gate semiconductor device structure (1) that wherein forms the hole potential barrier;
Figure 29 shows the sectional view of the insulated-gate semiconductor device structure (2) that wherein forms the hole potential barrier;
Figure 30 shows the sectional view of conventional insulated-gate semiconductor device structure (1);
Figure 31 shows the sectional view of conventional insulated-gate semiconductor device structure (2); And
Figure 32 shows the sectional view of conventional insulated-gate semiconductor device terminal structure.
Embodiment
Specify exemplary embodiment of the present invention below with reference to the accompanying drawings.In an embodiment, the present invention is applied to MOS, to control the conducting of (DS) between drain electrode and the source electrode by insulated gate electrode being applied voltage.
[first embodiment]
Has the structure shown in the sectional view of Fig. 1 at the insulated-gate semiconductor device among first embodiment 100 (hereinafter being called semiconductor device 100).Among Fig. 1, has identical functions with the element that has same reference numerals in the conventional semiconductor device shown in Figure 30.In this specification, the whole assembly that partly is made of initial substrate and the monocrystalline silicon that forms on initial substrate by epitaxial growth is called Semiconductor substrate.
In semiconductor device 100, on the top of Fig. 1 of Semiconductor substrate, and in order to reduce the P that contact resistance is set to high concentration
+Source area 32 forms N together
+Source area 31.On the other hand, in the bottom N is set
+Drain region 11.Between the two, P is set from top
-Tagma 41 and N
-Drift region 12.P
-Tagma 41 and N
-The thickness of the land of drift region 12 (hereinafter being called epitaxial loayer) is about 5.5 μ m (P wherein
-The thickness in tagma 41 is about 1.2 μ m).
By digging out the part top of Semiconductor substrate, form gate trench 21.The degree of depth of gate trench 21 is about 3.2 μ m, and it has penetrated P
-Tagma 41.In the bottom of gate trench 21, form depositing insulating layer 23 by deposition of insulative material.More particularly, form depositing insulating layer 23 by the height of silica being collected about 1.7 μ m apart from the bottom of gate trench 21.On depositing insulating layer 23, further form gate electrode 22 by deposited conductor (for example, polysilicon).The lower end of gate electrode 22 is positioned at P
-The below of 41 bottoms, tagma.By the gate-dielectric 24 that the wall surface at gate trench 21 forms, the N of gate electrode 22 and Semiconductor substrate
+Source area 31 and P
-Tagma 41 is relative.That is to say, by gate-dielectric 24, gate electrode 22 and N
+Source area 31 and P
-Tagma 41 insulation.In semiconductor device 100, by gate electrode 22 is applied voltage, at P with this structure
-Produced channeling effect in the tagma 41, thus control N
+Source area 31 and N
+Conducting between the drain region 11.
In addition, Semiconductor substrate comprises by N
-The P floating region 51 that drift region 12 surrounds.Shown in the sectional view of Fig. 1, the cross section of P floating region 51 is to be the center with gate trench 21 bottoms, and radius is the sub-circular of 0.6 μ m.Spacing with about 3.0 μ m forms each gate trench 21.So, kept enough spaces between adjacent two P floating regions 51,51.Therefore, under on-state, the existence of P floating region 51 can not stop flowing of drain current.The radius of P floating region 51 (about 0.6 μ m) is less than 1/2 of the thickness (about 1.7 μ m) of depositing insulating layer 23.So the position of the upper end of depositing insulating layer 23 is higher than the upper end of P floating region 51.Therefore, the gate electrode 22 that is deposited on the depositing insulating layer 23 is not relative with P floating region 51.
The semiconductor device 100 of embodiment has the P floating region 51 that is arranged on gate trench 21 belows that comprise gate electrode 22, and compares with the insulated-gate semiconductor device that does not have the P floating region, and it has following characteristic.That is to say, when grid voltage turn-offs, by DS voltage, from P wherein
- Tagma 41 is at N
-PN junction position in the drift region 12 forms depletion layer.The peak of field intensity appears near the PN junction position.When the front end of depletion layer arrived P floating region 51, P floating region 51 fell into pass-through state, and electromotive force is fixed.When DS applies voltage when very high, also form depletion layer from the lower end of P floating region 51.The peak of field intensity also appears near the lower end of P floating region 51, but be positioned at P
-The PN junction in tagma 41 separates.That is to say that the peak of electric field can form two positions, thereby can reduce peak-peak.As a result, realized higher withstand voltage design.Since high withstand voltage, by increasing N
-The impurity concentration of drift region 12 can realize designing than low on-resistance.
And because semiconductor device 100 has the depositing insulating layer 23 that is arranged in the gate trench 21, it also has following characteristic.That is to say that because as described belowly form P floating region 51 by ion injection etc. from the bottom of gate trench 21, the bottom of gate trench 21 more or less sustains damage.Yet,, thereby can prevent the defective that device property deterioration for example or reliability reduce because the existence of depositing insulating layer 23 can be avoided the influence of the bottom damage of gate trench 21.And,, weakened the influence in the face of causing of gate electrode 22 and P floating region 51, and reduced P by depositing insulating layer 23
-Connection resistance in the tagma 41.Compare with the structure that does not have depositing insulating layer 23, because gate electrode 22 is less, and gate-to-drain capacitor C gd is little, so switching speed is very fast.
A plurality of P floating regions can be set on the thickness direction of semiconductor device.For example, as shown in Figure 2, two-stage P floating region can be set.In semiconductor device shown in Figure 2 101, compare with semiconductor device 100 shown in Figure 1, the epitaxial loayer and the gate trench 21 of darker (about 8.5 μ m) is set.It also has with the bottom of gate trench 21 is the P floating region 51 at center, and is positioned at P floating region 51 and P
- P floating region 52 between the tagma 41.As a result, from P
-The depletion layer that the PN junction position in tagma 41 forms arrives P floating region 52 earlier, arrives P floating region 51 then.Therefore, except with P
-Beyond the PN junction position in tagma 41, the peak of field intensity appears in the lower end of the lower end of P floating region 52 and P floating region 51.So, formed three electric field peaks, therefore can further reduce peak-peak.In addition, be positioned at P floating region 51 and P by increase
-The number of the P floating region 52 between the tagma 41 can increase the number of peak electric field.Therefore, the number of P floating region 52 is big more, can realize high more withstand voltage design and low more connection resistive arrangement.
Manufacture method with reference to figure 3 explanations semiconductor device 100 shown in Figure 1.At first, by epitaxial growth as N
+The N of drain region 11
+Form N at preceding the end
-The type silicon layer.This N
-Type silicon layer (epitaxial loayer) forms N
-Drift region 12, P
-Tagma 41 and N
+The zone of source area 31.Ion injections by subsequently etc. form P
-Tagma 41 and N
+Source area 31.As a result, at N
+Formation has the Semiconductor substrate of epitaxial loayer on the drain region 11, shown in Fig. 3 (a).
Next, shown in Fig. 3 (b), penetrate P
-Tagma 41 forms gate trench 21, arrives N until its bottom
-Drift region 12.Subsequently, by thermal oxidation, on the wall of gate trench 21, form the oxide-film 95 of the about 50nm of thickness.Then, shown in Fig. 3 (c), begin ion from the bottom of gate trench 21 and inject.Because the sidewall to gate trench 21 does not apply the ion injection, inject so after forming oxide-film 95, carry out ion.After ion injects, remove the oxide-film 95 in the gate trench 21.When buried oxidation film, if there is the interfacial state problem, perhaps be easy to act as most buried insulation material when on silicon face, forming thin oxide film, be preferably formed as the thin heat oxide film of about 50nm so, then the buried insulation material.If the buried insulation material does not need this technology so when being easy to act as most the silicon face exposure.
Shown in Fig. 3 (d), by CVD deposition of insulative material (silica etc.) 23 in gate trench 21.For insulating material and the formation P floating region 51 of annealing, carry out thermal diffusion.As a result, form P floating region 51.The size of P floating region 51 is determined by the bottom size of gate trench 21.The position of P floating region 51 is determined by the degree of depth of groove on thickness direction.That is to say, because P floating region 51 is definite according to gate trench 21, so its accuracy to size is very high.Next, shown in Fig. 3 (e), wherein deposit the Semiconductor substrate of insulating material, remove the SI semi-insulation material by etching.Thereby reserve the space that is used to form gate electrode 22.
On the wall surface of the top of Semiconductor substrate and gate trench 21, form oxide-film 24 by thermal oxidation.Here it is grid oxidation film 24.In the space that previous step is reserved, deposited conductor (polysilicon etc.), and the gate electrode 22 of formation shown in Fig. 3 (f).Then, by forming source electrode and drain electrode, make insulated-gate semiconductor device, promptly semiconductor device 100, shown in Fig. 3 (g).
In manufacture method as shown in Figure 4, make semiconductor shown in Figure 2 101.In this manufacture method, identical with the manufacture method of semiconductor device 100 shown in Figure 1, the ion implantation step (corresponding to Fig. 3 (c)) after forming gate trench 21.After this, the Semiconductor substrate after ion injects, deposition of insulative material is not carried out thermal diffusion.As a result, form P floating region 52, shown in Fig. 4 (d).
Shown in Fig. 4 (e), by etching once more, gate trench 21 is further excavated.Shown in Fig. 4 (f),, on the wall of gate trench 21, form oxide-film 95 by thermal oxidation.From the bottom of gate trench 21, carry out ion once more and inject.Behind the ion infuser, remove the oxide-film 95 in the gate trench 21.When buried oxidation film, if there is the interfacial state problem, perhaps be easy to act as most buried insulation material when on silicon face, forming thin oxide film, be preferably formed as the thin heat oxide film of about 50nm so, then the buried insulation material.If the buried insulation material does not need this technology so when being easy to act as most the silicon face exposure.
Shown in Fig. 4 (g), by CVD deposition of insulative material (silica etc.) 23 in gate trench 21.For insulating material and the formation P floating region 51 of annealing, carry out thermal diffusion.As a result, form P floating region 51.
In the step identical, form the gate electrode 22 that is included in the gate trench 21, shown in Fig. 4 (h) with Fig. 3 (e) technology afterwards.After this, by forming source electrode and drain electrode, make the insulated-gate semiconductor device shown in Fig. 4 (i), promptly semiconductor device 101.By repeating the method for Fig. 4 (d), can on thickness direction, increase the number of P floating region 52 to Fig. 4 (f).
In semiconductor device shown in Figure 1 100, measurement result withstand voltage to DS and connection resistance is explained.When Fig. 5 shows grid voltage Vg and is fixed as 0V, the relation of DS voltage Vds and electric current I ds.As shown in Figure 5, when voltage Vds was 10V to 70V, current value I ds was near constant.When voltage Vds surpassed 72V, current value I ds increased suddenly.When 72V, puncture as can be known.Fig. 6 shows grid voltage Vg when variable, and DS voltage Vds and electric current I ds concern simulation drawing.The gradient of curve is connected resistance corresponding to DS.Usually, the silicon limit (the one pole limit) is represented by the connection resistance (Ron) that following equation (1) calculates.In equation (1), Vb represents withstand voltage.
Ron＝8.33×10
-9(Vb)
2.5 (1)
For example, withstand voltage be under the situation of 72V, connect resistance 36.6m Ω mm
2It is the one pole limit.In this embodiment, for example, when grid voltage Vg=15V, to connect resistance as can be known be 34.0m Ω mm to the slope of curve of Vg=15V from Fig. 6
2So the insulated-gate semiconductor device of this embodiment has realized surpassing the higher connection resistive arrangement of the one pole limit.
[second embodiment]
Identical with the semiconductor device 100 of first embodiment, semiconductor device 200 comprises N
+Source area 31, N
+Drain region 11, P
-Tagma 41 and N
-Drift region 12.By digging out the part top of semiconductor device 200, form gate trench 21.Gate trench 21 comprises gate electrode 22.By the gate-dielectric 24 that on the wall of gate trench 21, forms, gate electrode 22 and P
-Tagma 41 insulation.In semiconductor device 200, by gate electrode 22 is applied voltage, in tagma 41, produced channeling effect, thus control N
+Source area 31 and N
+Conducting between the drain region 11.
Except the gate trench 21 that comprises gate electrode 22, semiconductor device 200 also comprises the groove 25,25 that is arranged on gate trench 21 both sides.Each groove 25 is used filling insulating material.In addition, form and to contact with the bottom of groove 25 and by N
-The P floating region 54 that drift region 12 surrounds.Shown in the sectional view of Fig. 7, P floating region 54 cross sections are to be the sub-circular at center with groove 25 bottoms.
Identical with the semiconductor device 100 among first embodiment, in the semiconductor device 200 of this embodiment,, form the peak of electric field two positions, thereby can reduce peak-peak by forming P floating region 54.Compare with the semiconductor device 100 among first embodiment, it has following feature.That is to say that the structure of gate electrode is identical with conventional structure, and make easily.That is to say that compare with first semiconductor device 100, the distance between gate electrode 22 and the P floating region 54 is bigger.Therefore, than being easier to the holding current path, can realize lower connection resistive arrangement.In addition, because the P floating region relative with gate electrode 22 is set, there is not the problem of the increase of influence that ion injects or connection resistance.
In addition, identical with semiconductor device 100 among first embodiment, a plurality of P floating regions can be set on the thickness direction of semiconductor device.For example, as shown in Figure 8, the P floating region can form two-layer configuration.In semiconductor device shown in Figure 8 201, the groove 25 of formation is deeper than the groove 25 in the semiconductor device shown in Figure 7 200.The gate trench 21 that is used for gate electrode 22 has the identical degree of depth with semiconductor device 200 shown in Figure 7, but in semiconductor device 201, with the bottom of groove 25 be the center P floating region 54 be positioned at P floating region 54 and P
- P floating region 55 between the tagma 41 forms together.As a result, form the electric field peak three positions, thereby can realize higher withstand voltage design and lower connection resistive arrangement.
In addition, as shown in Figure 9, the groove 26 that its degree of depth is different with the degree of depth of groove 25 can have the gate electrode 22 that is arranged between groove 25 and the groove 26.This groove 26 is also used filling insulating material, and its bottom is arranged in P floating region 56.That is to say that P floating region 56 is arranged on the thickness direction position different with P floating region 54.So,, form the electric field peak three positions with identical in the semiconductor device 201 shown in Figure 8.So, can realize higher withstand voltage design and lower connection resistive arrangement.In semiconductor device 202, in order on Width, to connect depletion layer more reliably, groove pitch is designed to be narrower than slightly groove pitch in the semiconductor device 201.In semiconductor device 202, only a P floating region contacts with each groove, and the ion of each P floating region injects and thermal diffusion process only need be carried out once so be used to form.Therefore, can minimize because the deterioration in characteristics that thermal diffusion process causes.Can fill each groove in the same way, thereby simplify manufacture method.
The shape of each groove is rectangular, netted, point-like on the depth direction etc. among the figure.For higher withstand voltage design, strip shown in Figure 10 or shown in Figure 11 netted can be effective.
Manufacture method with reference to the semiconductor device 201 shown in Figure 12 key diagram 8.The gate electrode 22 and the gate trench 21 of semiconductor device 201 have general structure, form by known manufacture method.Shown in Figure 12 (a), by penetrating P
-The tagma forms groove 25, and its bottom is up to N
-Drift region 12.Then, carrying out ion from the bottom of groove 25 injects.Subsequently, carry out thermal diffusion process.As a result, form P floating region 55.Under this state, based on Semiconductor substrate, deposition of insulative material in groove 25, and form source electrode and drain electrode, so make semiconductor device 200 as shown in Figure 7.
Shown in Figure 12 (b),, excavate groove 25 by etching once more.From the bottom of groove 25, carry out ion once more and inject.Shown in Figure 12 (c), by CVD deposition of insulative material 23 in gate trench 21.Subsequently, for insulating material and the formation P floating region 54 of annealing, carry out thermal diffusion process.As a result, form P floating region 54.Then, by forming source electrode and drain electrode, make the insulated-gate semiconductor device shown in Figure 12 (d), promptly semiconductor device 201.
[the 3rd embodiment]
Identical with the semiconductor device 200 of the semiconductor device 100 of first embodiment and second embodiment, semiconductor device 300 comprises N
+Source area 31, N
+Drain region 11, P
-Tagma 41 and N
-Drift region 12.By digging out the part top of semiconductor device 300, form gate trench 21.In the bottom of gate trench 21, form depositing insulating layer 23 by deposition of insulative material.Further on depositing insulating layer 23, form gate electrode 22.By the gate-dielectric 24 that on the wall of gate trench 21, forms, gate electrode 22 and P
-Tagma 41 insulation.In semiconductor device 300, by gate electrode 22 is applied voltage, in tagma 41, produce channeling effect, thus control N
+Source area 31 and N
+Conducting between the drain region 11.
Except the gate trench 21 that contains gate electrode 22, Semiconductor substrate also has in gate trench 21 both sides and is deeper than the groove 25,25 of gate trench 21.Groove 25 is used filling insulating material.In addition, form by N
-The P floating region 51,54 that drift region 12 surrounds.Shown in the sectional view of Figure 13, the cross section of P floating region 51,54 is that the bottom with groove 25 is the sub-circular at center.In this specification, wherein the location P floating region of bottom that is used for the gate trench 21 of gate electrode is called " P floating region 51 ", and wherein the location P floating region of bottom that is used for the gate trench 25 of P floating region is called " P floating region 54 ".
Adjacent P floating region 51,54 is set, so that they do not contact mutually.If adjacent P floating region is in contact with one another, current path is very narrow during connection, increases thereby connect resistance.P floating region 51 is arranged on the extreme position of depletion layer, and this depletion layer is from P when turn-offing
-Tagma 41 and N
-The PN junction of drift region 12 is expanded downwards, before puncturing generation, arrives P floating region 51 always.This is to be directly proportional with the degree of depth of depletion layer because of withstand voltage, if P
-Distance between tagma 41 and the P floating region 51 is very short, so withstand voltage diminishing.P floating region 54 is arranged on the extreme position of depletion layer, and this depletion layer is expanded downwards from P floating region 51, before puncturing generation, up to arriving P floating region 54.This also is intended to realize optimum high withstand voltage design.
In the semiconductor device 300 of this embodiment, P floating region 51,54 is arranged on the bottom of the gate trench 21 that is used for gate electrode and is used for the bottom of the groove 25 of P floating region, and gate trench 21 has the different degree of depth with groove 25, so form the electric field peak three positions, this is identical with semiconductor device 201 shown in Figure 8 or semiconductor device 202 shown in Figure 9.Therefore higher withstand voltage design and lower connection resistive arrangement have been realized.
Different with Figure 13 and semiconductor device shown in Figure 14, in semiconductor device shown in Figure 15 302, the groove 25 that is used for the gate trench 21 of gate electrode and is used for the P floating region can form has same depth.This semiconductor device 302 produces following advantage.That is to say, because two kinds of grooves can form in same technology, so can reduce the number of technology.And the distance of adjacent P floating region is very short, and if N
-Drift region 12 dense can connect depletion layer reliably.Therefore, can realize lower connection resistive arrangement.Because realized higher withstand voltage design by a plurality of P floating regions 51,54, the size of each P floating region 51,54 can be very little.Therefore, the accelerating voltage in the time of can reducing the ion injection, and can suppress ion and inject the damage that causes.Compare with the semiconductor device with different gash depths, the thickness of epitaxial loayer can be less.Because the number of times of heat diffusion treatment is less, thus the diffusion of impurity can be suppressed, thus can suppress the increase of the connection resistance that causes by heat diffusion treatment.
The shape of groove can be an arbitrary shape in the semiconductor device 302 shown in Figure 15, and this is identical with other semiconductor device, comprises strip (see figure 10), netted (seeing Figure 11) and point-like.Because compare with other structure, the density of each P floating region is very high in the semiconductor device 302, so the manufacturing surplus broad of size etc.By utilizing this advantage, can form point-like groove 25 as shown in figure 16.In this layout, because part has been removed P floating region 54, current path is very wide, thereby realizes lower connection resistive arrangement.Even for the expansion that makes depletion layer, the distance of groove is set to evenly.In addition, netted at the partitioning portion formation gate trench 21 of groove 25 as shown in figure 17 to form, thus therefore the regional broad of gate electrode 22 realizes the gate electrode than low on-resistance.Section A-A among Figure 16 or the section B-B among Figure 17 are corresponding to the semiconductor device among Figure 15 302.
Manufacture method with reference to the semiconductor device 300 shown in Figure 18 key diagram 13.The gate electrode 22 of semiconductor device 300 and gate trench 21 have with Fig. 1 in semiconductor device 100 in identical structure, and the employing manufacture method identical with manufacture method shown in Figure 3 forms.At first, by the etching shown in Figure 18 (a), form the groove 25 that is deeper than gate trench 21.By thermal oxidation subsequently, on the wall of groove 25, form oxide-film 95.Carry out ion once more injects from the bottom of groove 25.After ion injects, remove the oxide-film 95 in the groove 25.When buried oxidation film, if there is the interfacial state problem, perhaps be easy to act as most buried insulation material when on silicon face, forming thin oxide film, be preferably formed as the thin heat oxide film of about 50nm so, then the buried insulation material.If the buried insulation material does not need this technology so when being easy to act as most the silicon face exposure.
Further, deposition of insulative material in groove.Subsequently, for insulating material and the formation P floating region 54 of annealing, carry out heat diffusion treatment.As a result, form P floating region 54 in the thickness direction position that is different from P floating region 51.Shown in Figure 18 (b), in groove 25, form depositing insulating layer 23.Then, by forming source electrode and drain electrode, make the insulated-gate semiconductor device shown in Figure 18 (c), promptly semiconductor device 300.Technology that can be identical only changes the degree of depth of groove, makes semiconductor device 301 shown in Figure 14.
In this manufacture method, before groove 25, form gate trench 21, this is intended to reduce heat load.Yet,, can form groove 25 earlier by reducing the gate oxidation temperature.
Manufacture method with reference to the semiconductor device 302 shown in Figure 19 key diagram 15.At first, shown in Figure 19 (a), penetrate P
-Tagma 41 forms gate trench 21 and groove 25, arrives N up to its bottom
-Drift region 12.Because two kinds of grooves form simultaneously, so they have the identical degree of depth.By thermal oxidation subsequently, on the wall of each groove, form oxide-film 95.Carry out ion injects from the bottom of each groove.After ion injects, remove the oxide-film 95 of each groove.When buried oxidation film, if there is the interfacial state problem, perhaps be easy to act as most buried insulation material when on silicon face, forming thin oxide film, be preferably formed as the thin heat oxide film of about 50nm so, then the buried insulation material.If the buried insulation material does not need this technology so when being easy to act as most the silicon face exposure.
Further, deposition of insulative material in each groove.As a result, in each groove, form deposition of insulative material 23.Subsequently, for insulating material and formation P floating region 51 and the P floating region 54 of annealing, carry out heat diffusion treatment.As a result, form P floating region 51 and P floating region 54 simultaneously by a step heat diffusion treatment.As a result, shown in Figure 19 (b), below gate trench 21, form P floating region 51, and below groove 25, form P floating region 54.
By etching deposit insulating barrier 23 in gate trench 21, remove part depositing insulating layer 23.Further, by thermal oxidation on the wall of gate trench 21, form oxide-film 24.This is a grid oxidation film 24.By deposited conductor in gate trench 21, form the gate electrode 22 that is included in the gate trench 21, shown in Figure 19 (c).Then, by forming source electrode and drain electrode, make insulated-gate semiconductor device, i.e. semiconductor device 302 shown in Figure 19 (d).
[the 4th embodiment]
Has the structure shown in the sectional view of Figure 20 at the insulated-gate semiconductor device among the 4th embodiment 400 (hereinafter being called semiconductor device 300).Semiconductor device 400 has the terminal structure different with conventional semiconductor device.Identical with the semiconductor device 100 of first embodiment, the semiconductor device 400 of this embodiment comprises N
+Source area 31, N
+Drain region 11, P
-Tagma 41, N
-Drift region 12 and the gate trench 21 that comprises gate electrode 22.By gate electrode 22 being applied voltage, control N
+Source area 31 and N
+Conducting between the drain region 11.In this manual, at the periphery of element region (element area), the zone that is used as terminals is called " terminal area ".
As shown in figure 21, in the terminal area of semiconductor device 400, form terminals groove 62 with the embracing element zone.The inside of terminals groove 62 shown in Figure 20 insulating material (silica etc.) complete filling.Below terminals groove 62, P floating region 51 has the P floating region 53 of same function among the formation and first embodiment.
Below by reference Figure 22, the manufacture method of semiconductor device 400 is described, mainly be about terminal area.At first, shown in Figure 22 (a), at N
+Form epitaxial loayer (N on the drain region 11
- Drift region 12, P
-Tagma 41, N
+Source area 31).Identical among details and first embodiment.On Semiconductor substrate, form gate trench 21 then.At this moment, in terminal area, also form terminals groove 62 simultaneously.Shown in Figure 22 (b),, form P floating region 51,53 by injecting from the bottom ion.
Shown in Figure 22 (c),, form depositing insulating layer 23 by deposition of insulative material in each groove.Shown in Figure 22 (d), on the terminal area at Semiconductor substrate top, form resist 96.Utilize resist 96 as mask, the etching insulating material.As a result, the height of depositing insulating layer 23 obtains adjusting.When this etching, by the deposition of insulative material of resist 96 protections in terminal area.Therefore, only the height of the deposition of insulative material in element area is adjusted.So, do not remove the insulating material in the terminals groove 62 fully, terminals groove 62 keeps being filled.After the Height Adjustment of deposition of insulative material, remove resist 96.
Shown in Figure 22 (e), on the wall of the top of Semiconductor substrate and gate trench 21, form oxide-film, and in gate trench 21 deposited conductor 22.As a result, in gate trench 21, form gate electrode 22.If need, can further form P
+Source area 32.Then, by forming source electrode and drain electrode, make insulated-gate semiconductor device, i.e. semiconductor device 400 shown in Figure 22 (f).
Field intensity analog result to semiconductor device 400 is illustrated.In this simulation, determined the field strength distribution of Figure 21 middle section X-X.Figure 23 shows the equipotential lines in the semiconductor device 400.As shown in figure 23, the electric field peak appears at two positions, i.e. P
-Tagma 41 and N
-Near the PN junction of the drift region 12 and lower end of P floating region 52.The curve of Figure 24 shows the field intensity in the Y-Y cross section of Figure 20.The longitudinal axis is represented field intensity (V/cm), and transverse axis is represented the distance (μ m) with the Semiconductor substrate end face.Field intensity in the Y-Y cross section shows two positions, promptly apart from the peak at about 1.5 μ m of end face and 3.5 μ m places, as shown in figure 24.From curve also as can be known, at P
-Tagma 41 and N
-Near the PN junction of drift region 12 and in the lower end of P floating region 52, electric field reaches peak value.Hence one can see that, alleviated concentrating of electric field in terminal area and element area.
By terminals groove 62 and corresponding P floating region 52, the semiconductor device 400 of this embodiment has been realized higher withstand voltage design.As a result, compare, have following feature with conventional insulated-gate semiconductor device shown in Figure 32.That is to say that in the semiconductor device 400 of this embodiment, the P floating region 53 of terminal area can the technology identical with the P floating region 51 of element area be made, and has therefore reduced the number of technology, makes easily.Compare with P terminals diffusion region 61, the heat load of P floating region 53 is less.So, can form the less N of thickness
-Drift region 12 (epitaxial loayer), thus connection resistance can be reduced.The size of P floating region 53 little than in the conventional P terminals diffusion region 61.Therefore, controlling dimension easily.
In semiconductor device 400, form three terminals grooves 62, but the number of terminals groove 62 is not limited to this.The number of terminals groove 62 is big more, and is withstand voltage high more.For example, under the situation of semiconductor device 400, the number of supposing terminals groove 62 is one, and so withstand voltage is 50V.By comparison, be increased to two by number with terminals groove 62, the withstand voltage 64V that rises to, and by number being increased to three, the withstand voltage 72V that rises to.On the other hand, by increasing the number of groove, the space of terminal area broadens, and this contradicts with the compact design of entire semiconductor device.So, according to withstand voltage formation terminals groove 62.Improve withstand voltage by the spacing between the adjacent line end groove 62 of optimization.Specifically, in semiconductor device 400, compare with the distance (3 μ m) between the gate trench 21, (2 μ m) is designed to nearer with the distance between the terminals groove 62.In this embodiment, terminals groove 62 is formed in the elongated channels, but is not limited thereto.For example, it can form poroid.
As said, in the semiconductor device 100 (Fig. 1) of first embodiment, in epitaxially grown single-step process, form epitaxial loayer (N
-Drift region 12), and further injects and thermal diffusion, in epitaxial loayer, form P by ion
-Tagma 41.Have formation gate trench 21 on the Semiconductor substrate of this epitaxial loayer, and passing through to form P floating region 51 from the ion injection of the bottom of gate trench.That is to say,, only need a step epitaxial growth technology for forming P floating region 51.When in as semiconductor device 101 (Fig. 2), on thickness direction, making a plurality of P floating region 52 or when in as semiconductor device 400 (Figure 20), in terminal area, also being like this during manufacturing P floating region 53.By P floating region 51, when turn-offing grid voltage, promote N
-Exhausting of drift region 12, and can alleviate concentrating of electric field.Therefore, realize higher withstand voltage design and lower connection resistive arrangement, and realized the insulated-gate semiconductor device and the manufacture method thereof of easy manufacturing.
In gate trench 21, can form depositing insulating layer 23.As a result, under the situation of the influence that is not subjected to the ion injection, can form gate-dielectric 24 and gate electrode 22.Therefore, but the decline of the deterioration of characteristic and reliability between inhibition period.The upper end of depositing insulating layer 23 is positioned at the position of the upper end that is higher than P floating region 51.Therefore, can prevent facing between gate electrode 22 and the P floating region 51.So, the increase that can prevent to connect resistance.
In semiconductor device 101 (Fig. 2), at P
-Form P floating region 52 between tagma 41 and the P floating region 51.As a result, form the peak of electric field three positions, thereby can further reduce peak-peak.Therefore, by forming P floating region 52, can realize higher withstand voltage design and lower connection resistive arrangement.
In the semiconductor device 200 (Fig. 7) of second embodiment, be provided for the groove 25 of P floating region.That is to say, the groove that does not comprise gate electrode 22 is set.On the other hand, below the gate trench 21 that comprises gate electrode 22, the P floating region is not set.Therefore, there is not ion injection effect for example or connect the problem that resistance increases.Below the groove 25 that forms for the P floating region, P floating region 54 is set.Therefore, needn't consider the position or the size of gate electrode 22, thereby improve the degree of freedom of design.Distance between gate electrode 22 and the P floating region 54 is than the length in first semiconductor device 100.So,, when guaranteeing higher withstand voltage design, can more easily guarantee current path, and can realize lower connection resistive arrangement with identical in the semiconductor device 100 of first embodiment.
In semiconductor device 201 (Fig. 8), at P
-Form P floating region 55 between tagma 41 and the P floating region 54.As a result, form the peak of electric field three positions, thereby can further reduce peak-peak.In semiconductor device 202 (Fig. 9), form groove 25, and a P floating region 54 is set in each beneath trenches with different depth.So, the deterioration in characteristics that is caused by heat diffusion treatment can be remained least limit, thereby can realize higher withstand voltage design and lower connection resistive arrangement.
In the semiconductor device 300 (Figure 13) of the 3rd embodiment, be provided for the gate trench 21 of gate electrode and be used for the groove 25 of P floating region, and P floating region 51,54 further is set below these two kinds of grooves.And gate trench 21 has the different degree of depth with groove 25.As a result, form the peak of electric field in a plurality of positions, thereby can further reduce peak-peak.
In semiconductor device 302 (Figure 15), form gate trench 21 and groove 25 with the same degree of depth.Therefore, gate trench 21 and groove 25 can form in same step process.That is to say, reduced the number of technology.And heat diffusion treatment also can be carried out in same step process, and the diffusion of impurity is less, thereby can suppress the increase of the connection resistance that heat diffusion treatment causes.Simultaneously, " the same degree of depth " and do not mean that the accurately identical degree of depth.The small depth offset that takes place during forming groove is also included within the scope of the same degree of depth.
In the semiconductor device 400 (Figure 20) of the 4th embodiment, terminal area also comprises P floating region 53.Therefore, not only in element area, and in terminal area, can realize higher withstand voltage design.This P floating region 53 can form in same step process with P floating region 51 in the element area.Therefore, can fewer purpose technology constitute terminal structure.Compare with conventional semiconductor device, P floating region 53 does not need very wide space.So dimensional controllability is good, thereby semiconductor device itself is compact.
Embodiment only is an example, is not to be intended to limit the scope of the invention.So, in the scope that does not depart from true spirit of the present invention, can change freely or revise the present invention.For example, can between P type and N type, carry out the exchange of semiconductor regions.Gate-dielectric 24 is not limited to oxide-film, can comprise nitride film, other dielectric film or combined films.Semiconductor is not limited to silicon, can comprise the semiconductor (SiC, GaN, GaAs etc.) of other type.
In semiconductor device shown in Figure 20 400, the groove 62 insulating material complete filling in the terminal area, but identical with gate trench 21 in the element area, can come deposited conductor by removing the SI semi-insulation material.In this case, the conductor in the terminals groove 62 is not electrically connected with grid wiring.Even in such semiconductor device, can in fewer purpose technology, realize the higher withstand voltage design of terminal area.
Insulated-gate semiconductor device of the present invention also can be applicable to adopt in the MOS or conductivity modulation type MOS of P type substrate 13 shown in Figure 25.
The insulated-gate semiconductor device of embodiment also has following characteristic except having characteristic described here.That is to say that because hole accumulation in P floating region 51, P floating region 51 becomes the source of supply in hole.As a result, at N
-In the surf zone of drift region 12, specifically, be higher than in the zone of P floating region 51, can increase hole concentration in its position.As a result, reduced loss.And, owing to below gate electrode 22, form depositing insulating layer 23, so gate-to-drain electric capacity (Cgd) is very little.Therefore, can reduce transmission failure or drive loss.
Because also form depletion layer, so withstand voltage when having improved load short circuits from P floating region 51.That is to say, in not having the conventional insulated-gate semiconductor device of P floating region 51, when load short circuits, as shown in figure 26, from P
-Tagma 41 and N
-The drain side of the PN junction of drift region 12 forms depletion layer 15, the regional electric current below gate trench 21 flow (seeing the arrow among Figure 26).On the other hand, in the insulated-gate semiconductor device 100 of embodiment, below gate electrode 22, form depositing insulating layer 23, so electric current is mobile along gate trench 21, as shown in figure 27.Also form depletion layer 15 from P floating region 51.Therefore, current path very narrow (seeing the arrow among Figure 27) when load short circuits.As a result, short circuit current reduces, thus withstand voltage when increasing load short circuits.
Shown in Figure 28 and 29, the present invention also can be applicable at P
-Tagma 41 and N
-Form MOS between the drift region 12 as the barrier region, N hole 18 of hole potential barrier.Under the situation of the MOS that forms barrier region, N hole 18, the expansion of depletion layer is very narrow in barrier region 18, N hole.So, can reduce withstand voltage.Yet, in MOS, except by P with P floating region 51
-Tagma 41 and N
-Beyond the depletion layer that PN junction between the drift region 12 forms, also form depletion layer from P floating region 51, thereby can suppress withstand voltage reduction.
Industrial usability
According to the present invention, by the floating region that is surrounded by the drift region, can realize higher withstand voltage design and Lower connection resistive arrangement. By depositing insulating layer, can avoid the impact of Impurity injection. By Bottom Implantation from groove can form floating region, and the multiple passage epitaxial growth does not form silicon layer. So when having realized higher withstand voltage design and lower connection resistive arrangement, having provided can Insulated-gate semiconductor device and the manufacture method thereof easily made.
Claims (17)
1. insulated-gate semiconductor device comprises:
The tagma is arranged on the upper surface side in the Semiconductor substrate, and described tagma has the semiconductor of first conduction type;
The drift region contacts with the bottom surface in described tagma, and described drift region has the semiconductor of second conduction type; And
Trench portions is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more,
Wherein said insulated-gate semiconductor device also comprises the floating region that is surrounded by described drift region, and described floating region has the semiconductor of first conduction type,
The bottom of described trench portions is arranged in the described floating region,
In described trench portions, be formed with the depositing insulating layer that constitutes by deposition of insulative material and be arranged on described depositing insulating layer top and in the face of the gate electrode in described tagma, and
The lower end of described gate electrode the top of described floating region more above,
The interval between the lower end of the lower end of described depositing insulating layer and described floating region is wider than at interval between the bottom surface in described tagma and the top of described floating region,
The interval between the top of the bottom surface in described tagma and described floating region is wider than at interval between the lower end of described gate electrode and the lower end of described depositing insulating layer,
Between the adjacent floating region is such interval at interval, and under this interval, at the blocking interval of grid voltage, the depletion layer that forms from described adjacent floating region in the mid portion between described floating region on the direction that connects described floating region is connected to each other, and
The thickness of described depositing insulating layer forms the thickness at electric field peak for be enough to two positions on the thickness direction in described Semiconductor substrate at the blocking interval of grid voltage.
2. according to the insulated-gate semiconductor device of claim 1, floating region in the middle of also comprising, the top that is arranged on described floating region is top and surrounded by described drift region more, described in the middle of floating region have the semiconductor of first conduction type,
Wherein said trench portions penetrates described middle floating region, and
The top of described depositing insulating layer be arranged on described in the middle of floating region the top more the top.
3. according to the insulated-gate semiconductor device of claim 1, also comprise:
The secondary trenches part is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more, the inside filling insulating material of described secondary trenches part; And
Auxiliary floating region is surrounded by described drift region, and described auxiliary floating region has the semiconductor of first conduction type,
The bottom of wherein said secondary trenches part is arranged in the described auxiliary floating region.
4. according to the insulated-gate semiconductor device of claim 3, the degree of depth of wherein said trench portions is different with the degree of depth of described secondary trenches part.
5. according to the insulated-gate semiconductor device of claim 3, the degree of depth of wherein said trench portions is identical with the degree of depth of described secondary trenches part.
6. according to the insulated-gate semiconductor device of claim 3, wherein observe from the top side of described Semiconductor substrate, the structure of described secondary trenches part is a dot pattern.
7. according to the insulated-gate semiconductor device of claim 1,
Wherein in the zone around the element region, be provided with:
The terminals trench portions, its inner filling insulating material of using; And
The terminals floating region is surrounded by described drift region, and described terminals floating region has the semiconductor of first conduction type, and
The bottom of described terminals trench portions is arranged in the described terminals floating region, and
Interval between the adjacent line end floating region is narrower than the interval between the top of the bottom surface in described tagma and described terminals floating region.
8. according to the insulated-gate semiconductor device of claim 1, wherein
Described floating region has the cross sectional shape of sub-circular, and the radius of wherein said floating region is less than half of the thickness of described depositing insulating layer, and the semiconductor of the semiconductor of wherein said first conduction type and described second conduction type is made by silicon.
9. insulated-gate semiconductor device comprises:
The tagma is arranged on the upper surface side in the Semiconductor substrate, and described tagma has the semiconductor of first conduction type;
The drift region contacts with the bottom surface in described tagma, and described drift region has the semiconductor of second conduction type;
Trench portions is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more; And
Gate electrode is arranged in the described trench portions and in the face of described tagma,
Wherein said insulated-gate semiconductor device also comprises:
The secondary trenches part is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more, the inside filling insulating material of described secondary trenches part; And
Auxiliary floating region is surrounded by described drift region, and described auxiliary floating region has the semiconductor of first conduction type,
The bottom of wherein said secondary trenches part is arranged in the described auxiliary floating region,
The interval between the lower end of the lower end of described depositing insulating layer and described auxiliary floating region is wider than at interval between the bottom surface in described tagma and the top of described auxiliary floating region,
Between the adjacent floating region is such interval at interval, and under this interval, at the blocking interval of grid voltage, positive field strength distribution curve is connected to each other in the mid portion between described floating region on the direction that connects described floating region, and
The thickness of described depositing insulating layer forms the thickness at electric field peak for be enough to two positions on the thickness direction in described Semiconductor substrate at the blocking interval of grid voltage.
10. according to the insulated-gate semiconductor device of claim 9, also comprise auxiliary in the middle of floating region, the top that is arranged on described auxiliary floating region is top and surrounded by described drift region more, described auxiliary in the middle of floating region have the semiconductor of first conduction type,
The described auxiliary middle floating region of wherein said secondary trenches partial penetration, and
The top of described depositing insulating layer be arranged on described auxiliary in the middle of floating region the top more the top.
11. the insulated-gate semiconductor device according to claim 9 also comprises:
The second secondary trenches part, in the face of described secondary trenches part, wherein said gate electrode inserts between the two, described second secondary trenches partly is set to penetrate described tagma from the upper surface of described Semiconductor substrate, the bottom surface that arrives described tagma is the plane of below more, the inside filling insulating material of described second secondary trenches part; And
The second auxiliary floating region is surrounded by described drift region, and the described second auxiliary floating region has the semiconductor of first conduction type,
The degree of depth of wherein said secondary trenches part is different with the degree of depth of described second secondary trenches part.
12. according to the insulated-gate semiconductor device of claim 9, wherein observe from the top side of described Semiconductor substrate, the structure of described secondary trenches part is a dot pattern.
13. according to the insulated-gate semiconductor device of claim 9,
Wherein in the zone around the element region, be provided with:
The terminals trench portions, its inner filling insulating material of using; And
The terminals floating region is surrounded by described drift region, and described terminals floating region has the semiconductor of first conduction type, and
The bottom of described terminals trench portions is arranged in the described terminals floating region, and
Interval between the adjacent line end floating region is narrower than the interval between the top of the bottom surface in described tagma and described terminals floating region.
14. according to the insulated-gate semiconductor device of claim 9, wherein
Described floating region has the cross sectional shape of sub-circular, and the radius of wherein said floating region is less than half of the thickness of described depositing insulating layer, and the semiconductor of the semiconductor of wherein said first conduction type and described second conduction type is made by silicon.
15. the manufacture method of an insulated-gate semiconductor device, described insulated-gate semiconductor device comprises:
The tagma is arranged on the upper surface side in the Semiconductor substrate, and described tagma has the semiconductor of first conduction type;
The drift region contacts with the bottom surface in described tagma, and described drift region has the semiconductor of second conduction type;
Trench portions is set to penetrate described tagma from the upper surface of described Semiconductor substrate, and the bottom surface that arrives described tagma is the plane of below more;
Floating region is surrounded by described drift region, and described floating region has the semiconductor of first conduction type;
Depositing insulating layer is arranged in described trench portions, and is made of deposition of insulative material; And
Gate electrode is arranged on the described depositing insulating layer and in the face of described tagma,
Wherein
The lower end of described gate electrode the top of described floating region more above,
The interval between the lower end of the lower end of described depositing insulating layer and described floating region is wider than at interval between the bottom surface in described tagma and the top of described floating region, and
The interval between the top of the bottom surface in described tagma and described floating region is wider than at interval between the lower end of described gate electrode and the lower end of described depositing insulating layer,
Between the wherein adjacent floating region is such interval at interval, under this interval, at the blocking interval of grid voltage, the depletion layer that forms from described adjacent floating region in the mid portion between described floating region on the direction that connects described floating region is connected to each other, and
The thickness of described depositing insulating layer forms the thickness at electric field peak for be enough to two positions on the thickness direction in described Semiconductor substrate at the blocking interval of grid voltage,
Described manufacture method may further comprise the steps:
Trench portions forms step, has formed thereon in the described Semiconductor substrate in described drift region and described tagma and has formed described trench portions;
Oxide-film forms step, forms oxide-film on the sidewall of the described trench portions that forms in described trench portions formation step;
The impurity implantation step, described oxide-film form form described oxide-film in the step after, from form the bottom implanted dopant of the trench portions that forms the step in described trench portions;
The insulating material deposition step, after passing through described impurity implantation step implanted dopant, deposition of insulative material in described trench portions;
Floating region forms step, behind the described insulating material of deposition, forms floating region by carrying out heat diffusion treatment in described insulating material deposition step;
The etch-back step behind the described insulating material of deposition, is removed the described insulating material of part in described insulating material deposition step, be removed to the degree of depth below the bottom surface in described tagma; And
The grid material deposition step deposits grid material in the space that is to be formed in the described etch-back step in the described trench portions.
16., further comprising the steps of according to the manufacture method of the insulated-gate semiconductor device of claim 15:
Trench portions boring step is in described impurity implantation step behind the implanted dopant, further downwards to the bottom hole of described trench portions; And
The impurity step of reinjecting re-injects impurity from the bottom of the described trench portions of further being holed described trench portions boring step.
17. according to the manufacture method of the insulated-gate semiconductor device of claim 15, wherein
Form in the step in described trench portions, in the zone around element region and the described element region, form described trench portions, and
Described insulating material deposition step may further comprise the steps:
The filling insulating material step forms the inside of the described trench portions that forms in the step with filling insulating material in described trench portions; And
The deposition materials set-up procedure is used in described filling insulating material step in the described trench portions of filling insulating material by removing, specifically, and the SI semi-insulation material in the described trench portions in described element region, the height of adjustment depositing insulating layer.
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2003349806A JP4538211B2 (en) | 2003-10-08 | 2003-10-08 | Insulated gate semiconductor device and manufacturing method thereof |
| JP349806/2003 | 2003-10-08 | ||
| JP375098/2003 | 2003-11-05 |
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| Publication Number | Publication Date |
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| CN1864270A CN1864270A (en) | 2006-11-15 |
| CN100557819C true CN100557819C (en) | 2009-11-04 |
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| CNB2004800295286A Expired - Fee Related CN100557819C (en) | 2003-10-08 | 2004-10-06 | Insulated-gate semiconductor device and manufacture method thereof |
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| JP (1) | JP4538211B2 (en) |
| CN (1) | CN100557819C (en) |
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Also Published As
| Publication number | Publication date |
|---|---|
| CN1864270A (en) | 2006-11-15 |
| JP2005116822A (en) | 2005-04-28 |
| JP4538211B2 (en) | 2010-09-08 |
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