CN100570819C - A kind of method of two-stage back type etching - Google Patents
A kind of method of two-stage back type etching Download PDFInfo
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- CN100570819C CN100570819C CNB2007101094133A CN200710109413A CN100570819C CN 100570819 C CN100570819 C CN 100570819C CN B2007101094133 A CNB2007101094133 A CN B2007101094133A CN 200710109413 A CN200710109413 A CN 200710109413A CN 100570819 C CN100570819 C CN 100570819C
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Abstract
A kind of method of two-stage back type etching, this method comprises: the substrate that has several layers of hard mask layer is provided earlier.Then, carry on the back the etch substrate back side and side for the first time, to remove the part hard mask layer of substrate back and side.Then, patterning hard mask layer and substrate in regular turn are to form several irrigation canals and ditches in substrate.At last, before carrying out a wet sump cleaning step, carry on the back the etch substrate side for the second time, to remove the acicular texture that is positioned at substrate side.
Description
Technical field
The present invention relates to a kind of manufacture method of semiconductor circuit, particularly a kind of manufacture method with dynamic random access memory of deep channel capacitor device.
Background technology
Dynamic random access memory (Dynamic Random Access Memory, DRAM) be a kind of semiconductor memory, it mainly is made of the transistor AND gate capacitor, utilize the number of stored electric charge in the capacitor to represent the data of (bit), wherein a kind of capacitor arrangement that is usually used in dynamic random access memory is ditching type (trench) capacitor.
So-called ditching type capacitor is meant a kind of capacitor to be arranged on capacitor arrangement in the substrate.In the process of making ditching type capacitor, at first utilize etching plasma that substrate is carried out dry etching, in substrate, etch irrigation canals and ditches, and then capacitor is arranged in the irrigation canals and ditches.In manufacture process, in order to increase the capacitance of ditching type capacitor, that often irrigation canals and ditches are made is darker, and the capacitor with this deep trenches structure is called as the deep channel capacitor device.Yet regular meeting produces the irrigation canals and ditches fault of construction in the process of making the deep channel capacitor device, causes the deep channel capacitor device can't store charge, and then problem such as the semiconductor element quality that exerts an influence.
Therefore, how in the manufacturing process of deep channel capacitor device, the source of removal of defects reduces generation of defects, improves the qualification rate of product, is an important problem in fact.
Summary of the invention
The objective of the invention is to, a kind of method of two-stage back type etching is provided, in order to reduce the incidence of defective in the deep channel capacitor device manufacturing process.
To achieve these goals, the invention provides a kind of method of two-stage back type etching, at first, provide the substrate that has several layers of hard mask layer.Then, carry on the back the etch substrate back side and side for the first time, to remove the part hard mask layer of substrate back and side.Then, patterning hard mask layer and substrate form several irrigation canals and ditches in substrate in regular turn.At last, before carrying out a wet sump cleaning step, carry on the back the etch substrate side for the second time, to remove the acicular texture that is positioned at substrate side.
According to one embodiment of the invention, for fear of effective chip region in etching time infringement substrate center, therefore, carry on the back etch substrate side and the step of carrying on the back the etch substrate side for the second time the above-mentioned first time, all be in the invalid chip region of substrate side, to carry out, form first active region and second active region with the side at substrate respectively, and the scope of second active region is more than or equal to first active region.
According to as can be known above-mentioned, by carrying on the back for the first time etching and the mode of carrying on the back etching for the second time, can reduce the incidence of defective, improve the qualification rate of product.In addition, because before the step of the irrigation canals and ditches that etch the deep channel capacitor device, the part hard mask layer is removed, even therefore improve the processing range (processwindow) of plasma, can not produce the block defective yet, it is darker more complete that the irrigation canals and ditches etching is got, and then increase the storage usefulness of deep channel capacitor device.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Figure 1A-1C is the profile of each operation stage of the deep channel capacitor device of one embodiment of the invention;
Fig. 2 A-2C is the profile of each operation stage of the deep channel capacitor device of one embodiment of the invention;
Fig. 3 is the generalized section of the back of the body etching device of one embodiment of the invention.
Wherein, Reference numeral:
The 100-substrate
The 106-polysilicon layer
The 104-silicon nitride layer
102-pyrex layer
The 108-defective
The 109-defective
The 120-irrigation canals and ditches
The 200-substrate
The 200a-front
The 200b-back side
The effective chip region of 210-
The invalid chip region of 212-
The 214-board
The 216-etching liquid
218-gas
224-first active region
228-second active region
Embodiment
In order to reduce the number of defective, need elder generation in the technology of deep channel capacitor device, find out the source of defective, and then address this problem.Therefore, monitor, and detect the defects count that is produced in each step simultaneously each processing step.
The processing step of monitored deep channel capacitor device roughly comprises: form several layers of hard mask layer earlier on silicon substrate.This hard mask layer significant feature is in order to replace general photoresist, with the patterned silicon substrate.This is because general photoresist can't be kept out the long etching of etching plasma, therefore in order to etch the irrigation canals and ditches of deep channel capacitor device in silicon substrate, must form hard mask layer on the surface of disk earlier, to keep out the etching of plasma.Then, these hard mask layers of patterning in regular turn.At last, utilize the hard mask layer of patterning, in silicon substrate, etch the irrigation canals and ditches of deep channel capacitor device.In above-mentioned technical process, utilize the scattering light value of oblique ultrared sensing silicon substrate simultaneously, with the quantity of monitoring defective generation.
Found that by what detect after the step of patterning number layer hard mask layer, and etch the step of irrigation canals and ditches structure on silicon substrate before, although detect some defectives, the quantity of defective does not have significant change.Yet, etch the step of irrigation canals and ditches at silicon substrate after, the quantity of defective but obviously increases severely, and the place that takes place of defective is all near the side of silicon substrate.
Infer by The above results, may be because in technical process, in order to carry or place silicon substrate, need catch the silicon substrate edge with mechanical arm, thereby cause the hard mask layer that is positioned at silicon substrate edge to be easier to peel off, perhaps suffer scratch, collision, thereby cause the defective of fraction.When carrying out the etching of irrigation canals and ditches, these defectives very easily attract etching plasma, make etching plasma accumulate in the silicon substrate edge, thereby produce a large amount of products in etching process.These products can be deposited in the silicon substrate edge further, hinder the carrying out of etching, thereby the defective of silicon substrate marginal zone is increased suddenly, and this phenomenon is referred to as block defective (chipping effect).
Except above-mentioned block defective, in each processing step of monitoring deep channel capacitor device, also find, after the irrigation canals and ditches etch step of deep channel capacitor device is finished, can form acicular substance at the edge of silicon substrate, this time acicular substance link to each other with silicon substrate.After the wet sump through subsequent technique cleaned (wet bench) step, this acicular substance can rupture and be dispersed in the side and central authorities of silicon substrate, thereby damaged effective chip of silicon substrate.It mainly is the mode of utilizing the ultrasonic waves concussion that aforesaid wet sump cleans, and removes the silicon substrate surface because of impurity that etching technics produced.
The reason that this acicular substance produces; may be because the area of silicon substrate is excessive and its edge presents radian; thereby when forming hard mask layer; the formed hard mask layer of silicon substrate edge is thin or imperfect; cause at the etch silicon substrate when forming the step of irrigation canals and ditches; can't effectively protect the edge of silicon substrate, and then on exposed silicon substrate, produce acicular texture.These acicular textures can rupture in the wet sump cleaning step of subsequent technique, are dispersed in the edge and central authorities of silicon substrate, thereby cause defective, and this phenomenon is called as needle shape flaw (needle defect).
Hereinafter, with proposing a kind of method of preventing block defective and needle shape flaw to produce, to improve the qualification rate of product.
Figure 1A-1C is the profile of each operation stage of a kind of deep channel capacitor device of one embodiment of the invention.In the present embodiment, focus on how preventing the defective that in the step of etch substrate, produced.Therefore in the following embodiments, begin to narrate, will repeat no more as for the pre-process of other deep channel capacitor device by the step that forms several layers of hard mask layer.
At first, please refer to Figure 1A, on substrate 100, form in regular turn silicon nitride layer 102, pyrex layer (Borosilicate Glass, BSG) 104 with the hard mask layer of polysilicon layer 106 as the etching deep trenches.The hard mask layer Material Selection must be taken into account the formation thickness of hard mask layer and the selectivity of etching, in order to avoid produce because hard mask layer is too thick etching not exclusively or because of the too thin problem that can't finish the etching of deep trenches.In the present embodiment, it is formed that polysilicon layer 106 and silicon nitride layer 102 are to use boiler tube to carry out chemical vapor deposition method, and therefore polysilicon layer 106 and silicon nitride layer 102 are arranged at the back side of substrate 100.Pyrex layer 104 is to use ion growth form chemical vapor deposition to form, and has therefore only covered the side edge of substrate 100.Yet, the actual state of the material of above-mentioned hard mask layer and the material category of use and covered substrate thereof, still can owing to actual demand and employed formation method and different, this is known by the personnel that are familiar with semiconductor technology, gives unnecessary details various changing conditions no longer one by one.
In addition, in Figure 1A, the defective 108 in the polysilicon layer 106 is for the purpose of illustration only, and causes the source and the position of block defective in order to explanation.Defective 108 also may occur in pyrex layer 104 and silicon nitride layer 102 parts.
Then, shown in Figure 1B, carry out carrying on the back the first time etching, to remove the part polysilicon layer 106 of substrate 100 back sides and side.By removing the part polysilicon layer 106 that is positioned at substrate 100 sides, can relatedly remove the defective 108 in the polysilicon layer 106.
At last, shown in Fig. 1 C, patterned polysilicon layer 106, pyrex layer 104 and silicon nitride layer 102 in regular turn.Because defective 108 has removed in above-mentioned steps, even therefore carry out follow-up technology, for example, on substrate 100, further etch the irrigation canals and ditches of deep channel capacitor device, can not cause the block defective yet.
In order to confirm to carry on the back the incidence that the etching mode can reduce the block defective really the above-mentioned first time, respectively two have been carried out and do not carried out carrying on the back the etching processing substrate the above-mentioned first time, after etching irrigation canals and ditches, test.Test result finds that without carrying on the back the substrate of etching processing for the first time, the number of defects height of eye of substrate side reaches 30,000, has passed through the substrate of carrying on the back etching processing for the first time, and the defective number of its side only has 1,000.Hence one can see that, by carrying on the back etching processing the above-mentioned first time, can prevent the generation of substrate side block defective significantly, makes the defective number reduce about thirtyfold, for the raising of product percent of pass very big effect arranged.
By as can be known aforementioned, the generation of needle shape flaw mainly is relevant with the incomplete acicular texture that causes of silicon layer etching at substrate edges place, and it mainly is to occur in after the step of etch substrate, before the step that wet sump cleans.Therefore, in the present embodiment, be described in the technology after the etch substrate step is finished emphatically, with the generation of prevention needle shape flaw.As for the pre-process before the etch substrate step and carry on the back for the first time step such as etching, then as previously mentioned.
Fig. 2 A-2C is one embodiment of the invention, the profile of each operation stage of deep channel capacitor device.According to above-mentioned, in Fig. 2 A, through carrying on the back etching processing for the first time, therefore, the part polysilicon layer 106 of the side of substrate 100 has been removed substrate 100.Then, patterned polysilicon layer 106, pyrex layer 104 and silicon nitride layer 102.
In Fig. 2 B, be mask with silicon nitride layer 102 then with the polysilicon layer behind the patterning 106, pyrex layer 104, further utilize plasma in substrate 100, to etch a plurality of irrigation canals and ditches 120, in order to the deep channel capacitor device to be set.After the formation of finishing irrigation canals and ditches 120, then patterned polysilicon layer 106, pyrex layer 104 are removed.Be noted that in Fig. 2 B, the defective 109 of substrate 100 sides is only used as example, in order to representative when the etch substrate, the source and the position of needle-like block defective.
Then, in Fig. 2 C, utilize etching liquid that substrate 100 sides are carried out carrying on the back the second time etching, to remove the acicular texture that is positioned at substrate 100 sides.In this step, the acicular texture of substrate 100 sides can be removed, at this moment, even carry out follow-up technology again, for example the step of wet sump cleaning can not cause the fracture of acicular texture yet or cause producing needle shape flaw.
In order to confirm to carry on the back the incidence that the etching mode can reduce needle shape flaw really the above-mentioned second time, therefore two have been carried out and have not been carried out carry on the back for the second time the substrate of etching processing respectively, after through the wet sump cleaning, test.Test result finds that without carrying on the back the substrate of etching processing for the second time, the defective number of substrate side is about 1,000, has passed through the substrate of carrying on the back etching processing for the second time, and the defective number of its side only has 100.Hence one can see that, by carrying on the back the mode of etching the above-mentioned second time, can prevent the needle-like generation of defects significantly, makes the defective number reduce about ten times, for the raising of product percent of pass very big help arranged.
In order to do more detailed explanation with carrying on the back for the second time etching to carrying on the back etching the above-mentioned first time, please refer to Fig. 3, this is the generalized section of the back of the body etching device of one embodiment of the invention.In Fig. 3, the mode of the wet etching of back of the body etching utilization is carried out.As shown in the figure, substrate 200 with back side 200b up, positive 200a mode down places on the board 214, substrate 200 mainly comprises effective chip region 210 of central authorities and invalid chip region 212 two parts of side.In order to carry on the back etching, etching liquid 216 is by the pipe flow will of the board 214 tops back side 200b to substrate 200, and then covers the back side 200b of whole base plate 200.Then, etching liquid 216 can be along with the side of substrate 200, flows to positive 200a by the back side 200b of substrate 200, to carry out etching.
Etching scope for fear of etching liquid 216 surpasses invalid chip region 212, damage effective chip region 210 of substrate 200 central authorities, therefore, below board 214, be connected with gas 218, this gas 218 is blowed to the invalid chip region 212 of substrate 200 sides by effective chip region 210 of the positive 200a central authorities of substrate 200, to drive the flow direction of etching liquid 216, avoid etching liquid 216 to damage effective chip region 210.Like this, no matter be to carry on the back etching for the first time or carry on the back etching for the second time, the scope of etching all only limits to the invalid chip region 212 of substrate 200 sides, simultaneously, in order to remove the acicular texture of substrate 200 sides fully, carry on the back for the second time the sphere of action of etching, i.e. second active region 228 can be more than or equal to carrying on the back for the first time formed first active region 224 of corrasion scope.
The selection of above-mentioned etching liquid 216 is different according to material.Is example with above-mentioned silicon nitride layer 102 as hard mask layer, pyrex layer 104 with polysilicon layer 106, and its etching liquid 216 can be selected hydrofluoric acid (or HF/NH respectively
3The aqueous solution), hot phosphoric acid and HF/HNO
3The aqueous solution.
The above-mentioned wet type back of the body etching method dry type back of the body etching method of also can arranging in pairs or groups is carried out.Is example with the above-mentioned silicon nitride layer 102 as hard mask layer, pyrex layer 104 with polysilicon layer 106, can use wet type back of the body etching method to remove the polysilicon layer 106 of substrate 100 back sides and side earlier, re-use dry type back of the body etching method and remove the silicon nitride layer 102 and pyrex layer 104 that is positioned at substrate 100 sides.
The material of the hard mask layer among the present invention can be selected from a group that is made up of silica, polysilicon, silicon nitride and above-mentioned combination in any.
By the foregoing description as can be known, before and after the step of etch silicon substrate, mode by this back of the body etching, not only can prevent the generation of block defective and needle shape flaw, the regional extent of etching can also be limited in the invalid chip region, not only can not have any impact, can also help the raising of product percent of pass effective chip region.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art work as can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (7)
1, a kind of method of two-stage back type etching is characterized in that, this method comprises at least:
One substrate is provided, and this substrate has a plurality of hard mask layers;
Carry on the back for the first time the back side and the side of this substrate of etching, to remove this hard mask layer that is positioned at this substrate back and side;
This hard mask layer of patterning and this substrate in regular turn are to form a plurality of irrigation canals and ditches in this substrate;
Before carrying out a wet sump cleaning step, carry on the back this substrate side of etching for the second time, to remove a plurality of acicular textures that are positioned at this substrate side.
2, the method for claim 1 is characterized in that, the material of this hard mask layer is selected from a group that is made up of silica, polysilicon, silicon nitride and above-mentioned combination in any.
3, the method for claim 1 is characterized in that, carries on the back the step of this substrate side of etching for the first time and carries out with wet etching or dry etching respectively with the step of carrying on the back this substrate side of etching for the second time.
4, method as claimed in claim 3 is characterized in that, in this dry etching step, carries out etching with a plasma.
5, the method for claim 1 is characterized in that, when the material of this hard mask layer of part was polysilicon, the step of carrying on the back this substrate side of etching for the first time was a wet etch step.
6, the method for claim 1 is characterized in that, when the material of this hard mask layer of part was silica or silicon nitride, this step of carrying on the back this substrate side of etching for the first time was a dry etching step.
7, the method for claim 1, it is characterized in that, the step of carrying on the back this substrate side of etching for the first time, with the step of carrying on the back this substrate side of etching for the second time, all in an invalid chip region of this substrate side, carry out, forming one first active region and one second active region respectively, and the scope of this second active region is more than or equal to the scope of this first active region.
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| Application Number | Priority Date | Filing Date | Title |
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| CNB2007101094133A CN100570819C (en) | 2007-06-18 | 2007-06-18 | A kind of method of two-stage back type etching |
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|---|---|---|---|
| CNB2007101094133A CN100570819C (en) | 2007-06-18 | 2007-06-18 | A kind of method of two-stage back type etching |
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| CN100570819C true CN100570819C (en) | 2009-12-16 |
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