CN100570860C - 双应力记忆技术方法和相关半导体器件 - Google Patents

双应力记忆技术方法和相关半导体器件 Download PDF

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CN100570860C
CN100570860C CNB2006101463928A CN200610146392A CN100570860C CN 100570860 C CN100570860 C CN 100570860C CN B2006101463928 A CNB2006101463928 A CN B2006101463928A CN 200610146392 A CN200610146392 A CN 200610146392A CN 100570860 C CN100570860 C CN 100570860C
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pfet
semiconductor device
stressor layers
nfet
silicon nitride
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CN1971882A (zh
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方隼飞
骆志炯
郑阳伟
尼沃·罗夫多
金田中
吴洪业
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Samsung Electronics Co Ltd
GlobalFoundries Singapore Pte Ltd
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Chartered Semiconductor Manufacturing Pte Ltd
International Business Machines Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823807—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the channel structures, e.g. channel implants, halo or pocket implants, or channel materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof  ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7842—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate
    • H01L29/7843—Field effect transistors with field effect produced by an insulated gate means for exerting mechanical stress on the crystal lattice of the channel region, e.g. using a flexible substrate the means being an applied insulating layer

Abstract

公开了一种用于在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法以及相关结构。本方法的一个实施例包括：在nFET上方形成张应力层且在pFET上方形成压应力层，进行退火以在半导体器件中记忆应力并去除应力层。压应力层可以包括使用高密度等离子体(HDP)淀积方法淀积的高应力氮化硅。退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保在pFET中保持压应力记忆。

Description

双应力记忆技术方法和相关半导体器件
技术领域
本发明一般地涉及应力记忆技术，且更特别地涉及提供双应力记忆技术的方法和相关结构。
背景技术
已知将应力施加于场效应晶体管(FET)可以改进它们的性能。当在纵向方向(即，在电流方向)上施加应力时，张应力可以提高电子迁移率(或n沟道FET(nFET)驱动电流)，而已知压应力可以提高空穴迁移率(或p沟道FET(pFET)驱动电流)。
一种提供这种应力的方式被称为应力记忆技术(SMT：stressmemorization technique)，其包括在沟道区上方施加固有应变的材料(例如，氮化硅)并进行退火以使应力被记忆在例如栅极多晶硅或扩散区中。然后去除应变材料。然而，应力得以保留并改进电子或空穴的迁移率，这提高了整体的性能。典型地将该退火提供为掺杂剂激活退火的一部分。
SMT的一个问题是其只能应用于n型场效应晶体管(nFET)。具体而言，尽管可以在pFET上方形成压应变氮化硅层来带来压应力，但通过随后必经的掺杂剂激活退火去除了大部分的应力。即，大多数压应力没有被记忆在pFET中。
考虑到上述内容，需要在本技术中提供一种可以用于nFET和pFET的SMT。
发明内容
公开了一种用于在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法以及相关结构。本方法的一个实施例包括：在nFET上方形成张应力层且在pFET上方形成压应力层，进行退火以在半导体器件中记忆应力，以及去除应力层。压应力层可以包括使用高密度等离子体(HDP)淀积方法淀积的高应力氮化硅。退火步骤可以包括使用约400-1200℃的温度。高应力压缩氮化硅和/或退火温度确保在pFET中保持压应力记忆。
本发明的第一方面提供了一种在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法，该方法包括以下步骤：在半导体器件上方形成第一应力层；在第一应力层上方形成刻蚀停止层；去除在nFET和pFET中第一个的上方的第一应力层和刻蚀停止层；在半导体器件上方形成第二应力层，其中在pFET上方的应力层包括压应力氮化硅；进行退火以将应力记忆在半导体器件中；以及去除第一应力层和第二应力层以及刻蚀停止层。
本发明的第二方面提供了一种针对包括nFET和pFET的半导体器件提供双应力记忆技术的方法，所述方法包括以下步骤：在nFET上方形成张应力层且在pFET上方形成压应力层，其中压应力层包括在随后退火期间至少保持部分压应力的高应力膜；进行退火以在半导体器件中记忆应力；以及去除压应力层和张应力层。
本发明的第三方面提供了一种半导体器件，其包括：具有记忆在其一部分中的张应力的nFET；以及具有记忆在其一部分中的压应力的pFET。
设计了本发明的示例方面，来解决由本领域技术人员发现的这里所述的问题和没有讨论的其它问题。
附图说明
从以下结合描述本发明各个实施例的附图对本发明各个方面所做出的详细描述，可以更容易地理解本发明的这些和其它特征，其中：
图1示出用于根据本发明方法的一个实施例的初步结构。
图2至图7示出根据本发明一个实施例的方法。
应注意，本发明的附图并非是按比例绘出。附图旨在仅描述本发明的典型方面，且因此不应被视作是限制本发明的范围。在附图中，相同的标号表示附图之间相同的元件。
具体实施方式
从附图开始，图1示出用于向半导体器件100提供双应力记忆技术(SMT)的方法的一个实施例的初步结构。该初步结构包括衬底102，该衬底102具有形成在其上的n型场效应晶体管(nFET)104和p型场效应晶体管(pFET)106。如图所示，半导体器件100已经完成初始处理，诸如常规浅沟槽隔离(STI)110的形成、阱注入、栅极电介质112的形成、栅极导体114的形成以及用于扩散116的扩展/晕圈(halo)/源极/漏极的注入。
参考图2，在该方法的一个实施例中，第一步骤包括在nFET 104上方形成张应力层120和在pFET 106上方形成压应力层122。张应力层120和压应力层122都可以包括固有应变的氮化硅(Si3N4)。然而，在一个优选实施例中，压应力层122包括高密度等离子体(HDP)氮化硅(Si3N4)，即，使用高密度等离子体淀积工艺形成的氮化硅。在一个优选实施例中，压应力层形成步骤包括使用以下条件来执行氮化硅的HDP淀积：约50mTorr的压力、约200标准立方厘米(sccm)的氩气(Ar)、约100sccm的硅烷(SiH4)、约300sccm的氮气(N2)、约0-1500W的射频(RF)偏置功率以及约2000W-4500W的RF源功率。因而，压应力层122包括高应力氮化硅，因为所述高应力氮化硅允许压应力的保持(完全或部分)，使得在以下描述的后续退火步骤期间应力被记忆在pFET 106的一部分中，所以所述高应力氮化硅能够提供双SMT。
可以用许多方式来提供该形成步骤，这里将只描述它的两个说明性实施例。图3至图6示出了这两个说明性实施例。如图3所示，第一可选的初步步骤包括形成例如二氧化硅(SiO2)的刻蚀停止层118(在图3中只用虚线示出)。接着，如图3中所示，第一子步骤包括在半导体器件100上方形成第一应力层130。如以下将要描述的，第一应力层130可以是张应力层120(图2)或压应力层122(图2)。然而，如图3中所示，第一应力层130包括固有张应变的氮化硅。还如图3中所示，第二子步骤包括在第一应力层130上方形成刻蚀停止层132。刻蚀停止层132可以包括诸如二氧化硅(SiO2)的任何现在已知或以后要研制的刻蚀停止材料。接着，还如图3中所示，去除在nFET 104和pFET 106中第一个(图中所示的pFET 106)的上方的第一应力层130和刻蚀停止层132，以暴露FET中的一个。刻蚀138可以包括针对所使用的材料来使用构图掩膜136(图中以虚线示出)以及任何常规的干法刻蚀。图4示出包括被暴露的pFET 106的生成结构。
接着，如图5中所示，在半导体衬底100上方形成第二应力层140。如图所示，第二应力层140形成在pFET 106上方，且因此包括上述高密度、压应力的氮化硅。在一个可替选实施例中，下一步骤可以包括在以下描述的退火步骤之前去除在nFET 104上方的第二应力层140。去除步骤可以包括针对所使用的材料来使用构图掩膜146(图中以虚线示出)以及任何常规的干法刻蚀144。图6示出了生成的结构。在没有去除第二应力层140的情况下，应认识到可能出现由第一应力层130所带来的应力的一些退化，但这种退化是最小限度的。
在可替选实施例中，可以改变上述步骤。即，形成步骤可以包括：在半导体器件100上方形成压应力层122，在压应力层上方形成刻蚀停止层132，去除在nFET 104上方的压应力层122和刻蚀停止层132，以及在半导体器件100上方形成张应力层120。如上述实施例中那样，可以在以下描述的退火步骤之前将张应力层120可选地去除。在没有去除张应力层120的情况下，应认识到可能出现由压应力层122所带来的应力的一些退化，但这种退化是最小限度的。
图6还示出了根据本方法的一个实施例的第二步骤，其包括进行退火150以在半导体器件100中记忆应力。退火150优选地包括使用不小于约400℃且不大于约1200℃的温度。对退火温度进行优化，使得器件100将能够记忆来自应力层120、122的应力，而不丢失在pFET106的部分上的压应力，这将在其上引起中性应力或张应力。例如，一种常规的等离子体增强型化学汽相淀积(PECVD)的压缩氮化硅，其形成有约-1.8GPa/cm2的应力，在退火后下降到约0.04GPa/cm2的应力，即张应力。相比之下，在一个实施例中，根据本发明的HDP压应力氮化硅形成有约-3.0GPa/cm2的应力，这产生不小于-100MPa/cm2的应力，因而保持了压应力。在一个实施例中，压应力可以在约-1GPa/cm2的范围中。
图7示出包括去除应力层120、122和刻蚀停止层132的第三步骤。这个去除步骤148可以包括湿法或干法刻蚀、或它们的组合；例如，使用湿法或干法刻蚀来去除刻蚀停止层132，然后使用热磷酸的湿法剥离来去除氮化硅应力层。图7还示出了根据本发明的半导体器件200，其包括nFET 204，该nFET 204具有记忆到其一部分中——例如栅极导体214和/或扩散区216——的张应力260，以及pFET 206，该pFET 206具有记忆到其一部分中——例如栅极导体220和/或扩散区222——的压应力262。
为了说明和描述的目的，给出了本发明各个方面的以上描述。其并不旨在穷尽列举或将本发明限制为所公开的精确形式，且明显地，可以进行多种修改和变化。本发明旨在将对于本领域技术人员是显而易见的这些修改和变化包括在由所附权利要求限定的本发明的范围内。

Claims (16)

1.一种用于在包括nFET和pFET的半导体器件中提供双应力记忆技术的方法，所述方法包括以下步骤：
在所述半导体器件上方形成第一应力层；
在所述第一应力层上方形成刻蚀停止层；
去除在所述nFET和所述pFET中第一个的上方的所述第一应力层和所述刻蚀停止层；
在所述半导体器件上方形成第二应力层，其中在所述pFET上方的应力层包括压应力氮化硅，所述压应力氮化硅包括高密度等离子体氮化硅；
进行退火以将应力记忆在所述半导体器件中，其中所述退火步骤包括使用不低于400℃且不高于1200℃的温度；以及
去除所述第一应力层和所述第二应力层及所述刻蚀停止层。
2.如权利要求1的方法，进一步包括在所述第一应力层的形成步骤之前，淀积附加的刻蚀停止层的步骤。
3.如权利要求1的方法，其中所述压应力氮化硅在所述退火步骤后具有不小于-100Mpa/cm2的应力。
4.如权利要求1的方法，进一步包括在所述退火步骤之前，去除在所述nFET和所述pFET中另一个的上方的所述第二应力层的步骤。
5.如权利要求1的方法，其中所述nFET和所述pFET中的所述第一个包括所述nFET，且所述第一应力层包括固有张应变的材料，所述第二应力层包括所述压应力氮化硅。
6.如权利要求1的方法，其中每个应力层包括氮化硅。
7.如权利要求1的方法，其中所述刻蚀停止层包括二氧化硅。
8.一种针对包括nFET和pFET的半导体器件提供双应力记忆技术的方法，所述方法包括以下步骤：
在所述nFET上方形成张应力层且在所述pFET上方形成压应力层，其中所述压应力层包括在随后退火期间至少保持部分压应力的高密度等离子体氮化硅；
进行退火以在所述半导体器件中记忆应力，其中所述退火步骤包括使用不低于400℃且不高于1200℃的温度；以及
去除所述压应力层和所述张应力层。
9.如权利要求8的方法，其中所述压应力层形成步骤包括使用以下条件来执行氮化硅的高密度等离子体淀积：50mTorr的压力、200标准立方厘米的氩气、100sccm的硅烷、300sccm的氮气、0-1500W的射频偏置功率以及2000W-4500W的RF源功率。
10.如权利要求8的方法，其中每个应力层包括氮化硅。
11.如权利要求8的方法，其中所述形成步骤包括：
在所述半导体器件上方形成所述张应力层；
在所述张应力层上方形成刻蚀停止层；
去除在所述pFET上方的所述张应力层和所述刻蚀停止层；以及
在所述半导体器件上方形成所述压应力层。
12.如权利要求11的方法，进一步包括在所述退火步骤之前，去除在所述nFET上方的所述压应力层的步骤。
13.如权利要求11的方法，其中所述刻蚀停止层包括二氧化硅。
14.如权利要求8的方法，其中所述形成步骤包括：
在所述半导体器件上方形成所述压应力层；
在所述压应力层上方形成刻蚀停止层；
去除在所述nFET上方的所述压应力层和所述刻蚀停止层；
在所述半导体器件上方形成所述张应力层。
15.如权利要求14的方法，进一步包括在所述退火步骤之前，去除在所述pFET上方的所述张应力层的步骤。
16.一种半导体器件，包括：
nFET，具有记忆到其一部分中的张应力；以及
pFET，具有记忆到其一部分中的压应力，
其中所述pFET具有通过压缩的高密度等离子体氮化硅层而被记忆的压应力。
CNB2006101463928A 2005-11-10 2006-11-09 双应力记忆技术方法和相关半导体器件 Expired - Fee Related CN100570860C (zh)

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Families Citing this family (49)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2005286341A (ja) * 2004-03-30 2005-10-13 Samsung Electronics Co Ltd 低ノイズ及び高性能のｌｓｉ素子、レイアウト及びその製造方法
US7785950B2 (en) 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure
US7332447B2 (en) * 2005-11-24 2008-02-19 United Microelectronics Corp. Method of forming a contact
US7678630B2 (en) * 2006-02-15 2010-03-16 Infineon Technologies Ag Strained semiconductor device and method of making same
JP4899085B2 (ja) 2006-03-03 2012-03-21 富士通セミコンダクター株式会社 半導体装置およびその製造方法
US7514370B2 (en) * 2006-05-19 2009-04-07 International Business Machines Corporation Compressive nitride film and method of manufacturing thereof
WO2007139140A1 (ja) 2006-05-31 2007-12-06 Tokyo Electron Limited プラズマｃｖｄ方法、窒化珪素膜の形成方法および半導体装置の製造方法
JP5017958B2 (ja) * 2006-08-08 2012-09-05 富士通セミコンダクター株式会社 半導体装置の製造方法
US7632729B2 (en) * 2006-09-27 2009-12-15 Taiwan Semiconductor Manufacturing Co., Ltd. Method for semiconductor device performance enhancement
US7795644B2 (en) * 2007-01-04 2010-09-14 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuits with stress memory effect and fabrication methods thereof
US7759207B2 (en) * 2007-03-21 2010-07-20 Chartered Semiconductor Manufacturing Ltd. Integrated circuit system employing stress memorization transfer
US20080237734A1 (en) * 2007-03-29 2008-10-02 United Microelectronics Corp. Complementary metal-oxide-semiconductor transistor and method of fabricating the same
US7611939B2 (en) * 2007-05-07 2009-11-03 Texas Instruments Incorporated Semiconductor device manufactured using a laminated stress layer
US7834399B2 (en) 2007-06-05 2010-11-16 International Business Machines Corporation Dual stress memorization technique for CMOS application
US7741168B2 (en) * 2007-07-25 2010-06-22 Sematech, Inc. Systems and methods for fabricating nanometric-scale semiconductor devices with dual-stress layers using double-stress oxide/nitride stacks
US20090050972A1 (en) * 2007-08-20 2009-02-26 Richard Lindsay Strained Semiconductor Device and Method of Making Same
JP5117883B2 (ja) * 2008-02-25 2013-01-16 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8871587B2 (en) 2008-07-21 2014-10-28 Texas Instruments Incorporated Complementary stress memorization technique layer method
US7767534B2 (en) * 2008-09-29 2010-08-03 Advanced Micro Devices, Inc. Methods for fabricating MOS devices having highly stressed channels
US8969969B2 (en) 2009-03-20 2015-03-03 International Business Machines Corporation High threshold voltage NMOS transistors for low power IC technology
US8298876B2 (en) 2009-03-27 2012-10-30 International Business Machines Corporation Methods for normalizing strain in semiconductor devices and strain normalized semiconductor devices
US8039349B2 (en) * 2009-07-30 2011-10-18 Globalfoundries Inc. Methods for fabricating non-planar semiconductor devices having stress memory
CN102054769B (zh) * 2009-10-29 2013-03-27 中芯国际集成电路制造(上海)有限公司 互补型金属氧化物半导体结构的形成方法
CN102194749B (zh) * 2010-03-11 2013-06-12 中芯国际集成电路制造(上海)有限公司 制作互补型金属氧化物半导体器件的方法
KR20120023968A (ko) 2010-09-03 2012-03-14 삼성전자주식회사 트랜지스터 형성 방법, 상보형 트랜지스터 형성 방법 및 이를 이용한 반도체 소자 제조 방법
CN102446761B (zh) * 2010-09-30 2015-07-15 中国科学院微电子研究所 半导体结构的制造方法
US9202913B2 (en) 2010-09-30 2015-12-01 Institute of Microelectronics, Chinese Academy of Sciences Method for manufacturing semiconductor structure
US8535999B2 (en) 2010-10-12 2013-09-17 International Business Machines Corporation Stress memorization process improvement for improved technology performance
CN102456626B (zh) * 2010-10-20 2013-12-18 中芯国际集成电路制造(上海)有限公司 基于双应力薄膜技术的半导体器件的制作方法
CN102468160A (zh) * 2010-11-03 2012-05-23 中芯国际集成电路制造(上海)有限公司 利用应力记忆技术提高nfet窄沟道效应的方法
US8216928B1 (en) 2011-01-26 2012-07-10 GlobalFoundries, Inc. Methods for fabricating semiconductor devices having local contacts
CN102420119B (zh) * 2011-04-29 2013-06-26 上海华力微电子有限公司 一种增强应力记忆效应的栅多晶硅刻蚀方法
KR20120136672A (ko) 2011-06-09 2012-12-20 삼성전자주식회사 반도체 소자의 제조 방법
CN102456565A (zh) * 2011-08-29 2012-05-16 上海华力微电子有限公司 一种预防在双应力氮化硅工艺中光阻失效的方法
CN102446722A (zh) * 2011-08-29 2012-05-09 上海华力微电子有限公司 一种预防在双应力氮化硅工艺中光阻失效的方法
CN103094108B (zh) * 2011-10-29 2015-12-02 中芯国际集成电路制造(上海)有限公司 半导体器件的制作方法
CN103183307B (zh) * 2011-12-28 2016-04-20 中国科学院微电子研究所 张应力LPCVD SiO2膜的制造方法
CN102709178B (zh) * 2012-05-22 2015-08-19 上海华力微电子有限公司 一种形成双应力层氮化硅薄膜的方法
CN103474350A (zh) * 2012-06-06 2013-12-25 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
CN103839800A (zh) * 2012-11-20 2014-06-04 中国科学院微电子研究所 氮化硅制造方法
CN103107236B (zh) * 2012-12-06 2016-05-04 杭州赛昂电力有限公司 异质结太阳能电池及其制作方法
CN103107239B (zh) * 2012-12-06 2016-08-31 杭州赛昂电力有限公司 异质结太阳能电池及其制作方法
CN103107234B (zh) * 2012-12-06 2016-03-23 杭州赛昂电力有限公司 异质结太阳能电池及其制作方法
CN103700631A (zh) * 2013-11-29 2014-04-02 上海华力微电子有限公司 无结mos fet器件的制备方法
US9368627B2 (en) 2014-09-11 2016-06-14 Taiwan Semiconductor Manufacturing Company Ltd. Semiconductor structure and manufacturing method thereof
CN104733391A (zh) * 2015-03-31 2015-06-24 上海华力微电子有限公司 半导体器件的制造方法
KR102426960B1 (ko) * 2015-10-15 2022-08-01 주식회사 테스 플라즈마를 이용하여 실리콘 산화막을 형성하는 방법
US9941211B1 (en) 2017-03-24 2018-04-10 International Business Machines Corporation Reducing metallic interconnect resistivity through application of mechanical strain
KR102414957B1 (ko) 2018-06-15 2022-06-29 삼성전자주식회사 반도체 장치의 제조 방법

Family Cites Families (90)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3602841A (en) * 1970-06-18 1971-08-31 Ibm High frequency bulk semiconductor amplifiers and oscillators
US4853076A (en) * 1983-12-29 1989-08-01 Massachusetts Institute Of Technology Semiconductor thin films
US4665415A (en) * 1985-04-24 1987-05-12 International Business Machines Corporation Semiconductor device with hole conduction via strained lattice
EP0219641B1 (de) * 1985-09-13 1991-01-09 Siemens Aktiengesellschaft Integrierte Bipolar- und komplementäre MOS-Transistoren auf einem gemeinsamen Substrat enthaltende Schaltung und Verfahren zu ihrer Herstellung
JPS6476755A (en) 1987-09-18 1989-03-22 Hitachi Ltd Semiconductor device
US4958213A (en) * 1987-12-07 1990-09-18 Texas Instruments Incorporated Method for forming a transistor base region under thick oxide
US5354695A (en) * 1992-04-08 1994-10-11 Leedy Glenn J Membrane dielectric isolation IC fabrication
US5459346A (en) * 1988-06-28 1995-10-17 Ricoh Co., Ltd. Semiconductor substrate with electrical contact in groove
US5006913A (en) * 1988-11-05 1991-04-09 Mitsubishi Denki Kabushiki Kaisha Stacked type semiconductor device
US5108843A (en) * 1988-11-30 1992-04-28 Ricoh Company, Ltd. Thin film semiconductor and process for producing the same
US4952524A (en) * 1989-05-05 1990-08-28 At&T Bell Laboratories Semiconductor device manufacture including trench formation
US5310446A (en) * 1990-01-10 1994-05-10 Ricoh Company, Ltd. Method for producing semiconductor film
US5060030A (en) * 1990-07-18 1991-10-22 Raytheon Company Pseudomorphic HEMT having strained compensation layer
US5081513A (en) * 1991-02-28 1992-01-14 Xerox Corporation Electronic device with recovery layer proximate to active layer
US5371399A (en) * 1991-06-14 1994-12-06 International Business Machines Corporation Compound semiconductor having metallic inclusions and devices fabricated therefrom
US5134085A (en) * 1991-11-21 1992-07-28 Micron Technology, Inc. Reduced-mask, split-polysilicon CMOS process, incorporating stacked-capacitor cells, for fabricating multi-megabit dynamic random access memories
US5391510A (en) * 1992-02-28 1995-02-21 International Business Machines Corporation Formation of self-aligned metal gate FETs using a benignant removable gate material during high temperature steps
US6008126A (en) * 1992-04-08 1999-12-28 Elm Technology Corporation Membrane dielectric isolation IC fabrication
US5561302A (en) * 1994-09-26 1996-10-01 Motorola, Inc. Enhanced mobility MOSFET device and method
US5670798A (en) * 1995-03-29 1997-09-23 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact non-nitride buffer layer and methods of fabricating same
US5679965A (en) * 1995-03-29 1997-10-21 North Carolina State University Integrated heterostructures of Group III-V nitride semiconductor materials including epitaxial ohmic contact, non-nitride buffer layer and methods of fabricating same
US5557122A (en) * 1995-05-12 1996-09-17 Alliance Semiconductors Corporation Semiconductor electrode having improved grain structure and oxide growth properties
KR100213196B1 (ko) * 1996-03-15 1999-08-02 윤종용 트렌치 소자분리
US6403975B1 (en) * 1996-04-09 2002-06-11 Max-Planck Gesellschaft Zur Forderung Der Wissenschafteneev Semiconductor components, in particular photodetectors, light emitting diodes, optical modulators and waveguides with multilayer structures grown on silicon substrates
US5880040A (en) * 1996-04-15 1999-03-09 Macronix International Co., Ltd. Gate dielectric based on oxynitride grown in N2 O and annealed in NO
US5861651A (en) * 1997-02-28 1999-01-19 Lucent Technologies Inc. Field effect devices and capacitors with improved thin film dielectrics and method for making same
US5940736A (en) * 1997-03-11 1999-08-17 Lucent Technologies Inc. Method for forming a high quality ultrathin gate oxide layer
US6309975B1 (en) * 1997-03-14 2001-10-30 Micron Technology, Inc. Methods of making implanted structures
US6025280A (en) * 1997-04-28 2000-02-15 Lucent Technologies Inc. Use of SiD4 for deposition of ultra thin and controllable oxides
US5960297A (en) * 1997-07-02 1999-09-28 Kabushiki Kaisha Toshiba Shallow trench isolation structure and method of forming the same
JP3139426B2 (ja) * 1997-10-15 2001-02-26 日本電気株式会社 半導体装置
US6066545A (en) * 1997-12-09 2000-05-23 Texas Instruments Incorporated Birdsbeak encroachment using combination of wet and dry etch for isolation nitride
US6274421B1 (en) * 1998-01-09 2001-08-14 Sharp Laboratories Of America, Inc. Method of making metal gate sub-micron MOS transistor
KR100275908B1 (ko) * 1998-03-02 2000-12-15 윤종용 집적 회로에 트렌치 아이솔레이션을 형성하는방법
US6361885B1 (en) * 1998-04-10 2002-03-26 Organic Display Technology Organic electroluminescent materials and device made from such materials
US6165383A (en) * 1998-04-10 2000-12-26 Organic Display Technology Useful precursors for organic electroluminescent materials and devices made from such materials
US5989978A (en) * 1998-07-16 1999-11-23 Chartered Semiconductor Manufacturing, Ltd. Shallow trench isolation of MOSFETS with reduced corner parasitic currents
JP4592837B2 (ja) * 1998-07-31 2010-12-08 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6319794B1 (en) * 1998-10-14 2001-11-20 International Business Machines Corporation Structure and method for producing low leakage isolation devices
US6235598B1 (en) * 1998-11-13 2001-05-22 Intel Corporation Method of using thick first spacers to improve salicide resistance on polysilicon gates
US6117722A (en) * 1999-02-18 2000-09-12 Taiwan Semiconductor Manufacturing Company SRAM layout for relaxing mechanical stress in shallow trench isolation technology and method of manufacture thereof
US6255169B1 (en) * 1999-02-22 2001-07-03 Advanced Micro Devices, Inc. Process for fabricating a high-endurance non-volatile memory device
US6284626B1 (en) * 1999-04-06 2001-09-04 Vantis Corporation Angled nitrogen ion implantation for minimizing mechanical stress on side walls of an isolation trench
US6362082B1 (en) * 1999-06-28 2002-03-26 Intel Corporation Methodology for control of short channel effects in MOS transistors
US6656822B2 (en) * 1999-06-28 2003-12-02 Intel Corporation Method for reduced capacitance interconnect system using gaseous implants into the ILD
US6228694B1 (en) * 1999-06-28 2001-05-08 Intel Corporation Method of increasing the mobility of MOS transistors by use of localized stress regions
US6281532B1 (en) * 1999-06-28 2001-08-28 Intel Corporation Technique to obtain increased channel mobilities in NMOS transistors by gate electrode engineering
KR100332108B1 (ko) * 1999-06-29 2002-04-10 박종섭 반도체 소자의 트랜지스터 및 그 제조 방법
TW426940B (en) * 1999-07-30 2001-03-21 United Microelectronics Corp Manufacturing method of MOS field effect transistor
US6483171B1 (en) * 1999-08-13 2002-11-19 Micron Technology, Inc. Vertical sub-micron CMOS transistors on (110), (111), (311), (511), and higher order surfaces of bulk, SOI and thin film structures and method of forming same
US6284623B1 (en) * 1999-10-25 2001-09-04 Peng-Fei Zhang Method of fabricating semiconductor devices using shallow trench isolation with reduced narrow channel effect
US6372291B1 (en) * 1999-12-23 2002-04-16 Applied Materials, Inc. In situ deposition and integration of silicon nitride in a high density plasma reactor
US6476462B2 (en) * 1999-12-28 2002-11-05 Texas Instruments Incorporated MOS-type semiconductor device and method for making same
US6221735B1 (en) * 2000-02-15 2001-04-24 Philips Semiconductors, Inc. Method for eliminating stress induced dislocations in CMOS devices
US6531369B1 (en) * 2000-03-01 2003-03-11 Applied Micro Circuits Corporation Heterojunction bipolar transistor (HBT) fabrication using a selectively deposited silicon germanium (SiGe)
US6368931B1 (en) * 2000-03-27 2002-04-09 Intel Corporation Thin tensile layers in shallow trench isolation and method of making same
US6881665B1 (en) * 2000-08-09 2005-04-19 Advanced Micro Devices, Inc. Depth of focus (DOF) for trench-first-via-last (TFVL) damascene processing with hard mask and low viscosity photoresist
US6493497B1 (en) * 2000-09-26 2002-12-10 Motorola, Inc. Electro-optic structure and process for fabricating same
US6501121B1 (en) * 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
KR100784603B1 (ko) * 2000-11-22 2007-12-11 가부시키가이샤 히타치세이사쿠쇼 반도체 장치 및 그 제조 방법
US7312485B2 (en) * 2000-11-29 2007-12-25 Intel Corporation CMOS fabrication process utilizing special transistor orientation
US6563152B2 (en) * 2000-12-29 2003-05-13 Intel Corporation Technique to obtain high mobility channels in MOS transistors by forming a strain layer on an underside of a channel
US20020086497A1 (en) * 2000-12-30 2002-07-04 Kwok Siang Ping Beaker shape trench with nitride pull-back for STI
US6265317B1 (en) * 2001-01-09 2001-07-24 Taiwan Semiconductor Manufacturing Company Top corner rounding for shallow trench isolation
US6403486B1 (en) * 2001-04-30 2002-06-11 Taiwan Semiconductor Manufacturing Company Method for forming a shallow trench isolation
US6531740B2 (en) * 2001-07-17 2003-03-11 Motorola, Inc. Integrated impedance matching and stability network
US6498358B1 (en) * 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
US6908810B2 (en) * 2001-08-08 2005-06-21 Taiwan Semiconductor Manufacturing Co., Ltd. Method of preventing threshold voltage of MOS transistor from being decreased by shallow trench isolation formation
JP2003060076A (ja) * 2001-08-21 2003-02-28 Nec Corp 半導体装置及びその製造方法
WO2003025984A2 (en) 2001-09-21 2003-03-27 Amberwave Systems Corporation Semiconductor structures employing strained material layers with defined impurity gradients and methods for fabricating same
US20030057184A1 (en) * 2001-09-22 2003-03-27 Shiuh-Sheng Yu Method for pull back SiN to increase rounding effect in a shallow trench isolation process
US6656798B2 (en) * 2001-09-28 2003-12-02 Infineon Technologies, Ag Gate processing method with reduced gate oxide corner and edge thinning
US6635506B2 (en) * 2001-11-07 2003-10-21 International Business Machines Corporation Method of fabricating micro-electromechanical switches on CMOS compatible substrates
US6461936B1 (en) * 2002-01-04 2002-10-08 Infineon Technologies Ag Double pullback method of filling an isolation trench
US6621392B1 (en) * 2002-04-25 2003-09-16 International Business Machines Corporation Micro electromechanical switch having self-aligned spacers
US6717216B1 (en) * 2002-12-12 2004-04-06 International Business Machines Corporation SOI based field effect transistor having a compressive film in undercut area under the channel and a method of making the device
US6974981B2 (en) * 2002-12-12 2005-12-13 International Business Machines Corporation Isolation structures for imposing stress patterns
US20050156208A1 (en) * 2003-09-30 2005-07-21 Taiwan Semiconductor Manufacturing Company, Ltd. Device having multiple silicide types and a method for its fabrication
US6977194B2 (en) * 2003-10-30 2005-12-20 International Business Machines Corporation Structure and method to improve channel mobility by gate electrode stress modification
US6939814B2 (en) 2003-10-30 2005-09-06 International Business Machines Corporation Increasing carrier mobility in NFET and PFET transistors on a common wafer
US6982196B2 (en) * 2003-11-04 2006-01-03 International Business Machines Corporation Oxidation method for altering a film structure and CMOS transistor structure formed therewith
US7052946B2 (en) * 2004-03-10 2006-05-30 Taiwan Semiconductor Manufacturing Co. Ltd. Method for selectively stressing MOSFETs to improve charge carrier mobility
DE102004052578B4 (de) * 2004-10-29 2009-11-26 Advanced Micro Devices, Inc., Sunnyvale Verfahren zum Erzeugen einer unterschiedlichen mechanischen Verformung in unterschiedlichen Kanalgebieten durch Bilden eines Ätzstoppschichtstapels mit unterschiedlich modifizierter innerer Spannung
US7271110B2 (en) * 2005-01-05 2007-09-18 Chartered Semiconductor Manufacturing, Ltd. High density plasma and bias RF power process to make stable FSG with less free F and SiN with less H to enhance the FSG/SiN integration reliability
US7396724B2 (en) * 2005-03-31 2008-07-08 International Business Machines Corporation Dual-hybrid liner formation without exposing silicide layer to photoresist stripping chemicals
US20070010073A1 (en) * 2005-07-06 2007-01-11 Chien-Hao Chen Method of forming a MOS device having a strained channel region
US20070018252A1 (en) * 2005-07-21 2007-01-25 International Business Machines Corporation Semiconductor device containing high performance p-mosfet and/or n-mosfet and method of fabricating the same
US7470943B2 (en) * 2005-08-22 2008-12-30 International Business Machines Corporation High performance MOSFET comprising a stressed gate metal silicide layer and method of fabricating the same
US20070075360A1 (en) * 2005-09-30 2007-04-05 Alpha &Omega Semiconductor, Ltd. Cobalt silicon contact barrier metal process for high density semiconductor power devices
US7785950B2 (en) 2005-11-10 2010-08-31 International Business Machines Corporation Dual stress memory technique method and related structure

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