CN100570889C - 在体硅和soi mos器件中制造无位错应力沟道的结构和方法 - Google Patents

在体硅和soi mos器件中制造无位错应力沟道的结构和方法 Download PDF

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CN100570889C
CN100570889C CNB2005100553049A CN200510055304A CN100570889C CN 100570889 C CN100570889 C CN 100570889C CN B2005100553049 A CNB2005100553049 A CN B2005100553049A CN 200510055304 A CN200510055304 A CN 200510055304A CN 100570889 C CN100570889 C CN 100570889C
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CN1691350A (zh
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朱慧珑
B·B·多里斯
陈华杰
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明提供了通过利用SiGe和/或Si:C的栅极应力在体硅和SOI(绝缘体上硅)CMOS(互补金属氧化物半导体)器件中制造无位错应力沟道的结构和方法。MOS器件包括体硅或SOI的衬底、衬底上的栅极介质层以及SiGe和/或Si:C的叠层栅极结构，该叠层栅极结构具有在叠层栅极结构中的SSi(应变Si)/SiGe或SSi/Si:C的界面处产生的应力。叠层栅极结构具有在栅极介质层上的大晶粒尺寸Si或SiGe的第一应力膜层、第一应力膜层上的应变SiGe或应变Si:C的第二应力膜层以及第二应力膜层上的半导体或导体如p(多晶)-Si。

Description

在体硅和SOI MOS器件中制造无位错应力沟道的结构和方法
技术领域
本发明总体上涉及通过利用SiGe和/或Si:C的栅极应力在体硅和SOI(绝缘体上硅)MOS(金属氧化物半导体)器件中制造无位错应力沟道的结构和方法。
背景技术
位错是晶体结构中的缺陷，并在具有这种位错的体硅和SOI CMOS器件中可能不利地提供漏电流的电流路径。
发明内容
本发明提供了通过利用SiGe和/或Si:C的栅极应力在体硅和SOI MOS(金属氧化物半导体)器件中制造无位错应力沟道的结构和方法。MOS器件包括体硅或SOI的衬底、衬底上的栅极介质层以及SiGe和/或Si:C的叠层栅极结构，该叠层栅极结构具有在叠层栅极结构中的SSi(应变Si)/SiGe或SSi/Si:C的界面处产生的应力。该叠层栅极结构具有在栅极介质层上的大晶粒尺寸Si或SiGe的第一应力膜层、第一应力膜层上的应变Si或应变SiGe或应变Si:C的第二应力膜层以及第二应力膜层上的半导体或导体如p(多晶)-Si或硅化物。
本说明书在此论述应力和应变，应该认识到应力和应变是相关的，应力与应变成正比，等于应变乘以常数。而且，强应变在晶体结构中常常产生位错。本说明书在此也涉及拉伸应力和压缩应力，其中拉伸应力指nFET沟道中施加的应力，压缩应力指pFET沟道中施加的应力。
本发明：
避免了在体硅和SOI(绝缘体上硅)MOS(金属氧化物半导体)器件的沟道中产生的位错；
分别施加不同类型的应力到nFET和pFET器件；
克服了可能引起窄电线断裂的SiGe的蚀刻和清洗方法；
通过用于超薄SOI器件的SiGe施加应力；
克服了在更高的温度下位错产生增加。这是由于SD RTA(源区、漏区、快速热退火)限制了在较低的温度(例如550℃)下生长的应变Si(SSi)的厚亚稳定层的使用；
克服了与高Ge％SSi/SiGe要求SSi非常薄以减小位错产生的需求相关的问题。但是，如果应变Si太薄(例如5nm，对应于35％Ge的临界厚度)，那么SSi/SiGe的界面可能降低迁移率。
本发明：
提供了通过利用SiGe和Si:C叠层栅极的应力栅极技术制造应变体硅和SOI CMOS器件的结构和方法；
由于栅极中的SSi/SiGe或SSi/Si:C的界面，允许使用大的Ge％和SiGe厚度，以产生大应力；
由于如在高温处理(例如SD RTA)之后进行的替换部分栅极的工艺(指栅极中的部分多晶硅的替换，如下面所公开和论述)，提供了更稳定的SSi/SiGe和SSi/Si:C的应力膜；
通过调整SiGe或Si:C中的Ge％或C％或通过改变薄膜厚度来控制器件沟道中的应力；
可以直接应用体硅和SOI技术，而不改变前段制程(FEOL)工艺中的常规扩散工艺。
附图说明
通过结合附图，参考以下几个实施例的详细描述，本领域的技术人员可以更容易地理解通过利用SiGe和/或Si:C的栅极应力在体硅和SOICMOS器件中制造无位错应力沟道的结构和方法的本发明的上述目的和优点，其中在整个附图中使用相同的标号表示相同的部分，以及其中：
图1至8示出了本发明的第一实施例的制造方法步骤；
图1示出了步骤1和2完成之后的结构，步骤1和2使用常规工艺在硅衬底上形成栅极氧化物，淀积非晶硅或多晶硅，并进行退火以获得具有大晶粒尺寸的多晶硅；
图2示出了步骤3之后的结构，步骤3包括氧化和蚀刻大晶粒多晶硅层上的氧化物，直到达到～10nm厚度；
图3示出了步骤4之后的结构，步骤4包括淀积p(多晶)-SiGe以形成叠层栅极；
图4示出了步骤5之后的结构，步骤5包括用于替换栅极以使器件具有栅极中的p-SiGe和围绕栅极的隔离层的常规方法；
图5示出了步骤6之后的结构，步骤6包括淀积氧化物，接着进行CMP(化学机械抛光)，在栅极顶部上停止，以及淀积薄氮化物层；
图6示出了步骤7之后的结构，步骤7包括用光致抗蚀剂覆盖并构图pFET，蚀刻氮化物，并有选择地蚀刻p-SiGe栅极用于nFET；
图7示出了步骤8之后的结构，步骤8包括除去光致抗蚀剂、选择性epi应变c-SiGe，在nFETs中再填充多晶硅，以及进行CMP，停止在氧化物上；
图8示出了步骤9之后的结构，步骤9包括淀积薄氮化物层和光致抗蚀剂，以及通常重复步骤6和7，但是此时覆盖nFET和处理pFET；
图9示出了通过使用SiGe和/或Si:C的栅极应力完成的体硅或SOICMOS器件；
图10示出了本发明的第二实施例，包括类似于第一实施例的方法步骤，但是使用弛豫的大晶粒尺寸p-Si1-xGex 100代替p-Si作为第一栅极层或籽晶层，以在栅极中生长应力膜；
图11示出了本发明的第三实施例，包括类似于第二实施例的方法，但是其中用于nFETs和pFETs的籽晶层具有不同的Ge含量，例如用于nFET的p-Si1-xnGexn110和用于pFET的p-Si1-xpGexp111；
图12示出了本发明的第四实施例，使用不同的方法通过在栅极构图之前形成叠层栅极，在栅极中形成应力层，以获得与第一、第二和第三实施例相同的结构；
图13示出了本发明的第五实施例，使用具有两个单晶硅层的键合处理晶片，两个单晶硅层具有各自的键合氧化物/硅界面和热氧化物/硅界面；
图14示出了本发明的第六实施例，使用另一方法制造具有如第五实施例所示的两个单晶层的结构。该方法使用从a-Si层的单晶再生长，开始于栅极附近的籽晶；
步骤1从单晶硅(c-Si)衬底140上的常规晶片开始，接着进行常规方法，以在硅衬底上制造栅极氧化物层142，然后淀积a-Si 144的薄层(例如，～25nm厚度)，如图14所示；
图15示出了步骤2之后的结构，步骤2包括淀积并构图光致抗蚀剂，蚀刻a-Si，并蚀刻栅极氧化物；
图16示出了步骤3之后的结构，步骤3包括除去光致抗蚀剂和淀积a-Si(～25nm)；
图17示出了步骤4之后的结构，步骤4包括构图光致抗蚀剂，以使它仍然覆盖nFET区和pFET区，以及蚀刻a-Si直到栅极氧化物，以便隔离用于晶体硅再生长的nFET区和pFET区；
图18示出了步骤5之后的结构，步骤5包括退火以再结晶a-Si层，从而形成单晶Si。
具体实施方式
图1至8示出了本发明的第一实施例的制造方法步骤。
图1示出了完成步骤1和2之后的结构。步骤1使用常规方法在晶片的Si衬底10(替换性实施例可以采用SOI技术)上形成栅极氧化物12，步骤2包括淀积a-Si(非晶硅)或多晶硅，以及退火a-Si或多晶硅，以获得具有大晶粒尺寸的多晶硅14。如果晶粒尺寸接近200nm，如图1所示，那么对于50nm的栅极器件(示为Lpo1y＝50nm)，在栅极的横向中有75％概率不能看见晶粒边界16，如图1所示。晶粒边界有助于消除材料中的应力。
图2示出了步骤3之后的结构，步骤3包括氧化和蚀刻大晶粒多晶硅层上的氧化物，直到达到～10nm厚度。
图3示出了步骤4之后的结构，步骤4包括淀积p(多晶)-SiGe，以形成叠层栅极40。
图4示出了步骤5之后的结构，步骤5包括用于替换栅极以使器件具有栅极中的p-SiGe40和围绕栅极的隔离层42的常规方法。注意所有掺杂剂被注入和退火，以变为有源区，以及对于掺杂剂激活不需要进一步扩散。
图5示出了步骤6之后的结构，步骤6包括淀积氧化物50，接着进行CMP(化学机械抛光)，在栅极顶部上停止，以及淀积薄氮化物层52，以防止当分开处理nFET和pFET时在栅极顶部上epi(外延晶体生长)。
图6示出了步骤7之后的结构，步骤7包括用光致抗蚀剂64覆盖并构图pFET，蚀刻氮化物52，并有选择地蚀刻在66处的p-SiGe40栅极用于nFET62。覆盖pFET的目的是在nFET器件和pFET器件中分别产生不同级别或类型的应力。
图7示出了步骤8之后的结构，步骤8包括除去光致抗蚀剂64，选择性epi(外延晶体生长)应变c-SiGe(单晶)70(＜临界厚度并可能需要就地对栅极进行掺杂)，在nFET 62中在72处再填充多晶硅，进行CMP，在氧化物50上停止，并可能在nFET 62中稍微回蚀刻。
图8示出了步骤9之后的结构，步骤9包括淀积薄氮化物层80和光致抗蚀剂82，以及通常重复步骤6和7，但是此时覆盖nFET 62并处理pFET 64；使用应变Si:C 84代替SiGe用于pFET，然后在86处再填充多晶硅并进行CMP，在氧化物50处停止。图8示出了晶粒边界16连续进入应变Si:C。图8示出了第一实施例完成的叠层栅极结构，在该步骤之后，使用常规方法形成用于栅极的硅化物并完成后段制程(BEOL)工作。
另一选择方案包括覆盖nFET区并将碳注入pFET栅极中，以及在700℃-850℃下退火，以在pFET栅极中的注入区中产生拉伸应力。
图9示出了通过使用SiGe和/或Si:C的叠层栅极以通过叠层栅极结构中的SSi/SiGe或SSi/Si:C的界面产生应力的栅极应力，完成的应变体硅或SOIMOS器件。图9示出了可以在体半导体(Si)10或绝缘体上半导体(SOI)90的衬底上制造的器件，该器件包括衬底顶部上的栅极介质层，以及叠层栅极结构和围绕叠层栅极结构的介质隔离层42，叠层栅极结构具有在栅极介质层12上的单晶或大晶粒尺寸Si或SiGe的第一半导体或导体应力膜层14，在第一应力膜层上的应变c-SiGe或应变Si:C的第二半导体或导体应力膜层70或84，以及在第二应力膜层上的半导体或导体膜72或86如p-Si。通过不同的材料或通过材料的不同百分比可以在不同的实施例中产生栅极中的应力/应变。
图10示出了本发明的第二实施例，包括类似于第一实施例的方法步骤，但是使用弛豫的大晶粒尺寸p-Si1-xGex 100代替p-Si作为第一栅极层，该第一栅极层用作籽晶层以在栅极中生长应力膜。在选择性外延生长步骤之后该层应变。在不同的实施例中可以改变材料的百分比以获得不同的应力。在第一实施例的步骤4中，用p-Si淀积代替p-SiGe淀积。类似地，在第一实施例的步骤7和8中，p-SiGe的选择性蚀刻步骤变为p-Si的选择性蚀刻。在此情况下，在nFET 102的栅极中生长Si1-yGey(y＞x)106，以及在pFET 104的栅极中生长Si1-zGez(z＜x)108。因此，该方法在pFET沟道中产生压缩应力和在nFET沟道中产生拉伸应力。对于pFET，该方法也可以使用Si:C代替Si1-zGez(z＜x)，尽管与Si:C具有比SiGe具有更好的热稳定性。x的值也可以用于调整pFET的Vt(阈值电压)。通常，这要求在pFET沟道中减少晕圈掺杂，这可以进一步提高pFET的性能。图10示出了进行所有方法步骤之后的最终所得结构。Si1-xGex 100是用于其上的部分栅极的籽晶层，以及在选择性外延生长之后该层应变。
图11示出了本发明的第三实施例，包括类似于第二实施例方法，但是其中用于nFET112和pFET114的籽晶层具有不同的Ge含量，例如用于nFET112的p-Si1-xnGexn110和用于pFET114的p-Si1-xpGexp111。该方法可以使用分别覆盖pFET和nFET区的常规方法。在此情况下，在nFET的栅极中生长Si1-yGey(y＞xn)116，以及在pFET的栅极中生长Si1-zGez(z＜xp)118。因此，该方法获得压缩的pFET沟道和拉伸的nFET沟道。对于pFET，该方法也可以使用Si:C代替Si1-zGez(z＜x)118，尽管与Si:C相比SiGe具有更好的热稳定性。x的值也可用于调整pFET的Vt。通常，这要求在pFET沟道中减少晕圈掺杂，这可以进一步提高pFET的性能。图10示出了最终的所得结构。在选择性外延生长之后，用于该籽晶层上的部分栅极的Si1-xnGexn110籽晶层和该籽晶层应变。在选择性外延生长之后用于该籽晶层上的部分栅极的Si1-xpGexp111籽晶层和该籽晶层应变。
图12示出了本发明的第四实施例，使用不同的方法通过在栅极构图之前形成叠层栅极120可以更容易地在栅极中形成应力层，如图12所示，以获得与第一、第二和第三实施例相同的结构。模拟表明尽管他们结构方式是相同的，但是通过第一、第二和第三实施例方法产生的应力大于由第四实施例产生的30％。在nFET和pFET区中应变SiGe或应变Si:C层分别可以具有不同的应力级别、不同的应力类型以及不同的Ge含量。在nFET和pFET区中作为用于epi SiGe或Si:C层的籽晶的大晶粒尺寸p-Si 14或p-SiGe 100可以具有不同的应力级别、不同的应力类型和不同的Ge含量。
图13示出了本发明的第五实施例。第一至第四实施例的一个缺点是叠层栅极中的晶粒中的晶体取向不同。由于在窄宽度器件的栅极中只有一个晶粒，因此这可能引起窄宽度器件的性能变化。为了避免该问题，方法可以使用具有两个单晶硅层132、134的键合处理晶片130，两个单晶硅层具有各自的键合氧化物/硅界面133和热氧化物/硅界面135，如图12所示。该结构可用于代替第一实施例的步骤2所示的结构，然后接着第一至第四实施例的其余步骤，以制造应变硅器件。为了利用Smart-Cut(在键合之后通过采用H注入以损坏单晶硅132来切割晶片，然后沿损坏的注入切割/破裂的方法)，该方法可以在键合到处理晶片130之前，在栅极氧化物131上淀积薄金属或硅化物层。薄金属或硅化物层可用于调整器件的阈值电压Vt，或获得用于给定厚度的栅极氧化物的更薄的电介质厚度。
图14示出了本发明的第六实施例，使用另一方法制造具有如第五实施例所示的两个单晶层的结构。该方法使用从a-Si层的单晶再生长，开始于栅极附近的籽晶。
步骤1从单晶c-Si衬底140上的常规晶片开始，接着进行常规方法，以在Si衬底上制造栅极氧化物层142，然后淀积a-Si 144的薄层(例如，～25nm厚度)，如图14所示。
图15示出了步骤2之后的结构，步骤2包括淀积并构图光致抗蚀剂150，在152处蚀刻a-Si，以及在154处蚀刻栅极氧化物。
图16示出了步骤3之后的结构，步骤3包括除去光致抗蚀剂150和淀积a-Si(～25nm)160，以及示出了用于单晶再生长的籽晶162。
图17示出了步骤4之后的结构，步骤4包括构图光致抗蚀剂，以使它仍然覆盖nFET区172和pFET区174，以及在170处蚀刻a-Si直到栅极氧化物，以便在162处隔离用于晶体硅再生长的nFET区172和pFET区174，该162也是STI(浅沟槽隔离)区，以便栅极氧化物的去除没有问题。
图18示出了步骤5之后的结构，步骤5包括在570℃下退火10小时，以再结晶a-Si层，从而形成单晶Si 180(Brian J.Greene等人)。在此条件下，a-Si可以再生长只要在横向上为～1μm，对于高性能器件，器件的总宽度通常小于0.5μm。在该步骤之后，可以使用第一至第四实施例中描述的方法制造在它们的栅极中具有相同晶体取向的器件。用于单晶的再生长的籽晶位置也是STI的位置，以便栅极氧化物的去除是精细的。
尽管在此详细描述了用于通过利用SiGe和/或Si:C的栅极应力在体硅和SOI MOS器件中制造无位错应力沟道的结构和方法的本发明的几个实施例和变化，但是对本领域的技术人员来说，本发明的公开和教导所暗示的许多选择性设计应该是显而易见的。

Claims (26)

1.一种体硅或绝缘体上硅金属氧化物半导体器件，具有由SiGe和/或Si:C产生的栅极应力，包括：
体硅或绝缘体上硅的衬底，以及在所述衬底上的栅极介质层；
SiGe和/或Si:C的叠层栅极结构，其中通过所述叠层栅极结构中的应变Si/SiGe或应变Si/Si:C的结构产生应力，所述叠层栅极结构具有在所述栅极介质层上的大晶粒尺寸Si或SiGe的第一应力膜层、在所述第一应力膜层上的应变SiGe或应变Si:C的第二应力膜层、以及在所述第二应力膜层上的半导体或导体。
2.根据权利要求1的器件，其中通过不同的半导体材料和/或通过半导体材料的不同百分比在所述叠层栅极结构中产生应力。
3.根据权利要求1的器件，在具有nFET器件和pFET器件的芯片上制造，以及其中所述nFET器件的沟道中具有拉伸应力和pFET器件的沟道中具有压缩应力。
4.根据权利要求3的器件，其中所述nFET器件的叠层栅极结构包括单晶硅的第一应力膜层上的应变SiGe的第二应力膜层，以及所述pFET器件的叠层栅极结构包括单晶硅的第一应力膜层上的应变Si:C的第二应力膜层。
5.根据权利要求3的器件，其中所述nFET器件的叠层栅极结构包括应变Si1-xGex的第一应力膜层上的应变Si1-yGey的第二应力膜层，以及所述pFET器件的叠层栅极结构包括应变Si1-xGex的第一应力膜层上的应变Si1-zGez的第二应力膜层，其中y＞x和z＜x，以产生不同的应力。
6.根据权利要求5的器件，其中选择x的值以调整pFET的阈值电压Vt。
7.根据权利要求5的器件，其中所述Si1-xGex是用于所述Si1-xGex层上的部分栅极的籽晶层，以及所述Si1-xGex层在选择性外延生长之后应变。
8.根据权利要求3的器件，其中所述nFET器件的叠层栅极结构包括应变Si1-xnGexn的第一应力膜层上的应变Si1-yGey的第二应力膜层，以及所述pFET器件的叠层栅极结构包括应变Si1-xpGexp的第一应力膜层上的应变Si1-zGez的第二应力膜层，其中y＞xn和z＜xp，以产生应力。
9.根据权利要求8的器件，其中所述Si1-xnGexn是用于所述Si1-xnGexn上的部分栅极的籽晶层，所述籽晶层在选择性外延生长之后应变，以及所述Si1-xpGexp是用于所述Si1-xpGexp上的部分栅极的籽晶层，所述籽晶层在选择性外延生长之后应变。
10.根据权利要求3的器件，其中所述nFET器件的叠层栅极结构包括应变Si1-xGex的第一应力膜层上的应变Si1-yGey的第二应力膜层，以及所述pFET器件的叠层栅极结构包括应变Si1-xGex的第一应力膜层上的应变Si:C的第二应力膜层，其中y＞x，以产生不同的应力。
11.根据权利要求1的器件，在包括具有所述叠层栅极结构的nFET器件和pFET器件的集成电路中制造。
12.根据权利要求1的器件，在包括具有所述叠层栅极结构的nFET器件的集成电路中制造。
13.根据权利要求1的器件，在包括具有所述叠层栅极结构的pFET器件的集成电路中制造。
14.根据权利要求1的器件，其中所述在所述第二应力膜层上的半导体或导体包括多晶硅。
15.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
在体硅或绝缘体上硅衬底上的栅极氧化物上淀积非晶硅或多晶硅，并进行退火以获得具有大晶粒尺寸的多晶硅；
在所述具有大晶粒尺寸的多晶硅上淀积多晶SiGe，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖pFET；
对nFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于nFET的多晶SiGe栅极来形成nFET，除去所述光致抗蚀剂，执行应变单晶SiGe的选择性外延生长，在nFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖nFET并处理pFET。
16.根据权利要求15的方法，包括在所述退火步骤之后氧化并蚀刻大晶粒多晶硅层，以获得选择的厚度。
17.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
在体硅或绝缘体上硅衬底上的栅极氧化物上淀积非晶硅或多晶硅，并进行退火以获得具有大晶粒尺寸的多晶硅；
在所述具有大晶粒尺寸的多晶硅上淀积多晶SiGe，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖nFET；
对pFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于pFET的多晶SiGe栅极来形成pFET，除去所述光致抗蚀剂，执行应变单晶SiGe的选择性外延生长，在pFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖pFET并处理nFET。
18.根据权利要求17的方法，包括在所述退火步骤之后氧化并蚀刻大晶粒多晶硅层，以获得选择的厚度。
19.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
在体硅或绝缘体上硅衬底上的栅极氧化物上淀积弛豫的大晶粒多晶Si1-xGex，并进行退火以获得具有大晶粒尺寸的多晶Si1-xGex；
在所述具有大晶粒尺寸的多晶Si1-xGex上淀积多晶硅，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖pFET；
对nFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于nFET的多晶硅栅极来形成nFET，除去所述光致抗蚀剂，执行应变单晶Si1-yGey的选择性外延生长，其中y＞x，在nFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖nFET并处理pFET，生长Si1-zGez，其中z＜x。
20.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
在体硅或绝缘体上硅衬底上的栅极氧化物上淀积弛豫的大晶粒多晶Si1-xGex，并进行退火以获得具有大晶粒尺寸的多晶Si1-xGex；
在所述具有大晶粒尺寸的多晶Si1-xGex上淀积多晶硅，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖nFET；
对pFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于pFET的多晶硅栅极来形成pFET，除去所述光致抗蚀剂，执行应变单晶Si1-yGey的选择性外延生长，其中y＞x，在pFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖pFET并处理nFET，生长Si1-zGez，其中z＜x。
21.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该器件具有由SiGe和/或Si:C产生的栅极应力，该方法包括以下步骤：
形成在叠层结构中的应变Si/SiGe或应变Si/Si:C的界面处具有应力的SiGe和/或Si:C的叠层结构，其中所述叠层结构具有在所述栅极介质层上的大晶粒尺寸Si或SiGe的第一应力膜层、在所述第一应力膜层上的应变SiGe或应变Si:C的第二应力膜层、以及在所述第二应力膜层上的半导体或导体；以及
构图所述叠层结构，以形成构图的叠层栅极结构。
22.根据权利要求21的器件，其中所述在所述第二应力膜层上的半导体或导体包括多晶硅。
23.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
形成具有两个单晶硅层的键合处理晶片，所述两个单晶硅层具有各自的氧化物/硅界面；
在所述键合处理晶片上淀积多晶SiGe，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖pFET；
对nFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于nFET的多晶SiGe栅极来形成nFET，除去所述光致抗蚀剂，执行应变单晶SiGe的选择性外延生长，在nFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖nFET并处理pFET。
24.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
形成具有两个单晶硅层的键合处理晶片，所述两个单晶硅层具有各自的氧化物/硅界面；
在所述键合处理晶片上淀积多晶SiGe，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖nFET；
对pFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于pFET的多晶SiGe栅极来形成pFET，除去所述光致抗蚀剂，执行应变单晶SiGe的选择性外延生长，在pFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖pFET并处理nFET。
25.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
在体硅或绝缘体上硅衬底上形成栅极氧化物层，然后淀积非晶硅层；
淀积并构图光致抗蚀剂，蚀刻所述非晶硅，并蚀刻所述栅极氧化物；
除去所述光致抗蚀剂并淀积非晶硅；
淀积并构图光致抗蚀剂以覆盖将要形成nFET和pFET的区域，并蚀刻所述非晶硅直到所述栅极氧化物，以隔离用于晶体重结晶的nFET和pFET的区域；
退火所述结构，以重结晶所述非晶硅层，从而形成单晶硅；
在所述单晶硅上淀积多晶SiGe，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖nFET；
对pFET进行以下处理：通过蚀刻所述薄氮化物层和有选择地蚀刻用于pFET的多晶SiGe栅极来形成pFET，除去所述光致抗蚀剂，执行应变单晶SiGe的选择性外延生长，在pFET中填充多晶硅并进行化学机械抛光，在所述氧化物上停止；
淀积薄氮化物层和光致抗蚀剂并重复先前的方法步骤，但是此时覆盖pFET并处理nFET。
26.一种制造体硅或绝缘体上硅金属氧化物半导体器件的方法，该方法包括以下步骤：
在体硅或绝缘体上硅衬底上的栅极氧化物上淀积非晶硅或多晶硅，并进行退火以获得具有大晶粒尺寸的多晶硅；
在所述具有大晶粒尺寸的多晶硅上淀积多晶SiGe，以形成叠层栅极；
对所述叠层栅极进行构图；
淀积氧化物，接着进行化学机械抛光，在所述栅极顶部上停止，并淀积薄氮化物层；
用光致抗蚀剂覆盖所述薄氮化物层并构图所述光致抗蚀剂和所述薄氮化物层，以用所述光致抗蚀剂和所述薄氮化物层覆盖nFET；
通过将碳注入pFET栅极的多晶SiGe中来形成pFET，并进行退火以在pFET栅极中的注入区中产生拉伸应力。
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US20050236668A1 (en) 2005-10-27
US7504693B2 (en) 2009-03-17
TW200608590A (en) 2006-03-01
US20080064197A1 (en) 2008-03-13
US7713806B2 (en) 2010-05-11
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US7476580B2 (en) 2009-01-13

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