CN100573495C - The transmission method of serial circumference interface serial type flash memory - Google Patents
The transmission method of serial circumference interface serial type flash memory Download PDFInfo
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- CN100573495C CN100573495C CNB2007100038047A CN200710003804A CN100573495C CN 100573495 C CN100573495 C CN 100573495C CN B2007100038047 A CNB2007100038047 A CN B2007100038047A CN 200710003804 A CN200710003804 A CN 200710003804A CN 100573495 C CN100573495 C CN 100573495C
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Abstract
The present invention discloses the transmission method of a kind of serial circumference interface (SPI) serial type flash memory, comprises the step that first clock signal of system is provided and transmits one two bit data in a plurality of serial datas in the one-period of this first clock signal of system.Second clock signal of system that is produced by this first clock signal of system of frequency multiplication is to input or output transfer rate from this serial circumference interface (SPI) serial type flash memory in order to increase all.
Description
Technical field
The invention relates to the transmission method of a kind of serial circumference interface (SPI) serial type flash memory, refer to a kind of serial circumference interface (SPI) serial type flash memory transmission method that utilizes double data rate (DDR) especially.
Background technology
Press, general run-in index flash memory (Parallel Flash) has very many pins (more than 20) usually, in order to inputoutput data, reception power supply signal, receiver address signal and reception control signal.Yet when running, the pin of part is not used.When printed circuit board (PCB) (PCB) or other similarity use run-in index flash memory, can have the cost and the complicated shortcomings such as control circuit that on printed circuit board (PCB), occupy excessive area, increase system usually.For the design that promotes printed circuit board (PCB) and reduce cost, a kind of serial type flash memory (Serial Flash) promptly is developed.
Fig. 1 discloses each pin function of general serial circumference interface serial type flash memory (SPI Serial Flash) 10.Compare with the run-in index flash memory, serial circumference interface serial type flash memory 10 has less pin, the function of each pin be sketch in after.Pin SCK (serial clock, i.e. serial clock) is to provide work clock to serial circumference interface; Instruction, address or data input are to be latched in the rising edge of input clock, and data then are output in the drop edge of input clock.Pin SI (serial data input, i.e. serial data input) be with instruction, address or data continuous input to serial circumference interface serial type flash memory 10, and these a little inputs are to be latched in the rising edge of input clock.Pin SO (serial dataoutput, i.e. serial data output) is with continuous the exporting from serial circumference interface serial type flash memory 10 of data, and these data are to be output in the drop edge of input clock.Pin CE# (chip enable, i.e. enable signal) is by coming activation serial circumference interface serial type flash memory 10 by high level to low level variation, and it must maintain low level during any instruction sequence input.Pin WP# (writeprotect, i.e. write protection) is whether to programme in order to decision.Pin HOLD# (being holding signal) temporarily stops its serial communication under the situation of not reseting (reset) serial circumference interface serial type flash memory 10.V
DDBe power supply supply voltage, and V
SSIt then is ground voltage.
Fig. 2 discloses known serial circumference interface serial type flash memory 10 and reads precedence diagram, as shown in the figure: in the time of during reading, signal CE# must remain on low level, reading command is to begin by the order of carrying out one or eight (as 03H), and back to back 24 address bits are regarded as three group address signal ADDs.Reading order (03H) is via 8 cycles of pin SI received signal SCK (from the cycle 0 to the cycle 7), the output of 24 interior data of address bit is to begin in the drop edge in the 31st cycle of signal SCK, till low level was transformed into high level, wherein a byte in the data (eight positions) need take 8 cycles of signal SCK up to signal CE#.Before data output, pin SO can remain on high impedance (HIGH IMPEDANCE).In general, the data output rate of serial circumference interface serial type flash memory 10 is about 50MHz (50M bits/second), and is slow than the output speed of run-in index flash memory.Have smaller volume though only have the serial circumference interface serial type flash memory 10 of an output connecting pin, sacrificed its data output rate.Concerning serial circumference interface serial type flash memory 10, in the one-period of signal SCK, two data can be via pin SI input, that is the clock frequency of signal SCK limited the input of order, address and data, has also limited the output speed that is read data.
Therefore, with general serial circumference interface serial type flash memory 25MHz to the operation rate of 50MHz by comparison, the another kind of method that increases the serial circumference interface serial type flash memory output speed promptly is developed, and the speed of its access data can be increased to 75MHz.For data output rate is doubled, the input pin SI of serial circumference interface serial type flash memory can be taken as another output connecting pin and use between the data period of output, so can on four identical pin serial circumference interface serial type flash memory interfaces, in a clock period, export two data.Yet this mode only can double data output rate, and other operation is still limited by clock frequency.
Because the shortcoming of above-mentioned serial circumference interface serial type flash memory, it is not perfect to attaining for inventor's thoughts, then exhaust intelligence, concentrated research overcomes, with being engaged in the experience accumulation for many years of this industry, and then develop a kind of transmission method of serial circumference interface serial type flash memory, to reach the effect person who increases transfer rate.
Summary of the invention
By being, fundamental purpose of the present invention, promptly be to provide a kind of transmission method of serial circumference interface serial type flash memory, it is a technology of utilizing Double Data Rate (DDR), reaches the effect person who increases serial circumference interface serial type flash memory operating speed (comprising data output rate).
For reaching above-mentioned purpose, technology of the present invention is achieved as follows:
A kind of transmission method of serial circumference interface serial type flash memory, comprise the following step: provide first clock signal of system with first frequency, and, has second clock signal of system of second frequency with generation with this first frequency frequency multiplication of this first clock signal of system; And in the one-period of this second clock signal of system one two bit data of transmission in a plurality of serial datas, this serial data includes a plurality of orders (erase as reading order, byte program command, section order and other order etc.), a plurality of data (as reading of data and programming data) and a plurality of addresses relevant with these data.This each order that respectively has eight bit lengths is that (or in 8 cycles of this second system clock) quilt is imported in this serial circumference interface serial type flash memory in 4 cycles of this first clock signal of system; This each address that respectively has 24 bit lengths is that (or in 24 cycles of this second system clock) quilt is imported in this serial circumference interface serial type flash memory in 12 cycles of this first clock signal of system." flash memory " is meant a kind of nonvolatile memory of electrically erasing and programming that utilizes in herein.
With the read operation transmission method of (serial data comprises reading order, reading of data and the address relevant with this reading of data), transmission method of the present invention also is contained in the step that is provided after this address transfer time delay.Take 8 cycles of this second clock signal of system this time delay, person very, can adjust this time delay according to inner reading speed.In another embodiment, this transmission method also comprises the step that startup is read ready signal and exported reading of data from output connecting pin.A byte in this reading of data is to be output in 8 cycles of this second clock signal of system.
With the programming operation transmission method of (serial data comprises program command, programming data and the address relevant with this programming data), transmission method of the present invention also is contained in 8 cycles of this second clock signal of system and a byte in the programming data inputed to this address, in steps such as the 20th all after date anergy chip enable signal of this first clock signal of system and the operations of beginning inside programming.
With the transmission method of erase operation for use (serial data comprises the order of erasing, the data of erasing and the address relevant with this order of erasing), transmission method of the present invention also is contained in the 16th all after date anergy chip enable signal of this first clock signal of system and begins steps such as inner erase operation for use.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and cooperate appended graphicly, be described in detail below.
Description of drawings
Fig. 1 discloses the pin arrangement plan of general serial circumference interface serial type flash memory.
Fig. 2 discloses the precedence diagram that reads of known serial circumference interface serial type flash memory.
Fig. 3 is the transmission time sequence figure of the embodiment of the invention.
Fig. 4 exports the sequential chart of reading of data embodiment for the present invention.
[main element label declaration]
10: serial circumference interface serial type flash memory
CEN-R, CEN-P, CEN-E: chip enable signal
XSCK: first clock signal of system
Sck2: second clock signal of system
RC: read ready signal
PC: programming ready signal
EC: the ready signal of erasing
Latency: time delay
XSO: output connecting pin
ADDRESS: address
Embodiment
Fig. 3 is the transmission time sequence figure of the embodiment of the invention, and it includes operations such as reading, programme and erase.The first clock signal of system XSCK with first frequency provides by outer clock circuit, the second clock signal of system sck2 with second frequency is by this first frequency is doubled to produce, a plurality of subsequently serial datas can transmit, and transmit the bit data in this serial data in the one-period of this second clock signal of system sck2.In Fig. 3, serial data comprises three parts: the serial data of first is contained in the phase one reading order that (Phase 1) be transmitted and reads the address in what subordinate phase (Phase 2) was transmitted; The serial data of second portion is contained in the phase one program command that (Phase 1) be transmitted, in programming address that subordinate phase (Phase 2) is transmitted and the programming data that is transmitted in the phase III (Phase 3); The serial data of third part is contained in the phase one address of erasing of erasing order and being transmitted in subordinate phase (Phase 2) that (Phase 1) is transmitted.Wherein, the second clock signal of system sck2 produces in rising edge and the place, drop edge of the first system frequency signal XSCK.So, in another embodiment, the second clock signal of system sck2 can postpone the first system frequency signal XSCK by preset time.Input command data orders such as (as) reading, programme or erase, address and the programming data relevant with the input command data are to align with rising edge and the drop edge of the first system frequency signal XSCK, with decision start time (setup time) and retention time (hold time).In addition, also to be contained in the 4th cycle (referring to the cycle 4th among Fig. 3) the back determination data string of the first system frequency signal XSCK be steps such as reading order, program command or the order of erasing to transmission method of the present invention.Again, because chip enable signal CEN-R, CEN-P or CEN-E were not in low level at the 0th of the first system frequency signal XSCK before the cycle, therefore, the 0th cycle of the first system frequency signal XSCK is not its first cycle.
In read operation, the serial data that is transmitted includes eight reading order, reading of data and two ten four bit address relevant with reading of data.At first, when read operation, chip enable signal CEN-R can be converted to low level, and first rising edge of the first system frequency signal XSCK can be read the order affirmation in order to start the second system frequency signal sck2.When signal RC is in low level, reading order then can be in phase one (Phase 1), promptly the cycle 1st of the first clock signal of system XSCK is to the cycle 0th of the cycle 4th or the second clock signal of system sck2 during to cycle 7th, imported in the serial circumference interface serial type flash memory, so the transmission reading order needs the time in 4 cycles of the first clock signal of system XSCK.Subsequently, when signal RC changes high level into, 24 bit address then can be in subordinate phase (Phase 2), promptly the cycle 5th of the first clock signal of system XSCK is to the cycle 8th of the cycle 16th or the second clock signal of system sck2 during to cycle 31th, imported in the serial circumference interface serial type flash memory, so transmission 24 bit address need the time in 24 cycles of the second clock signal of system sck2.Be in order to providing the reading of data in the self-access memory crystal cell to be read the required time time delay (latency) that takies 8 cycles of the second clock signal of system sck2 in Fig. 3, and can adjust time delay (latency) according to inner reading speed.Time delay (latency) later, read ready signal RD and then can be activated to high level, use via output connecting pin reading of data exported.
Fig. 4 exports the sequential chart of reading of data embodiment for the present invention.Consult Fig. 3 and Fig. 4, reading of data in the A of address (ADDRESS) is latched when the drop edge of the first clock signal of system XSCK cycle 20th, when reading ready signal RD and be activated to high level, the reading of data in the A of address (ADDRESS) then can be exported via output connecting pin XSO during 4 cycles (i.e. 8 cycles of the second clock signal of system sck2) of the first clock signal of system XSCK; Simultaneously, another reading of data will be read in the A+1 of address (ADDRESS), and whole read operation will last till that chip enable signal CEN-R changes into till the high logic level.No matter the rising edge or the drop edge that are the first clock signal of system XSCK all can be used to carry out reading of data, so the output speed of data promptly becomes two times.
In the programming operation of Fig. 3, the serial data that is transmitted includes eight program commands, programming data and two ten four bit address relevant with programming data.At first, when programming operation, chip enable signal CEN-P can be converted to low level, and first rising edge of the first clock signal of system XSCK can be programmed the order affirmation in order to start the second clock signal of system sck2.When signal PC is in low level, program command then can be in phase one (Phase 1), promptly the cycle 1st of the first clock signal of system XSCK is to the cycle 0th of the cycle 4th or the second clock signal of system sck2 during to cycle 7th, imported in the serial circumference interface serial type flash memory, so the transmission program command needs the time in 4 cycles of the first clock signal of system XSCK.Subsequently, when signal PC changes high level into, 24 bit address then can be in subordinate phase (Phase 2), promptly the cycle 5th of the first clock signal of system XSCK is to the cycle 8th of the cycle 16th or the second clock signal of system sck2 during to cycle 31th, imported in the serial circumference interface serial type flash memory, so transmission 24 bit address need the time in 12 cycles of the first clock signal of system XSCK.After the transmission of 24 bit address (after the cycle 16th of the first clock signal of system XSCK), a byte in the programming data can be transferred in the serial circumference interface serial type flash memory in 4 cycles of the first clock signal of system XSCK.Subsequently, chip enable signal CEN-P can be converted to high level, carries out the inside programming operation to start programming ready signal Apgm.
In erase operation for use, the serial data that is transmitted includes eight erase order and two ten four bit address relevant with the order of erasing.At first, when erase operation for use, chip enable signal CEN-E can be converted to low level, and the order affirmation can be erased in order to start the second clock signal of system sck2 in first rising edge of the first clock signal of system XSCK.When signal EC is in low level, erasing order then can be in phase one (Phase 1), promptly the cycle 1st of the first clock signal of system XSCK is to the cycle 0th of the cycle 4th or the second clock signal of system sck2 during to cycle 7th, imported in the serial circumference interface serial type flash memory, order needs the time in 4 cycles of the first clock signal of system XSCK so transmission is erased.Subsequently, when signal EC changes high level into, 24 bit address then can be in subordinate phase (Phase 2), promptly the cycle 5th of the first clock signal of system XSCK is to the cycle 8th of the cycle 16th or the second clock signal of system sck2 during to cycle 31th, imported in the serial circumference interface serial type flash memory, so transmission 24 bit address need the time in 12 cycles of the first clock signal of system XSCK.After 24 bit address transmission (after the cycle 16th of the first clock signal of system XSCK), chip enable signal CEN-E can be converted to high level, carries out inner erase operation for use with the startup ready signal Aers that erases.
In Fig. 3, disclosed read, the transmission method of programming and erase operation for use, be meant that each two bit data in the serial data all can utilize the rising of the first clock signal of system XSCK and drop edge to transmit.In the serial data each two bit data are not to be limited and must to transmit in decline and the rising edge of the first clock signal of system XSCK, and also non-being restricted to of serial data read, programmed and erase order.Any serial data from serial circumference interface serial type flash memory output or input (increase program command, write the activation order, write anergy order or the like as page or leaf program command, automatic address) all can utilize Double Data Rate of the present invention (DDR) method to transmit, and uses the increase transfer rate.
According to the various embodiments described above, be not only data output rate, the input rate of order input rate, address input rate and programming data all will improve.Therefore, the present invention's purpose of increasing the serial circumference interface serial type flash memory operating speed can be reached.
The designing technique of DDR DRAM (Double Data Rate dynamic RAM) can be applied to double data rate serial perimeter interface flash memory, can be with reference to its differential input mode.Synchronous for rising and the drop edge of asking second clock signal of system and first clock signal of system, can utilize phase-locked loop (PLL) to reach.
Though the present invention discloses as above with preferred embodiment; right its is not in order to limit the present invention; any those skilled in the art; without departing from the spirit and scope of the present invention; when can doing a little change and retouching, so protection scope of the present invention is as the criterion when looking appended the claim scope person of defining.
Claims (17)
1, a kind of transmission method of serial circumference interface serial type flash memory comprises the following step:
First clock signal of system with first frequency is provided;
With this first frequency frequency multiplication of this first clock signal of system, has second clock signal of system of second frequency with generation; And
Transmit an one digit number certificate in a plurality of serial datas in regular turn according to a plurality of cycles of this second clock signal of system;
Wherein, this serial data comprises reading order and the address via the transmission of input pin,
Wherein, this reading order and this address are respectively at being transferred to this serial circumference interface serial type flash memory in 8 cycles of this second clock signal of system and 24 cycles.
2, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, also be contained in after this address transfer finishes, the step of time delay is provided.
3, according to the transmission method of the serial circumference interface serial type flash memory of claim 2, wherein, can adjust this time delay according to inner reading speed.
4, according to the transmission method of the serial circumference interface serial type flash memory of claim 2, wherein, be 8 cycles that take this second clock signal of system this time delay.
5, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, it also comprises the following step:
Start and read ready signal; And
The data that read out are exported via output connecting pin.
6,, wherein, be stored in that a byte in the data is to be output in 8 cycles of this second clock signal of system in this address according to the transmission method of the serial circumference interface serial type flash memory of claim 1.
7, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, wherein, this serial data comprises program command, address and programming data.
8, according to the transmission method of the serial circumference interface serial type flash memory of claim 7, wherein, this program command and this address are respectively at being transferred to this serial circumference interface serial type flash memory in 8 cycles of this second clock signal of system and 24 cycles.
9,, also be contained in 8 cycles of this second clock signal of system a byte in this programming data is inputed to this address according to the transmission method of the serial circumference interface serial type flash memory of claim 7.
10, according to the transmission method of the serial circumference interface serial type flash memory of claim 9, it also comprises the following step:
Start the programming ready signal; And
Begin to carry out the inside programming operation.
11, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, wherein, this serial data comprises erase order and address.
12, according to the transmission method of the serial circumference interface serial type flash memory of claim 11, wherein, this erase order and this address are respectively at being transferred to this serial circumference interface serial type flash memory in 8 cycles of this second clock signal of system and 24 cycles.
13, according to the transmission method of the serial circumference interface serial type flash memory of claim 11, it also comprises the following step:
Start the ready signal of erasing; And
Begin to carry out inner erase operation for use.
14, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, wherein, this second clock signal of system is in the rising edge of this first clock signal of system and the place, drop edge produces.
15, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, wherein, this serial data that comprises input command data, address and programming data is to align with the rising edge and the drop edge of this first system frequency signal, with decision start time and retention time.
16, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, wherein, one two in these data is to utilize the drop edge of this first clock signal of system and rising edge to transmit.
17, according to the transmission method of the serial circumference interface serial type flash memory of claim 1, its 4th all after date that also is contained in the first system frequency signal determines the step of this serial data.
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| CN111506529B (en) * | 2020-06-30 | 2020-10-16 | 深圳市芯天下技术有限公司 | High-speed SPI instruction response circuit applied to FLASH |
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