CN100578792C - NAND non-volatile memory and array thereof - Google Patents
NAND non-volatile memory and array thereof Download PDFInfo
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- CN100578792C CN100578792C CN200610100014A CN200610100014A CN100578792C CN 100578792 C CN100578792 C CN 100578792C CN 200610100014 A CN200610100014 A CN 200610100014A CN 200610100014 A CN200610100014 A CN 200610100014A CN 100578792 C CN100578792 C CN 100578792C
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- 230000015654 memory Effects 0.000 title claims abstract description 89
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- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 claims description 36
- 229910052581 Si3N4 Inorganic materials 0.000 claims description 24
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 claims description 24
- 239000000758 substrate Substances 0.000 claims description 24
- 238000012163 sequencing technique Methods 0.000 claims description 19
- 235000012239 silicon dioxide Nutrition 0.000 claims description 18
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- WQJQOUPTWCFRMM-UHFFFAOYSA-N tungsten disilicide Chemical compound [Si]#[W]#[Si] WQJQOUPTWCFRMM-UHFFFAOYSA-N 0.000 description 5
- 229910021342 tungsten silicide Inorganic materials 0.000 description 5
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Abstract
The invention discloses a non-volatile binary memory unit, comprising a unit stack and two selecting stacks arranged on an active area of one liner, wherein each selecting stack is arranged at one side of the unit stack while a side wall is arranged between the unit stack and each selecting stack. The unit stack comprises four portions as a first dielectric layer above the liner, a charge accumulation layer above the first dielectric layer for keeping one portion of charges to store information, a second dielectric layer above the charge accumulation layer, and a control grid above the second dielectric layer. The selecting stack comprises two portions as a third dielectric layer above the liner, and a selecting grid above the third dielectric layer which can convert the lower portion of one selecting stack into source/drain function of memory unit.
Description
Technical field
The present invention relates to a kind of semiconductor storage, particularly relate to a kind of and two flash memories of non-volatile.
Background technology
Although do not have the time a segment length under the situation of power supply supply, Nonvolatile semiconductor memory device still can keep stored data and can not miss.According to this specific character, in general non-volatile memory can be divided into ROM (read-only memory), PROM (programmble read only memory PROM), EPROM (programmble read only memory PROM of can erasing), EEPROM (electricity can erase programmble read only memory PROM) and flash memory or the like.Can erase fast/ability of sequencing because have, the EEPROM flash memory is widely used in storing in the device of mass data, as storage card, PDA (personal digital assistant) and MP3 player or the like.
The EEPROM flash memory is broadly divided into two kinds on NAND (with non-) type and NOR (or non-) type.The NAND flash memory has memory cell many and the shared source electrode of adjacent cells and the drain electrode and the bunchiness of connecting, and the NOR flash memory then has the memory cell of many parallel connections, and independently has its source electrode and drain electrode separately.Because this species diversity, the NAND flash memory will have higher cell density than NOR flash memory.
United States Patent (USP) is announced No. 6885586 and has been described a kind of self aligned separated grid NAND flash memory, its each memory cell comprises mutual storehouse and mutual self aligned control grid and floating grid, and the separated grid for erasing between between stacked gate.Floating grid is formed by a kind of polysilicon or this electric conducting material manufacturing of amorphous silicon with rounded sides, erases and the effect of sequencing in order to improvement.In the running of erasing, (Fu Le-Nuo Dehan) tunneling effect penetrates to its pairing separated grid by F-N from its rounded sides can to impel electronics by the electric field enhancing that circular bend caused of floating grid.In the running of sequencing, electronics will inject or F-N tunneling effect and being injected in the floating grid by channel region by hot electron.One memory cell can store one information.
Under for the demand that stores mass data and reduce cost, a kind of memory cell that can store two information and increase data storage density promptly is developed.
Summary of the invention
Main purpose of the present invention promptly is to provide a kind of and non-volatile two bit memories and manufacture method thereof, uses to reach the effect that stores mass data and reduce cost.
For reaching above-mentioned purpose, technology of the present invention is achieved as follows:
A kind of and non-volatile two bit memory cell, comprise that the cell stack that is disposed on substrate one active region and two selects storehouses, each selects storehouse to be disposed at a side of cell stack respectively and in cell stack and respectively select to dispose between the storehouse sidewall.Cell stack comprises four parts: one is disposed at first dielectric layer of substrate top; One is disposed at the electric charge accumulation layer of first dielectric layer top, electric charge can be remained in some and come store information; One is disposed at second dielectric layer of electric charge accumulation layer top; An and control grid that is disposed at second dielectric layer top.Select storehouse to comprise two parts: one is disposed at the 3rd dielectric layer of substrate top; And a selection grid that is disposed at the 3rd dielectric layer top, can one select storehouse below district be converted into the source/drain function of memory cell.
For above and other objects of the present invention, feature and advantage can be become apparent, preferred embodiment cited below particularly, and conjunction with figs. is described in detail below.
Description of drawings
Fig. 1 stores two and cross-sectional view non-memory cell embodiment for the present invention has;
Fig. 2 is the circuit diagram of memory cell array of the present invention;
Fig. 3 A is for forming two serializer circuit figure of memory cell array of the present invention;
Fig. 3 B implements illustration for one of the present invention's two serializer circuits;
Fig. 4 erases for being disclosed in, sequencing and reading in the memory cell process, bit line, word line, control grid, selects grid and other service voltage signal table;
Fig. 5 A-5L is the cross-sectional view of each operation stage of the present invention.
The simple symbol explanation
100 memory cells, 110 substrates
120 active regions, 130 cell stacks
132 first dielectric layers, 134 electric charge accumulation layers
136 second dielectric layers, 138 control grids
140 select storehouse 142 to select grid
145 select storehouse 147 to select grid
150 sidewalls, 155 sidewalls
160 the 3rd dielectric layers 165 the 3rd dielectric layer
502 substrate 504P trap active layers
506 oxide layers, 508 silicon nitride layers
510 silicon dioxide layers, 512 polysilicon layers
514 tungsten silicide layers, 516 silicon nitride layers
518 photoresist layer 520-530 cell stacks
540 silicon nitride layers, 542 bottom layer
544 side portion, 546 top layer portions
550 silicon dioxide layers, 552 bottom layer
554 side portion, 556 top layer portions
560 silicon dioxide layers, 562 polysilicon layers
564 photoresist layers, 556 silicon dioxide layer
Embodiment
A kind of and non-volatile two bit memory cell comprise electric charge being remained in the electric charge accumulation layer that some is come store information that the either side of electric charge accumulation layer all can store one information, and therefore, a memory cell can store two information.Arbitrary memory cell comprises that a cell stack and two with control grid and electric charge accumulation layer has the selection storehouse of selecting grid.Arbitrary selection stack arrangement is in a side of cell stack and dispose a sidewall between cell stack and selection storehouse, select storehouse when selecting the grid service voltage to be higher than its critical voltage, to select storehouse below district to be converted into the source/drain regions of memory cell with one.By the control service voltage, select grid in the sequencing running, to inject by the electronics of control source side.
As shown in Figure 1, a kind of and non-volatile two bit memory cell 100, comprise that the cell stack 130 that is disposed on substrate 110 1 active regions 120 and two selects storehouses 140,145, each selects storehouse 140,145 to be disposed at a side of cell stack 130 respectively and in cell stack 130 and respectively select to dispose between the storehouse 140,145 sidewall 150,155.Cell stack 130 comprises that one is disposed at first dielectric layer 132 of substrate 110 tops; One is disposed at the electric charge accumulation layer 134 of first dielectric layer, 132 tops, electric charge can be remained in some and come store information; One is disposed at second dielectric layer 136 of electric charge accumulation layer 134 tops; An and control grid 138 that is disposed at second dielectric layer, 136 tops.The either side of electric charge accumulation layer 134 can keep electric charge respectively, and therefore, a memory cell 100 can store two information (position 0 and position 1).
Each selects storehouse 140,145 to comprise that one is disposed at the 3rd dielectric layer 160,165 of substrate 110 tops; And a selection grid 142,147 that is disposed at the 3rd dielectric layer 160,165 tops, can one select storehouse below district be converted into the source/drain function of memory cell.When selecting grid 142,147 service voltages to be higher than its critical voltage, the part that can carry out sequencing according to electric charge accumulation layer 134 is converted into the channel region of selecting grid 142,147 belows the source/drain function of memory cell.
When the right side part of sequencing electric charge accumulation layer 134 (position 0), the right side selects the conversion channel region of below, storehouse 145 right sides can have the source electrode function of memory cell.When the left part of sequencing electric charge accumulation layer 134 (position 1), the left side selects the conversion channel region of storehouse 140 belows can have the source electrode function of memory cell.By the control service voltage, select grid 142,147 can in the sequencing running, control electronics injection toward electric charge accumulation layer 134 of source side from source area.
In one embodiment, substrate 110 is formed by the semi-conducting material as silicon, and in substrate 110, active region 120 is formed by P trap layer; Above active region 120, a thickness is that first dielectric layer 132 of 30-50 dust is silicon dioxide layer, and the function of insulation can be provided; Above first dielectric layer 132, a thickness is that the electric charge accumulation layer 134 of 60-80 dust is a silicon nitride layer, can provide the function that keeps electric charge when memory cell is carried out the process of sequencing; Above electric charge accumulation layer 134, a thickness is that second dielectric layer 136 of 20-40 dust is silicon dioxide layer; Above second dielectric layer 136, a thickness is formed by polysilicon by the control grid 138 of 1000 dusts; Select grid 142,147 to be formed by polysilicon, and with control grid 138 place's adjacency.At cell stack 130 and select the sidewall 150,155 of 140,145 in storehouse to comprise two layers, be respectively with cell stack 130 in abutting connection with and by the made interior layer of silicon nitride and with select storehouse 140,145 in abutting connection with and by the made exterior layer of silicon dioxide; And the thickness of sidewall 150,155 is about 180 dusts.At the 3rd dielectric layer 160,165 of selecting 110 of grid 142,147 and substrates are silicon dioxide layers that a thickness is about 140 dusts.
Fig. 2 discloses a kind of and non-volatile two bit memory cell arrays, and a plurality of memory cells are arranged in row and row, are a unit strings and be connected at the memory cell with delegation.Select transistor to be connected in each end of unit strings, the multi-memory unit that is positioned at even number line forms an even location string, and the multi-memory unit that is positioned at odd-numbered line forms an odd location string; Being connected to two of even location string one end, to select transistors be the even number string select transistor, and to select transistors be the odd number string select transistor and be connected to two of odd location string one end.Fig. 3 A is by an even location string, two even number string select transistors, an odd location string, two odd number string select transistors, formed two serializer circuit figure, as shown in the figure: the first even number string select transistor and the first odd number string select transistor are disposed at an end (upper end) of two serializer circuits, to be connected with even bitlines; The second even number string select transistor and the second odd number string select transistor are disposed at an end (lower end) of two serializer circuits, to be connected with odd bit lines.
In Fig. 2, it is right that array has M memory cell strings and is divided into (M+1)/2 unit strings, and each unit strings is to all containing an even location string and an odd location string.Each unit strings is wherein selected storehouse two sides that are disposed at cell stack at interval to also containing N the memory cell that utilizes N cell stack and N+1 selection storehouse connection bunchiness, and disposes a sidewall between cell stack and selection storehouse.Because the arrangement of this kind, the selection storehouse that is disposed between two cell stacks can be shared by two memory cells of its adjacency.For instance, as shown in Figure 3A, select 1 in storehouse to be shared by memory cell 0 and memory cell 1; Specifically, memory cell 0 comprises to be selected storehouse 0, cell stack 0 and selects storehouse 1, and memory cell 1 then comprises to be selected storehouse 1, cell stack 1 and select storehouse 2.
The bit line that comprises even bitlines and odd bit lines is to being connected to one or two serializer circuits.Even bitlines is connected with an end of two serializer circuits via the first even number string select transistor and the first odd number string select transistor, and odd bit lines is connected with the other end of two serializer circuits via the second even number string select transistor and the second odd number string select transistor.For instance, bit line 0 (BL 0) is connected with the upper end of unit strings 0 and the upper end of unit strings 1 via the first even number string select transistor and the first odd number string select transistor respectively; Bit line 1 (BL 1) is connected with the lower end of unit strings 0 and the lower end of unit strings 1 via the second even number string select transistor and the second odd number string select transistor respectively.In the process of sequencing, bit line 0 can provide voltage to unit strings 0 and unit strings 1 with bit line 1, yet, only have in unit strings 0 and the unit strings 1 and a stringly selectedly carry out sequencing by even number string select transistor or odd number string select transistor.Therefore, array can be divided into two pages, by even location string ( string 0,2..., M-1) formed page or leaf 0 and by odd location string ( string 1,3..., M) formed page or leaf 1.
Word line is connected to the control grid of each unit strings respectively and selects grid, and selection wire 0 (SEL 0) can be connected to the even number string select transistor of even location string.When selection wire 0 (SEL 0) activated, the even number string select transistor can be switched on, and can be chosen to by the formed page or leaf 0 of even location string.Selection wire 1 (SEL 1) can be connected to the odd number string select transistor of odd location string, and when selection wire 1 (SEL 1) activated, the odd number string select transistor can be switched on, and can be chosen to by the formed page or leaf 1 of odd location string.
Fig. 3 B implements illustration for another has four depletion-mode transistors to form with two serializer circuits of non-volatile two bit memories, as shown in the figure: the first depletion-mode transistor arranged perpendicular is between the first even number string select transistor and selection grid 0, and horizontal arrangement is on the alignment identical with the first odd number string select transistor; The second depletion-mode transistor arranged perpendicular is between the second even number string select transistor and bit line 1, and horizontal arrangement is on the alignment identical with the second odd number string select transistor; The 3rd depletion-mode transistor arranged perpendicular is between the first odd number string select transistor and bit line 0, and horizontal arrangement is on the alignment identical with the first even number string select transistor; The 4th depletion-mode transistor arranged perpendicular is between the selection grid N+1 and the second odd number string select transistor, and horizontal arrangement is on the alignment identical with the second even number string select transistor.The depletion-mode transistor can help the manufacture process of memory cell, but because of it is a permanent conduction, so it does not influence the running of memory basically.
Fig. 4 be one be disclosed in erase, sequencing and reading in the memory cell process, bit line, word line, control grid, select grid and other service voltage signal table.In the process of erasing,, electronics can be expelled to P trap layer from the electric charge accumulation layer in the voltage difference of controlling grid and substrate P trap interlayer, and set up an electric field according to the F-N tunneling effect.The word line that is connected in the control grid can be set to low-voltage as 0V, and the P trap layer of substrate can be set to the high voltage as 12V; The grid of even number string select transistor and odd number string select transistor can be set to the low-voltage as 0V, uses to make bit line and memory cell not conducting mutually.The grid oxic horizon damage that is caused for avoiding voltage to break through is selected grid can be set to about 5V and is reduced the voltage difference of selecting grid and substrate P trap interlayer.In another embodiment, be connected in the P trap layer that the word line of control grid can be set to pact-5V and substrate and can be set to about 7V, forming the voltage difference of 12V, and the selection grid can be set at about 0V to avoid the grid oxic horizon damage.
Be the programmed memory unit, the selection grid that is positioned at cell stack one side can select storehouse below district be converted into the function with source electrode, and be positioned at the cell stack opposite side another select grid can select storehouse below district be converted into function with drain electrode.In the process of sequencing, the electronics that flows to drain electrode from source electrode can be injected in the source side of electric charge accumulation layer, and remaines in the source side of electric charge accumulation layer.When the hot electron in the programmed process when source side is produced, this process then is called as source side and injects.For instance, be the position 0 of memory cell 1 in the sequencing unit strings 0, the grid of even number string select transistor can be set to the high voltage as 7V, and the grid of odd number string select transistor can be set to the low-voltage as 0V, uses selected cell string 0; The word line 1 that is connected in control grid 1 can be set at about 9V, to produce vertical electric field; Select grid 1 can be set at about 1.5V, can reach height and make the channel region conducting of selecting the grid below, and enough low to avoid big electric current to flow; And other all control grid and selection grid all can be set at about 7V.For in memory cell 1 the position 0 sequencing data " 0 ", the bit line 0 that is connected in source electrode can be set at about 0V, and the bit line 1 that is connected in drain electrode can be set at about 4.5V, and to produce lateral electric fields, the hot electron that then comes from source electrode can be injected in the top of the electric charge accumulation layer of memory cell 1.
Be the position 1 of memory cell 1 in the sequencing unit strings 0, the word line 1 that is connected in control grid 1 can be set at about 9V, to produce vertical electric field; Selecting grid 2 can be set at about 1.5V comes Control current to flow.For in memory cell 1 the position 1 sequencing data " 0 ", the bit line 0 that is connected in drain electrode can be set at about 4.5V, and the bit line 1 that is connected in source electrode can be set at about 0V, and to produce lateral electric fields, the hot electron that then comes from source electrode can be injected in the bottom of the electric charge accumulation layer of memory cell 1.
In process of reading, for reading the position 0 o'clock that is stored in memory cell 1 in the unit strings 0, the grid of even number string select transistor can be set at about 4.5V, and the grid of odd number string select transistor can be set at about 0V, with selected cell string 0.The word line 1 that is connected in control grid 1 can be set at about 1.5V, and the P trap layer of substrate can be set at about 0V.Bit line 0 is set at 0V, is connected to the source electrode of memory cell 1, and bit line 1 is set at 1.5V, is connected to the drain electrode of memory cell.If Charge Storage is when the upside of memory cell 1 (position 0), therefore the critical voltage of control grid 1 can change, and can be affected from the electric current that corresponding channel region flow to sensing amplifier.Therefore, no matter the side of what Charge Storage in the electric charge accumulation layer arranged, all can from the electric current of the sensing amplifier of flowing through, be detected out.
Fig. 5 A-5L discloses schematic diagrames a kind of and non-volatile two bit memory array processes, as shown in the figure: in Fig. 5 A, one monocrystalline substrate 502 has a P trap active layer 504, one thickness is 30-50 dust and to be taken as be that oxide layer 506 heat of first dielectric layer are grown up in substrate 502 tops, and oxide layer 506 has the function of grid oxic horizon or tunnel oxide; One thickness is that 60-80 dust and the silicon nitride layer 508 that is taken as to the electric charge accumulation layer are deposited on oxide layer 506 tops by LPVCD (low-pressure chemical vapor deposition); One thickness is 20-40 dust and to be taken as be that the silicon dioxide layer 510 of second dielectric layer is deposited on silicon nitride layer 508 tops; One thickness is about 1000 dusts and the polysilicon layer 512 that is taken as to the control grid is deposited on silicon dioxide layer 510 tops, and polysilicon layer 512 can be mixed by the ion of N type or P type, and N type polysilicon mixes with phosphorus usually; The tungsten silicide layer 514 that one thickness is about 300 dusts is deposited on polysilicon layer 512 tops, in order to reduce the impedance that word line connects; The silicon nitride layer 516 that one thickness is about 200 dusts is deposited on tungsten silicide layer 514 tops.In etching process subsequently, it is etched to prevent the polysilicon layer 512 in the territory, control gate polar region as the function of protective cover that silicon nitride layer 516 can provide.
In Fig. 5 B, above silicon nitride layer 516, can form a photoresist layer 518, utilize general photoetching technique with photoresist layer 518 patterning subsequently, with definition control grid layer and electric charge accumulation layer.The part that silicon nitride layer 516 comes out can utilize dry ecthing that it is etched away subsequently, and residual photoresist layer also can be removed subsequently.In Fig. 5 C; the reserve part branch of silicon nitride layer 516 provides the function as protective cover; come the tungsten silicide layer 514, polysilicon layer 512, silicon dioxide layer 510 and the silicon nitride layer 508 that form control grid layer and electric charge accumulation layer by anisotropic dry etch are carried out etching, and the cell stack 520-530 with autoregistration control grid layer and electric charge accumulation layer promptly is formed.
In Fig. 5 D, a thickness deposits part top between the oxide layer 506 at the side of cell stack and cell stack and top for about 30 dusts and the silicon nitride layer 540 that comprises bottom portion 542, side portion 544 and top layer portion 546 utilize LPCVD; One thickness is for about 150 dusts and comprise that the silicon dioxide layer 550 of bottom portion 552, side portion 554 and top layer portion 556 utilizes LPCVD to be deposited on silicon nitride layer 540 tops.In Fig. 5 E, the bottom portion 552 of silicon dioxide layer 550 and top layer portion 556 etch away by anisotropic dry etch, the bottom portion 542 of silicon nitride layer 540 and top layer portion 546 etch away by anisotropic dry etch, also etch away by anisotropic dry etch, two layers of sidewall that then are taken as silicon nitride layer 540 side portion 544 of interior layer and are taken as silicon dioxide layer 550 side portion 554 of exterior layer promptly can form.Therefore, the selection grid between cell stack can be fabricated to wideer and have less resistive.
In Fig. 5 F, at first, the oxide layer 506 of cell stack outside can be etched, subsequently thickness be about the silicon dioxide layer 560 of 140 dusts can be by the oxide layer 506 parts top of thermal oxidation between cell stack, and a thick polysilicon layer 562 is deposited into one and is higher than the height of silicon nitride layer 516 and is taken as the selection grid; In Fig. 5 G, polysilicon layer 562 can be etched back to the height that is lower than silicon nitride layer 516 tops slightly; In Fig. 5 H, utilize CMP (cmp) can be ground to tungsten silicide layer 514 downwards and a smooth end face is provided.Therefore, the privileged site of the residual fraction of silicon nitride layer 516 and polysilicon layer 562 then can be removed.
In Fig. 5 I, photoresist layer 564 can be formed at end face and can be patterned will be used as the transistorized regional exposure of depletion-mode.N type ion as arsenic can be injected into the transistorized grid of depletion-mode below channel region, to guarantee depletion-mode transistor permanent conduction; And residual photoresist layer 564 will be removed subsequently.In Fig. 5 J, originally be positioned at the oxide layer 560 of depletion-mode transistor top and even number string select transistor, the odd number string select transistor all can be removed by etching; One thickness is about the new silicon dioxide layer 566 of 200 dusts and will heat grows up and become the grid oxic horizon of depletion-mode transistor, even number string select transistor and odd number string select transistor in end face.In Fig. 5 K, the polysilicon layer that a thickness is about 1000 dusts will deposit and patterning, to become the grid of depletion-mode transistor 568,570, even number string select transistor 572 and odd number string select transistor 574.In Fig. 5 L, can be injected into as the N type ion of arsenic, to form the source electrode and the drain electrode of even number string select transistor 572 and odd number string select transistor 574.
Though the present invention discloses as above with preferred embodiment; yet it is not in order to limit the present invention; those skilled in the art can do a little change and retouching without departing from the spirit and scope of the present invention, thus protection scope of the present invention should with accompanying Claim the person of being defined be as the criterion.
Claims (12)
- One kind with the non-volatile memory cell, comprise a cell stack and two selection storehouses, all be disposed at the active area top of substrate, this is respectively selected storehouse to be disposed at a side of this cell stack respectively and respectively selects to dispose between the storehouse sidewall in this cell stack and this;Wherein, this cell stack comprises first dielectric layer that is disposed at this substrate top, the electric charge accumulation layer that is disposed at this first dielectric layer top, electric charge can be remained in the control grid that a part is come store information, is disposed at second dielectric layer of this electric charge accumulation layer top and is disposed at this second dielectric layer top; This selection storehouse comprises the 3rd dielectric layer that is disposed at this substrate top and the selection grid that is disposed at the 3rd dielectric layer top, this memory cell has first state that do not contain source electrode and drain region and can be via to this selection grid supply voltage, makes the below channel region of this selection grid be converted into second state of the source/drain function of this memory cell.
- 2. according to claim 1 and non-volatile memory cell, wherein this memory cell injects electronics by source terminal and by sequencing.
- 3. according to claim 1 and non-volatile memory cell, wherein this electric charge accumulation layer contains silicon nitride.
- 4. according to claim 1 and non-volatile memory cell, wherein the either side of this electric charge accumulation layer all can store one information.
- 5. according to claim 1 and non-volatile memory cell, wherein this selection grid contains polysilicon.
- 6. according to claim 1 and non-volatile memory cell, wherein this sidewall comprises the interior layer of silicon nitride and the exterior layer of silicon dioxide.
- One kind with the non-volatile memory cell array, comprising:A plurality of memory cells are arranged in multiple row and row, are unit strings and be connected at this each memory cell with delegation, and each end of this unit strings is connected with selecting transistor respectively; AndA plurality of bit lines are right, and this each bit line is to comprising even bitlines and odd bit lines, and this even bitlines is connected with this selection transistor that is disposed at this two adjacent units string, one end, and this odd bit lines is connected with this selection transistor that is disposed at this two adjacent units string opposite end;Wherein, this memory cell comprises a cell stack and two selection storehouses, all is disposed at the top of substrate, and this is respectively selected storehouse to be disposed at each side of this cell stack respectively and respectively selects to dispose between the storehouse sidewall in this cell stack and this; This cell stack comprises first dielectric layer that is disposed at this substrate top, the electric charge accumulation layer that is disposed at this first dielectric layer top, electric charge can be remained in the control grid that a part is come store information, is disposed at second dielectric layer of this electric charge accumulation layer top and is disposed at this second dielectric layer top; This selection storehouse comprises the 3rd dielectric layer that is disposed at this substrate top and the selection grid that is disposed at the 3rd dielectric layer top, this memory cell has first state that do not contain source electrode and drain region and can be via to this selection grid supply voltage, makes the below channel region of this selection grid be converted into second state of the source/drain function of this memory cell.
- 8. according to claim 7 and non-volatile memory cell array, wherein in carrying out programmed process, electronics can inject by source side and be injected in the part of this electric charge accumulation layer.
- 9. according to claim 7 and non-volatile memory cell array, wherein this electric charge accumulation layer contains silicon nitride.
- 10. according to claim 7 and non-volatile memory cell array, wherein the either side of this electric charge accumulation layer all can store one information.
- 11. according to claim 7 and non-volatile memory cell array, wherein this sidewall comprises the interior layer of silicon nitride and the exterior layer of silicon dioxide.
- 12. according to claim 7 and non-volatile memory cell array can also comprise a plurality of depletion-mode transistors.
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| JP5231972B2 (en) * | 2008-12-18 | 2013-07-10 | 力晶科技股▲ふん▼有限公司 | Nonvolatile semiconductor memory device |
| CN104183552B (en) * | 2013-05-23 | 2017-09-19 | 北京兆易创新科技股份有限公司 | NOR-type flash memory cell and its manufacture method |
| CN104183553B (en) * | 2013-05-23 | 2017-09-26 | 北京兆易创新科技股份有限公司 | A kind of manufacture method of NOR-type flash memory cell |
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