CN100594599C - 集成n型和p型金属栅晶体管 - Google Patents

集成n型和p型金属栅晶体管 Download PDF

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CN100594599C
CN100594599C CN200380107027A CN200380107027A CN100594599C CN 100594599 C CN100594599 C CN 100594599C CN 200380107027 A CN200380107027 A CN 200380107027A CN 200380107027 A CN200380107027 A CN 200380107027A CN 100594599 C CN100594599 C CN 100594599C
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CN1729565A (zh
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马克·多克兹
史蒂文·基廷
杰克·卡瓦莱厄斯
布赖恩·多伊尔
克里斯·巴恩斯
约翰·巴纳克
迈克尔·麦克斯威尼
贾斯廷·布拉斯克
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Intel Corp
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Abstract

至少一个p型和n型半导体器件被沉积在包含金属栅或金属合金栅的半导体晶片上。更具体地，互补金属氧化物半导体(CMOS)器件被形成在具有n型和p型金属栅的半导体晶片上。

Description

集成N型和P型金属栅晶体管
技术领域
本发明的实施方案涉及互补金属氧化物半导体(CMOS)器件的制造。更具体地说，本发明的实施方案涉及在单个CMOS器件中集成N型和P型金属栅晶体管。
背景技术
用现有技术半导体工艺制造的现有技术CMOS器件一般具有多晶硅栅结构。然而，多晶硅可能易受耗尽效应影响，而耗尽效应可能增加CMOS器件中总的栅电介质厚度。此外，随着有效的物理栅电介质厚度减小，多晶硅耗尽成比例地影响总的电介质厚度。因此，为了测算(scale)栅氧化物厚度，希望消除多晶硅耗尽。
另一方面，金属栅不像多晶硅那样容易受耗尽的影响，从很多方面来说都比多晶硅更适于形成栅结构。然而，典型的现有技术的半导体工艺没有将n型和p型金属栅合并在同一器件或集成电路中。这部分是由于开发这样的半导体工艺的复杂性和成本，所述工艺能够可靠地将不同类型的金属栅结构沉积到同一半导体器件或集成电路中。
附图说明
在附图中以示例而非限制的方式图示了本发明的实施方案，其中相同的标号代表相似的元素，在附图中：
图1图示了根据一个实施方案，晶体管在沉积ILD0后的状态。
图2图示了根据一个实施方案，晶体管在ILD0回抛(polish-back)后的状态，以露出多晶硅栅结构。
图3图示了根据一个实施方案，晶体管在选择性的n型多晶(poly)蚀刻后的状态。
图4图示了根据一个实施方案，晶体管在沉积n型金属后的状态。
图5图示了根据一个实施方案，晶体管在抛光所述n型金属后的状态。
图6图示了根据一个实施方案，晶体管在选择性地蚀刻p型多晶硅后的状态。
图7图示了根据一个实施方案，晶体管在沉积p型金属后的状态。
图8图示了根据一个实施方案，晶体管在抛光所述p型金属后的状态。
图9图示了根据一个实施方案的完成后的晶体管。
图10图示了根据一个实施方案，晶体管在可选的注入(implant)图案形成(patterning)后的状态
图11图示了晶体管在n型注入和可选的灰化(ash)后的状态。
图12图示了晶体管在第二次选择性的n型多晶硅蚀刻后的状态。
具体实施方式
这里所描述的发明的实施方案涉及半导体制造。更具体地说，所描述的发明的实施方案涉及将n型和p型金属栅晶体管集成在同一互补金属氧化物半导体(CMOS)器件或集成电路内。
为了制造可以避免栅耗尽效应的CMOS器件和集成电路，本发明的实施方案将n型和p型金属栅合并到同一CMOS器件或集成电路中。
图1图示了根据一种实施方案，在沉积了ILD0(“层间电介质”)后的、包含p型晶体管和n型晶体管的CMOS器件的横截面。在图1中，使用标准CMOS工艺技术来制造多晶硅栅晶体管105、110，以防止在多晶硅栅电极上形成硅化物。氮化物硬掩模115在硅化物生成期间用来保护栅结构，并且ILD0 120被沉积在所述结构上。
在图2中，ILD0被回抛，以露出掺杂后的多晶硅栅。ILD0抛光也去除氮化物掩模层附近的残余硅化物。在多晶硅栅205、210露出后，使用氢氧化铵蚀刻来有选择地蚀刻掉305n型多晶硅。氢氧化铵蚀刻是低温的(例如，＜40摄氏度)，使用超声处理(sonication)，并且具有大约2-29％的浓度。多晶硅蚀刻的结果如图3所示。
去除了栅电介质上的p型多晶硅后就产生了镶嵌状(damascene-like)的“沟槽”，它被n型金属405(例如Hf、Zr、Ti、Ta或Al)填充，如图4所示。可替换地，可以使用PVD(“物理气相沉积”)、CVD(“化学气相沉积”)或ALD(“原子层沉积”)，用包含n型成分的合金来填充所述沟槽。CVD和ALD可以使用有机金属或卤素前体(precursor)以及还原气氛。此外，n型金属或合金的厚度可以使得所述沟槽仅部分被填充。例如，在不同的实施方案中，n型金属或合金的厚度可以从大约50埃变化到大约1000埃。如果沟槽没有被完全填充，它们可以用容易抛光的金属，例如W(“钨”)或Al(“铝”)来填充。
n型金属被回抛，以产生n型金属栅505并且露出p型多晶硅栅510，如图5所示。
图6图示了执行了选择性的干蚀刻，以去除p型多晶硅而不去除n型金属栅后的晶体管。可以使用平行板或ECR(“电子回旋谐振”)蚀刻器和SF6(“六氟化硫”)、HBr(“溴化氢”)、HI(“碘化氢”)、Cl2(“氯”)、Ar(“氩”)和/或He(“氦”)来进行选择性的干蚀刻。可替换地，也可以使用湿蚀刻来去除p型多晶硅栅，湿蚀刻例如在或不在超声处理的条件下，在大约60-90摄氏度下以大约20-30％TMAH(“氢氧化四甲铵”)来进行。
p型金属，例如Ru(“钌”)、Pd(“钯”)、Pt(“铂”)、Co(“钴”)、Ni(“镍”)、TiAlN(“氮化铝钛(Titanium Aluminum Nitride)”)或WCN(“氮化碳钨(Tungsten CarbonNitride)”)可被用来填充由蚀刻p型多晶硅栅605产生的栅沟槽。可替换地，使用有机金属前体以及还原气氛来进行化学气相沉积或原子层沉积，可以将使用p型金属的合金沉积在沟槽中。此外，p型金属或合金的厚度可以使得沟槽仅部分被填充。图7图示了在p型金属或合金已沉积在栅沟槽710中后的晶体管。
如图8所示，p型金属或合金被回抛，以产生p型栅结构805、810，并且ILD0被再次沉积，从而为接触体(contact)层提供空间。
如图9所示，接触体903被蚀刻并沉积，产生了最终的晶体管结构。
不如上所述地使用干蚀刻来去除p型多晶硅，可以将p型多晶硅栅转换成n型，以允许用更温和的湿蚀刻来去除多晶硅，而不是用干蚀刻。例如，在p型多晶硅1010已露出后，不使用选择性的干蚀刻去除多晶硅，而是执行n型注入1015以改变所述多晶硅的掺杂，从而允许进行氢氧化铵蚀刻，如图10所示。
注入和灰化(如果需要的话)的结果如图11所示。氢氧化铵蚀刻去除了剩余的多晶硅栅结构1210，形成了图12中所示的结构。然后可以将p型金属或合金沉积在通过如上所述地去除p型多晶硅栅而留下的沟槽中。
虽然参考示意性的实施方案描述了本发明，但是这些描述不想被理解为限制性的。对本发明所属领域的技术人员显而易见的那些对示意性实施方案以及其他实施方案的不同修改都被视为落入本发明的精神和范围内。

Claims (18)

1.一种用于制造互补金属氧化物器件的方法，包括：
在半导体衬底上，在一互补金属氧化物半导体(CMOS)集成电路中形成晶体管的侧壁和电介质；
在由所述侧壁和电介质形成的沟槽内形成n型和p型晶体管的n型和p型金属栅结构，其中第一沟槽是通过对与所述n型和p型金属栅结构中的一种结构相对应的多晶硅栅结构的第一蚀刻而形成的，所述第一蚀刻基本未蚀刻与所述n型和p型金属栅结构中的另一种结构相对应的多晶硅栅结构以及位于所述第一沟槽底部的所述n型和p型金属栅结构中的所述一种结构的栅电介质。
2.如权利要求1所述的方法，还包括将第一类型的金属沉积在通过所述第一蚀刻形成的第一沟槽中，并且对与所述n型和p型金属栅结构中的所述另一种结构相对应的多晶硅栅结构执行第二蚀刻，所述第二蚀刻基本未蚀刻位于所述第二沟槽底部的所述n型和p型金属栅结构中的所述另一种结构的栅电介质。
3.如权利要求2所述的方法，还包括将第二类型的金属沉积在通过所述第二蚀刻形成的第二沟槽中，所述第二类型不同于所述第一类型金属。
4.如权利要求3所述的方法，其中所述第一和第二蚀刻是干蚀刻。
5.如权利要求3所述的方法，其中所述第一和第二蚀刻是湿蚀刻。
6.如权利要求1所述的方法，其中通过将n型材料和p型材料分别注入到所述n型和p型金属栅结构中，而形成所述n型和p型金属栅结构。
7.如权利要求3所述的方法，其中所述第一类型的金属是n型金属，并且所述第二类型的金属是p型金属。
8.如权利要求3所述的方法，其中所述第一类型的金属是p型金属，并且所述第二类型的金属是n型金属。
9.一种用于制造互补金属氧化物器件的方法，包括：
在半导体衬底上形成n型晶体管和p型晶体管，所述n型和p型晶体管分别包括n型和p型多晶硅栅，
从所述多晶硅栅的顶部去除层间电介质层；
蚀刻所述n型多晶硅栅，以形成部分地由基本垂直的横向侧壁隔离物和位于所述第一沟槽底部的栅电介质为界而成的第一沟槽；
之后将n型金属沉积到所述第一沟槽中；
去除多余的n型金属，以形成n型金属栅并且露出所述n型金属栅和所述p型多晶硅栅的顶部；
蚀刻所述p型多晶硅栅，以形成部分地由基本垂直的横向侧壁隔离物和位于所述第二沟槽底部的栅电介质为界而成的第二沟槽；
之后将p型金属沉积到所述第二沟槽中；
去除多余的p型金属，以形成p型金属栅并且露出所述n型金属栅和所述p型金属栅的顶部。
10.如权利要求9所述的方法，还包括在所述n型和p型晶体管的顶部形成所述层间电介质。
11.如权利要求10所述的方法，还包括对所述n型和p型晶体管形成源极、栅极和漏极接触体。
12.如权利要求9所述的方法，其中所述n型金属栅选自由Hf、Zr、Ti、Ta和Al组成的组。
13.如权利要求9所述的方法，其中所述p型金属栅选自由Ru、Pd、Pt、Co、Ni、TiAlN和WCN组成的组。
14.如权利要求9所述的方法，其中所述p型金属栅和所述n型金属栅至少有50埃厚，但不超过1000埃厚。
15.如权利要求9所述的方法，其中蚀刻所述n型和p型多晶硅栅是氢氧化铵蚀刻。
16.如权利要求9所述的方法，其中蚀刻所述n型和p型多晶硅栅是通过使用湿蚀刻来完成的。
17.如权利要求9所述的方法，其中在所述n型金属已被沉积到所述第一沟槽中后，通过注入n型材料来掺杂所述n型金属栅。
18.如权利要求9所述的方法，其中在所述p型金属已被沉积到所述第二沟槽中后，通过用p型材料注入所述金属栅来掺杂所述p型金属栅。
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Families Citing this family (76)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858483B2 (en) * 2002-12-20 2005-02-22 Intel Corporation Integrating n-type and p-type metal gate transistors
US7030430B2 (en) 2003-08-15 2006-04-18 Intel Corporation Transition metal alloys for use as a gate electrode and devices incorporating these alloys
US7217611B2 (en) * 2003-12-29 2007-05-15 Intel Corporation Methods for integrating replacement metal gate structures
US7153734B2 (en) * 2003-12-29 2006-12-26 Intel Corporation CMOS device with metal and silicide gate electrodes and a method for making it
US7247578B2 (en) * 2003-12-30 2007-07-24 Intel Corporation Method of varying etch selectivities of a film
JP2005217176A (ja) * 2004-01-29 2005-08-11 Tokyo Electron Ltd 半導体装置および積層膜の形成方法
US7226842B2 (en) * 2004-02-17 2007-06-05 Intel Corporation Fabricating strained channel epitaxial source/drain transistors
US7153784B2 (en) * 2004-04-20 2006-12-26 Intel Corporation Method for making a semiconductor device having a high-k gate dielectric layer and a metal gate electrode
US7060568B2 (en) * 2004-06-30 2006-06-13 Intel Corporation Using different gate dielectrics with NMOS and PMOS transistors of a complementary metal oxide semiconductor integrated circuit
US7279756B2 (en) * 2004-07-21 2007-10-09 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device with high-k gate dielectric and quasi-metal gate, and method of forming thereof
US20060065627A1 (en) * 2004-09-29 2006-03-30 James Clarke Processing electronic devices using a combination of supercritical fluid and sonic energy
US7902058B2 (en) * 2004-09-29 2011-03-08 Intel Corporation Inducing strain in the channels of metal gate transistors
US7332407B2 (en) * 2004-12-23 2008-02-19 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for a semiconductor device with a high-k gate dielectric
US20060220090A1 (en) * 2005-03-23 2006-10-05 Intel Corporation Semiconductor device with a high-k gate dielectric and a metal gate electrode
US7563701B2 (en) * 2005-03-31 2009-07-21 Intel Corporation Self-aligned contacts for transistors
JP2006344836A (ja) * 2005-06-09 2006-12-21 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
US7449756B2 (en) * 2005-06-13 2008-11-11 Intel Corporation Semiconductor device with a high-k gate dielectric and a metal gate electrode
US7501336B2 (en) * 2005-06-21 2009-03-10 Intel Corporation Metal gate device with reduced oxidation of a high-k gate dielectric
KR100688555B1 (ko) * 2005-06-30 2007-03-02 삼성전자주식회사 Ｍｏｓ트랜지스터를 구비하는 반도체 소자 및 그 제조 방법
KR100666917B1 (ko) 2005-12-02 2007-01-10 삼성전자주식회사 텅스텐 탄소 질화막을 포함하는 반도체 장치의 제조 방법.
US8455088B2 (en) * 2005-12-23 2013-06-04 Boston Scientific Scimed, Inc. Spun nanofiber, medical devices, and methods
US7226831B1 (en) 2005-12-27 2007-06-05 Intel Corporation Device with scavenging spacer layer
US7579282B2 (en) * 2006-01-13 2009-08-25 Freescale Semiconductor, Inc. Method for removing metal foot during high-k dielectric/metal gate etching
US20070262399A1 (en) * 2006-05-10 2007-11-15 Gilbert Dewey Sealing spacer to reduce or eliminate lateral oxidation of a high-k gate dielectric
US7456068B2 (en) * 2006-06-08 2008-11-25 Intel Corporation Forming ultra-shallow junctions
US7544594B2 (en) * 2006-06-28 2009-06-09 Intel Corporation Method of forming a transistor having gate protection and transistor formed according to the method
US7517746B2 (en) * 2007-04-24 2009-04-14 United Microelectronics Corp. Metal oxide semiconductor transistor with Y shape metal gate and fabricating method thereof
US7585716B2 (en) * 2007-06-27 2009-09-08 International Business Machines Corporation High-k/metal gate MOSFET with reduced parasitic capacitance
US7776680B2 (en) * 2008-01-03 2010-08-17 International Business Machines Corporation Complementary metal oxide semiconductor device with an electroplated metal replacement gate
US7955909B2 (en) * 2008-03-28 2011-06-07 International Business Machines Corporation Strained ultra-thin SOI transistor formed by replacement gate
US7800166B2 (en) * 2008-05-30 2010-09-21 Intel Corporation Recessed channel array transistor (RCAT) structures and method of formation
US8058119B2 (en) * 2008-08-27 2011-11-15 Taiwan Semiconductor Manufacturing Company, Ltd. Device scheme of HKMG gate-last process
US20100102393A1 (en) * 2008-10-29 2010-04-29 Chartered Semiconductor Manufacturing, Ltd. Metal gate transistors
US7915127B2 (en) * 2009-07-27 2011-03-29 United Microelectronics Corp. Manufacturing method of semiconductor device
DE102009046245B4 (de) * 2009-10-30 2016-08-04 Globalfoundries Dresden Module One Limited Liability Company & Co. Kg Herstellung von Metallgateelektrodenstrukturen mit einer separaten Abtragung von Platzhaltermaterialien in Transistoren unterschiedlicher Leitfähigkeitsart
US8039908B2 (en) * 2009-11-11 2011-10-18 International Business Machines Corporation Damascene gate having protected shorting regions
CN102064175B (zh) * 2009-11-11 2013-05-22 中国科学院微电子研究所 半导体结构及其制造方法
US20110147837A1 (en) * 2009-12-23 2011-06-23 Hafez Walid M Dual work function gate structures
CN102376572A (zh) * 2010-08-10 2012-03-14 中芯国际集成电路制造(上海)有限公司 制作半导体器件的方法
CN103119693B (zh) 2010-08-20 2016-05-04 三菱瓦斯化学株式会社 晶体管的制造方法
EP2613345A4 (en) 2010-08-31 2015-03-18 Mitsubishi Gas Chemical Co SILICON ETCHING AGENT AND PROCESS FOR PRODUCING TRANSISTORS USING THE SAME
EP2618367B1 (en) 2010-09-17 2016-10-19 Mitsubishi Gas Chemical Company, Inc. Silicon etching fluid and method for producing transistor using same
CN102468221B (zh) * 2010-11-11 2014-10-22 中国科学院微电子研究所 采用后栅工艺制备cmos器件中接触孔的方法
US20120135590A1 (en) * 2010-11-30 2012-05-31 Advanced Technology Materials, Inc. Silicon removal from surfaces and method of forming high k metal gate structures using same
US8574990B2 (en) 2011-02-24 2013-11-05 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gate
US8802524B2 (en) 2011-03-22 2014-08-12 United Microelectronics Corp. Method of manufacturing semiconductor device having metal gates
US8704294B2 (en) 2011-06-13 2014-04-22 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US8486790B2 (en) 2011-07-18 2013-07-16 United Microelectronics Corp. Manufacturing method for metal gate
US9070784B2 (en) 2011-07-22 2015-06-30 Taiwan Semiconductor Manufacturing Company, Ltd. Metal gate structure of a CMOS semiconductor device and method of forming the same
US8477006B2 (en) 2011-08-30 2013-07-02 United Microelectronics Corp. Resistor and manufacturing method thereof
CN102983097B (zh) * 2011-09-05 2015-02-18 中芯国际集成电路制造(上海)有限公司 制作金属栅极的金属塞方法
US8357978B1 (en) * 2011-09-12 2013-01-22 Globalfoundries Inc. Methods of forming semiconductor devices with replacement gate structures
US8765588B2 (en) 2011-09-28 2014-07-01 United Microelectronics Corp. Semiconductor process
US8709930B2 (en) 2011-11-25 2014-04-29 United Microelectronics Corp. Semiconductor process
DE112011105926T5 (de) 2011-12-09 2014-09-18 Intel Corporation Belastungskompensation in Transistoren
US8546212B2 (en) 2011-12-21 2013-10-01 United Microelectronics Corp. Semiconductor device and fabricating method thereof
US8860181B2 (en) 2012-03-07 2014-10-14 United Microelectronics Corp. Thin film resistor structure
US8951855B2 (en) 2012-04-24 2015-02-10 United Microelectronics Corp. Manufacturing method for semiconductor device having metal gate
US8987080B2 (en) 2012-04-26 2015-03-24 Applied Materials, Inc. Methods for manufacturing metal gates
CN103545258B (zh) * 2012-07-13 2017-03-01 中芯国际集成电路制造(上海)有限公司 Cmos晶体管及其形成方法
CN103545184B (zh) * 2012-07-13 2017-03-01 中芯国际集成电路制造(上海)有限公司 金属栅极、其形成方法及cmos晶体管
US9054172B2 (en) 2012-12-05 2015-06-09 United Microelectrnics Corp. Semiconductor structure having contact plug and method of making the same
US8735269B1 (en) 2013-01-15 2014-05-27 United Microelectronics Corp. Method for forming semiconductor structure having TiN layer
US9129985B2 (en) 2013-03-05 2015-09-08 United Microelectronics Corp. Semiconductor device having metal gate and manufacturing method thereof
US9337190B2 (en) 2013-03-12 2016-05-10 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor device including dummy isolation gate structure and method of fabricating thereof
US9184254B2 (en) 2013-05-02 2015-11-10 United Microelectronics Corporation Field-effect transistor and fabricating method thereof
US9159798B2 (en) 2013-05-03 2015-10-13 United Microelectronics Corp. Replacement gate process and device manufactured using the same
US9196542B2 (en) 2013-05-22 2015-11-24 United Microelectronics Corp. Method for manufacturing semiconductor devices
US8921947B1 (en) 2013-06-10 2014-12-30 United Microelectronics Corp. Multi-metal gate semiconductor device having triple diameter metal opening
US9196546B2 (en) 2013-09-13 2015-11-24 United Microelectronics Corp. Metal gate transistor
CN106486373B (zh) * 2015-08-28 2020-06-09 中芯国际集成电路制造(上海)有限公司 Mos晶体管及其形成方法
TWI662687B (zh) * 2017-04-06 2019-06-11 Powerchip Technology Corporation 半導體裝置及其製造方法
US10672783B2 (en) 2017-08-30 2020-06-02 Taiwan Semiconductor Manufacturing Co., Ltd. Integrated circuit and method for manufacturing the same
US11244866B2 (en) * 2020-02-26 2022-02-08 Taiwan Semiconductor Manufacturing Co., Ltd. Low dimensional material device and method
US11211471B1 (en) 2020-09-10 2021-12-28 United Microelectronics Corp. Method of manufacturing a semiconductor device
US20230154912A1 (en) * 2021-11-17 2023-05-18 Taiwan Semiconductor Manufacturing Co.,Ltd. Heterogenous Integration Scheme for III-V/Si and Si CMOS Integrated Circuits

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6261887B1 (en) * 1997-08-28 2001-07-17 Texas Instruments Incorporated Transistors with independently formed gate structures and method
US6107126A (en) * 1998-01-26 2000-08-22 Texas Instruments-Acer Incorporated Method to form different threshold NMOSFETS for read only memory devices
US6049114A (en) * 1998-07-20 2000-04-11 Motorola, Inc. Semiconductor device having a metal containing layer overlying a gate dielectric
GB2358737A (en) * 1999-03-01 2001-08-01 Nec Corp Methods for manufacturing a complimentary integrated circuit
US6255698B1 (en) 1999-04-28 2001-07-03 Advanced Micro Devices, Inc. Separately optimized gate structures for n-channel and p-channel transistors in an integrated circuit
JP4237332B2 (ja) * 1999-04-30 2009-03-11 株式会社東芝 半導体装置の製造方法
US6093661A (en) * 1999-08-30 2000-07-25 Micron Technology, Inc. Integrated circuitry and semiconductor processing method of forming field effect transistors
US6825528B2 (en) * 2000-01-07 2004-11-30 Sharp Kabushiki Kaisha Semiconductor device, method of manufacture thereof, and information processing device
JP2001284466A (ja) * 2000-03-29 2001-10-12 Matsushita Electric Ind Co Ltd 半導体装置及びその製造方法
JP2001308318A (ja) * 2000-04-19 2001-11-02 Mitsubishi Electric Corp 半導体装置の製造方法及び半導体装置
TW466606B (en) * 2000-04-20 2001-12-01 United Microelectronics Corp Manufacturing method for dual metal gate electrode
US6204137B1 (en) * 2000-04-24 2001-03-20 Chartered Semiconductor Manufacturing, Ltd. Method to form transistors and local interconnects using a silicon nitride dummy gate technique
US20020058734A1 (en) * 2000-09-01 2002-05-16 Harlan C. Wayne Asphalt emulsion
JP2002198441A (ja) * 2000-11-16 2002-07-12 Hynix Semiconductor Inc 半導体素子のデュアル金属ゲート形成方法
KR100387259B1 (ko) * 2000-12-29 2003-06-12 주식회사 하이닉스반도체 반도체 소자의 제조 방법
US6410376B1 (en) * 2001-03-02 2002-06-25 Chartered Semiconductor Manufacturing Ltd. Method to fabricate dual-metal CMOS transistors for sub-0.1 μm ULSI integration
US6365450B1 (en) 2001-03-15 2002-04-02 Advanced Micro Devices, Inc. Fabrication of P-channel field effect transistor with minimized degradation of metal oxide gate
US6642131B2 (en) * 2001-06-21 2003-11-04 Matsushita Electric Industrial Co., Ltd. Method of forming a silicon-containing metal-oxide gate dielectric by depositing a high dielectric constant film on a silicon substrate and diffusing silicon from the substrate into the high dielectric constant film
JP4499967B2 (ja) * 2001-09-18 2010-07-14 セイコーインスツル株式会社 半導体集積回路の製造方法
US6458695B1 (en) * 2001-10-18 2002-10-01 Chartered Semiconductor Manufacturing Ltd. Methods to form dual metal gates by incorporating metals and their conductive oxides
US6667246B2 (en) * 2001-12-04 2003-12-23 Matsushita Electric Industrial Co., Ltd. Wet-etching method and method for manufacturing semiconductor device
US6620664B2 (en) * 2002-02-07 2003-09-16 Sharp Laboratories Of America, Inc. Silicon-germanium MOSFET with deposited gate dielectric and metal gate electrode and method for making the same
US6858483B2 (en) * 2002-12-20 2005-02-22 Intel Corporation Integrating n-type and p-type metal gate transistors

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