CN101000891A - 可编程电阻随机存取存储器及其制造方法 - Google Patents

可编程电阻随机存取存储器及其制造方法 Download PDF

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CN101000891A
CN101000891A CNA2007100018113A CN200710001811A CN101000891A CN 101000891 A CN101000891 A CN 101000891A CN A2007100018113 A CNA2007100018113 A CN A2007100018113A CN 200710001811 A CN200710001811 A CN 200710001811A CN 101000891 A CN101000891 A CN 101000891A
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何家骅
赖二琨
谢光宇
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Macronix International Co Ltd
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Abstract

本发明公开可编程电阻随机存取存储器单元，其电阻根据其接触点的尺寸而定。低接触电阻的制造方法与集成电路也在本发明中进行了公开，其具有较小尺寸的接触点。

Description

可编程电阻随机存取存储器及其制造方法
相关申请的交叉引用
本申请主张于2006年1月9日提交的申请美国临时性申请的优先权日，该申请的申请号为No.60/757,368，发明名称为“Process ofResistance Random Access Memory”。
技术领域
本发明涉及集成电路非易失性存储器，并尤其涉及可编程电阻非易失性存储器，例如相变化存储器。
背景技术
非易失性存储器可以在不必持续供应电源的情况下储存数据。可编程电阻非易失性存储器，如相变化存储器即为非易失性存储器的一个示例。高电流重置脉冲将此可编程电阻非易失性存储器融化并快速冷却至非晶结构，而提高此可编程电阻非易失性存储器的电阻。另一方面，低电流设置脉冲将此可编程电阻非易失性存储器的电阻结晶化并降低。
由于所使用的电脉冲类型决定了储存在可编程电阻随机存取存储器(RAM)中的数据，且电脉冲的特征部分和可编程电阻RAM单元的电阻值相关，因此制造可编程电阻RAM单元时使其具有正确电阻值是相当重要的。
可编程电阻RAM单元的电阻值，可由缩小电接触点的体积而降低，此电接触点将可编程电阻RAM单元连接到此集成电路的其他部分。用以形成小尺寸电接触点的传统方法，依靠定义此小尺寸电接触点的平板印刷(photolithographic)掩模而形成。
因此，需要一种不依赖定义小的电接触点的过于严格的平板印刷掩模的情况下，制造用于可编程RAM的小的电接触点的方法。
发明内容
本发明的实施例包括使用自对准方法以形成集成电路，其具有非易失性存储单元。接下来的步骤包括：
形成导电行的步骤，导电行沿着各行而访问非易失性存储单元。
在导电行上形成介质层的步骤。在一实施例中，这些介质层包括多层，且其中至少两层的蚀刻选择性在各层中具有差异。
形成层间接触点的步骤，层间接触点穿透介质层以电连接至导电行。
在自对准工艺中，减少层间接触点的一部分截面的步骤。在某些实施例中，此减少工艺的实施，通过形成至少部分覆盖层间接触点的介质结构、并借着移除层间接触点处未被介质结构所覆盖的材料而实施。用以减少截面部分的实施例之一，如下进行。介质层被层间接触点所暴露，其通过移除层间接触点外的部分介质层而完成。接着形成新的介质层，其至少部分覆盖到层间接触点。被移除的仅是新介质层中覆盖到层间接触点的部分，留下的介质结构至少部分覆盖了层间接触点。移除新形成材料的实施例之一，是针对新介质层进行一段时间的湿蚀刻，其通过减少截面部分而控制层间接触点的关键尺寸。在一实施例中，此介质结构具有实质上三角形的截面。最后，通过移除层间接触点未被介质结构所覆盖的部分材料，而减少层间接触点的一部份截面。在一实施例中，通过针对层间接触点未被介质结构所覆盖的部分进行干蚀刻而减少层间接触点的截面。在一实施例中，层间接触点的关键尺寸控制在小于或等于60纳米。
非易失性存储单元的可编程电阻元件的形成步骤，是与层间接触点形成电连接。形成可编程电阻元件的示例材料包括：硫属化物(chalcogenide)、PrxCayMnO3、PxrSryMnO3、ZrOx、双元素存储化合物、TCNQ、以及PCBM。
形成导电列的步骤，这些导电列沿着各列存取非易失性存储单元，以电连接至可编程电阻元件。
某些实施例中，包括下列步骤：以额外介质结构环绕层间接触点，以填满在层间接触点与见电层间的沟槽。沟槽在缩减截面部分的步骤中形成。此额外介质结构的导热性，足够低而可降低重置(reset)电流。
本发明的其他实施例，包括具有非易失性存储单元的集成电路。此集成电路包括沿着各行存取非易失性存储单元的导电列行位于这些导电行上的介质层、位于介质层上的非易失性存储单元的可编程电阻元件、穿过这些介质层而电连接至这些导电行的层间接触点、以及沿着各列而存取非易失性存储单元以连接至可编程电阻元件的导电列。
每一层间接触点具有第一部份以及第二部分。第一部份邻近于可编程电阻元件并电连接至其中之一。在某些实施例中，第一部份的截面关键尺寸小于或等于60纳米。第二部分邻近于第一部份，并与之电连接。第二部分也电连接至导电行。第二部分的截面大于第一部份的截面。第二部分在第一部份与导电行间的截面实质上是均一的。
附图说明
图1为剖面图，其示出用以沿着各行选择特定的可编程电阻RAM单元的晶体管结构。
图2为剖面图，其示出上介质层的移除，并停止于次介质层。
图3为剖面图，其示出新介质层的形成，包括在接触点上的介质结构，其具有实质上三角形的截面。
图4为剖面图，其示出新介质层的移除，包括在接触点上的介质结构，其具有实质上三角形的截面。
图5为剖面图，其示出接触点结构未被实质上三角形介质结构所覆盖的部分的移除步骤。
图6为剖面图，示出在接触点周围的沟槽中形成介质层的步骤，此沟槽在先前移除接触点部分的步骤中所生成，此图并示出移除材料以平坦化上表面。
图7为剖面图，其示出电阻存储元件与上电极的形成。
图8为剖面图，其示出位线以及额外介质层的形成。
图9为方块图，其示出包括有非易失性可编程电阻存储单元阵列以及其他电路的集成电路
主要元件符号说明
8                 衬底
10，12            栅极
14，16，18        源极与漏极区域
20，22，24        介质层
28，30            层间接触点
32                高密度等离子体氧化物层
34，36，38，40    介质结构
42，44            小截面接触点
46，48            介质结构
50，52            可编程电阻元件
54，56            上电极
58                内介质层
60，62            通孔
64                金属位线
66                上介质层
900               存储阵列
901               行解码器
903               列解码器
902，904          存储阵列输入/输出总线
905，907          总线
911               数据输入线
915               数据输出线
950               集成电路
具体实施方式
本发明的各实施例涉及存储器的制造方法，例如使用可编程电阻随机存取存储器的非易失性内置存储器。可编程元件RAM的示范，包括电阻存储器(RRAM)、高分子存储器、以及相变化存储器(PCRAM)。可编程电阻RAM的层间接触点的顶部截面被缩减。
图1为一剖面图，其示出利用沿着行来选择特定可编程电阻RAM单元的晶体管结构。此衬底8(也可以具有n阱或p阱)具有源极与漏极区域14、16、18。栅极10、12为导电行，其用来选择存取可编程电阻RAM单元，并在衬底8中位于栅极10与12之下、介于区域14与16间、区域16与18间的对应区域中诱发产生沟道。介质层20、22、24覆盖了衬底8以及栅极10、12。层间接触点28、30物理上且电气地穿过介质层20、22、24而连接至源极与漏极区域14、18。介质层20、24的示例材料为如SiOx等的氧化物与低介电系数材料，以及其他与晶体管制造相关的介质材料。介质层20的示例性厚度为600纳米。而介质层24和28的示例性厚度范围介于100至200纳米之间。介质层22和26的示例性材料之一为氮化硅，且介质层22和26的示例性厚度为30纳米。层间接触点32、34的示例性材料为钨、未经掺杂的多晶硅、或以p或n掺杂的多晶硅(例如n+掺杂的多晶硅)。
图2为剖面图，其示出介质层的上层的移除，并停止于次介质层22。介质层24被移除，露出介质层22以及层间接触点28、30的顶部。为了移除介质层24，可使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。范一个示例使用稀释的氢氟酸(DHF)或缓冲氢氟酸(BHF)的湿蚀刻，以蚀刻二氧化硅。在介质层22与介质层24之间的蚀刻选择性的差异足够高，因而使得材料的移除会在介质层22停止。
图3为剖面图，其其示出新介质层的形成，包括在接触点之上的介质结构，其具有实质上三角形的截面。此图中沉积高密度等离子体(HDP)氧化物层32与具有实质上为三角形截面的结构34、36。氧化物层32的示例厚度范围，介于150至300纳米之间。结构34、36覆盖了层间接触点28、30。或者，接触点28、30的部分仍是未被覆盖的。
图4为一剖面图，其示出移除部分新介质层的步骤，包括位于接触点上且具有实质上三角形截面的介质结构。此步骤可使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。在一实施例中，使用含有六氟化硫(SF6)的反应性离子蚀刻，以蚀刻二氧化硅层32以及结构34、36。从结构34、36移除材料后，会使得其三角形截面的面积缩减，包括物理宽度的缩减，生成结构38、40。接触点28、30先前完全或是大部分被结构34、36所覆盖，如今则部分露出、部分被结构38、40所覆盖。或者，接触点28、30先前已经露出的部分，其面积会随着增加。接触点28、30与层32、结构34、36之间的蚀刻选择性的差异足够高，以避免接触点28，30的大幅度蚀刻。然而，层32与结构34、36同时被蚀刻。
图5为剖面图，其示出将接触点未被所剩下的实质三角形介质结构覆盖的部分移除的结果。在此步骤中，可使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。在一实施例中，使用含有六氟化硫(SF6)的反应性离子蚀刻，以针对接触点28、30进行干蚀刻。所进行的步骤中，实质上三角形的结构38、40做为硬掩模，以防止在结构38、40下的接触点28、30受到蚀刻。在接触点28、30与结构38、40之间的蚀刻选择性的差异足够高，因而可避免结构38、40的大幅度蚀刻。将蚀刻时间控制于在接触点28、30中形成适当深度，例如200纳米。接触点28、30现在则具有较小截面的对应部分42、44。
图6为截面图，其示出在接触点周围的沟槽中形成介质的结果，这些沟槽在先前移除接触点部分的步骤中所形成，接着则移除材料以形成平坦上表面。介质结构46、48沉积于移除部分接触点28、30所留下的空间中。因此，介质结构46、48环绕着接触点部分42、44。介质结构46、48的示例材料为低介电系数材料、高密度等离子体氧化物、以及使用适当的后续退火温度，例如400℃的Accuflow材料。
化学机械研磨(CMP)平坦化上表面，并将被介质结构46、48所覆盖的接触点部分42、44移除。接触点部分42、44的示例关键尺寸，为60纳米。
图7为剖面图，其示出电阻存储元件以及上电极的形成。
可编程电阻元件50、52实际上接触到接触点部分42、44，并与之形成电连接。
存储材料的实施例包括了相变化为基础的存储材料，包括以硫属化物为基础与的材料与其他材料做为电阻元件。硫属化物包括下列四元素中的任一种：氧(O)、硫(S)、硒(Se)、以及碲(Te)，形成元素周期表上第VI族的部分。硫属化物包括将硫属元素与更为正电性的元素或自由基结合而得。硫属化合物合金包括将硫属化合物与其他物质如过渡金属等结合。硫属化合物合金通常包括一个以上选自元素周期表第六栏的元素，例如锗(Ge)以及锡(Sn)。通常，硫属化合物合金包括下列元素中一个以上的复合物：锑(Sb)、镓(Ga)、铟(In)、以及银(Ag)。许多以相变化为基础的存储材料已在技术文件中进行了描述，包括下列合金：镓/锑、铟/锑、铟/硒、锑/碲、锗/碲、锗/锑/碲、铟/锑/碲、镓/硒/碲、锡/锑/碲、铟/锑/锗、银/铟/锑/碲、锗/锡/锑/碲、锗/锑/硒/碲、以及碲/锗/锑/硫。在锗/锑/碲合金家族中，可以尝试大范围的合金成分。此成分可以下列特征式表示：TeaGebSb100-(a+b)。一位研究员描述了最有用的合金为，在沉积材料中所包括的平均碲浓度远低于70％，典型地低于60％，并在一般类型的合金中的碲含量范围从最低23％至最高58％，且最佳为介于48％至58％得到碲含量。锗的浓度高于约5％，且其在材料中的平均范围从最低8％至最高30％，一般低于50％。最佳地，锗的浓度范围介于8％至40％。在此成分中所剩下的主要成分则为锑。上述百分比为原子百分比，其为所有组成元素总和为100％。(Ovshinky‘112专利，栏10～11)由另一研究者所评估的特殊合金包括Ge2Sb2Te5、GeSb2Te4、以及GeSb4Te7。(Noboru Yamada，”Potential of Ge-Sb-Te Phase-changeOptical Disks for High-Data-Rate Recording”，SPIE v.3109，pp.28-37(1997))更一般地，过渡金属如铬(Cr)、铁(Fe)、镍(Ni)、铌(Nb)、钯(Pd)、铂(Pt)、以及上述的混合物或合金，可与锗/锑/碲结合以形成相变化合金，其包括有可编程的电阻性质。可使用的存储材料的特殊范例，如Ovshinsky‘112专利中栏11-13所述，其范例在此列入参考。
相变化合金能在此单元活性通道区域内依其位置顺序在材料为一般非晶态的第一结构状态与为一般结晶固体状态的第二结构状态之间切换。这些材料至少为双稳定态的。“非晶”一词指相对较无次序的结构，其比单晶更无次序性，而带有可检测的特征，如比结晶态更高的电阻值。“结晶态”指相对较有次序的结构，其比非晶态更有次序，因此包括有可检测的特征，例如比非晶态更低的电阻值。典型地，相变化材料可电切换至完全结晶态与完全非晶态之间所有可检测的不同状态。其他受到非晶态与结晶态的改变而影响的材料特中包括，原子次序、自由电子密度、以及活化能。此材料可切换成为不同的固态、或可切换成为由两种以上固态所形成的混合物，提供从非晶态至结晶态之间的灰阶部分。此材料中的电性质也可能随之改变。
相变化合金可通过施加电脉冲而从一种相态切换至另一相态。先前观察指出，较短、较大幅度的脉冲倾向于将相变化材料的相态改变成大体为非晶态。较长、较低幅度的脉冲倾向于将相变化材料的相态改变成大体为结晶态。在较短、较大幅度脉冲中的能量够大，因此足以破坏结晶结构的键结，同时够短因此可以防止原子再次排列成结晶态。在没有不适当实验的情形下，可决定特别适用于特定相变化合金的适当脉冲量变曲线。在本文的后续部分，此相变化材料以GST代称，同时应该了解，也可使用其他类型的相变化材料。在本文中所描述的一种适用于PCRAM中的材料，为Ge2Sb2Te5。
可用于本发明其它实施例中的其它可编程的存储材料包括，掺杂N2的GST、GexSby、或其它以不同结晶态变化来决定电阻的物质；PrxCayMnO3、PrSrMnO、ZrOx、TiOx、NiOx、WOx、经掺杂的SrTiO3或其它利用电脉冲以改变电阻状态的材料；或其它使用电脉冲以改变电阻状态的物质；四氰代二甲基苯醌(7，7，8，8-tetracyanoquinodimethane，TCNQ)、甲烷富勒烯66苯基C61丁酸甲酯(methanofullerene 6，6-phenyl C61-butyric acid methyl ester，PCBM)、TCNQ-PCBM、Cu-TCNQ、Ag-TCNQ、C60-TCNQ、以其它物质掺杂的TCNQ、或任何其它聚合物材料其包括有以电脉冲而控制的双稳态或多稳态电阻态。
接着简单描述四种电阻存储材料。第一种为硫属化物材料，例如GexSbyTez，其中x∶y∶z＝2∶2∶5，或其它成分为x：0～5；y：0～5；z：0～10。以氮、硅、钛或其它元素掺杂的GeSbTe也可被使用。
一种用以形成硫属化物材料的示例方法，利用PVD溅镀或磁控管(Magnetron)溅镀方式，其反应气体为氩气、氮气、及/或氦气、压力为1mTorr至100mTorr。此沉积步骤一般在室温下进行。长宽比为1～5的准直器(collimater)可用以改良其填充性能。为了改善其填充性能，也可使用数十至数百伏特的直流偏压。另一方面，同时合并使用直流偏压以及准直器也是可行的。
可以选择性地在真空中或氮气环境中进行沉积后退火处理，以改良硫属化物材料的结晶态。此退火处理的温度典型地介于100℃至400℃，而退火时间则少于30分钟。
硫属化物材料的厚度随着单元结构的设计而定。一般而言，硫属化物的厚度大于8nm的可以具有相变化特性，使得此材料表现出至少双稳定的电阻态。
第二种适合用于本发明实施例中的存储材料为超巨磁阻(CMR)材料，例如PrxCayMnO3，其中x∶y＝0.5∶0.5，或其他成分为x：0～1；y：0～1。包括有锰氧化物的超巨磁阻材料也可被使用。
用以形成超巨磁阻材料的示例方法，利用PVD溅镀或磁电管溅镀方式，其反应气体为氩气、氮气、氧气及/或氦气、压力为1mTorr至100mTorr。此沉积步骤的温度可介于室温至600℃，视后处理条件而定。长宽比为1～5的准直器可用以改良其填充性能。为了改善其填充性能，也可使用数十至数百伏特的直流偏压。另一方面，同时合并使用直流偏压以及准直器也是可行的。可施加数十高斯至1特司拉(10,000高斯)之间的磁场，以改良其磁结晶态。
可以选择性地在真空中或氮气环境中或氧气/氮气混合环境中进行沉积后退火处理，以改良超巨磁阻材料的结晶态。此退火处理的温度典型地介于400℃至600℃，而退火时间则少于2小时。
超巨磁阻材料的厚度随着存储单元结构的设计而定。厚度介于10nm至200nm的超巨磁阻材料，可被用作为核心材料。
YBCO(YBACuO3，一种高温超导体材料)缓冲层通常被用以改良超巨磁阻材料的结晶态。此YBCO的沉积在沉积超巨磁阻材料之前进行。YBCO的厚度介于30nm至200nm。
第三种存储材料为双元素化合物，例如NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等，其中x∶y＝0.5∶0.5，或其他成分为x：0～1；y：0～1。用以形成此存储材料的示例方法，利用PVD溅镀或磁电管溅镀方式，其反应气体为氩气、氮气、氧气、及/或氦气、压力为1mTorr至100mTorr，其目标金属氧化物为如NixOy、TixOy、AlxOy、WxOy、ZnxOy、ZrxOy、CuxOy等。此沉积步骤一般在室温下进行。长宽比为1～5的准直器可用以改良其填充性能。为了改善其填充，也可使用数十至数百伏特的直流偏压。若有需要时，同时合并使用直流偏压以及准直器也是可行的。
可以选择性地在真空中或氮气环境或氧气/氮气混合环境中进行一沉积后退火处理，以改良金属氧化物内的氧原子分布。此退火处理的温度典型地介于400℃至600℃，而退火时间则少于2小时。
一种替代性的形成方法利用PVD溅镀或磁电管溅镀方式，其反应气体为氩气/氧气、氩气/氮气/氧气、纯氧、氦气/氧气、氦气/氮气/氧气等，压力为1mTorr至100mTorr，其目标金属氧化物为如Ni、Ti、Al、W、Zn、Zr、Cu等。此沉积步骤一般在室温下进行。长宽比为1～5的准直器可用以改良其填充性能。为了改善其填充，也可使用数十至数百伏特的直流偏压。若有需要时，同时合并使用直流偏压以及准直器也是可行的。
可以选择性地在真空中或氮气环境或氧气/氮气混合环境中进行沉积后退火处理，以改良金属氧化物内的氧原子分布。此退火处理的温度典型地介于400℃至600℃，而退火时间则少于2小时。
另一种形成方法，使用高温氧化系统(例如高温炉管或快速热处理(RTP))进行氧化。此温度介于200℃至700℃、以纯氧或氮气/氧气混合气体，在压力为数mTorr至一大气压下进行。进行时间可从数分钟至数小时。另一氧化方法为等离子体氧化。无线射频或直流电压源等离子体与纯氧或氩气/氧气混合气体、或氩气/氮气/氧气混合气体，在压力为1mTorr至100mTorr下进行金属表面的氧化，例如Ni、Ti、Al、W、Zn、Zr、Cu等。此氧化时间从数秒钟至数分钟。氧化温度从室温至约300℃，视等离子体氧化的程度而定。
第四种存储材料为聚合物材料，例如掺杂有铜、碳六十、银等的TCNQ，或PCBM、TCNQ混合聚合物。一种形成方法利用热蒸发、电子束蒸发、或原子束外延(MBE)系统进行蒸发。固态TCNQ以及掺杂物丸在单独室内进行共蒸发。此固态TCNQ以及掺杂物丸置于钨船或钽船或陶瓷船中。接着施加大电流或电子束，以熔化反应物，使得这些材料混合并沉积于晶圆之上。此处并未使用反应性化学物质或气体。此沉积作用在压力为10-4Torr至10-10Torr下进行。晶圆温度介于室温至200℃。
可以选择性地在真空中或氮气环境中进行沉积后退火处理，以改良聚合物材料的成分分布。此退火处理的温度典型地介于室温至300℃，而退火时间则少于1小时。
另一种用以形成一层以聚合物为基础的存储材料的技术使用旋转涂布机与经掺杂的TCNQ溶液，转速低于1000rpm。在旋转涂布之后，此晶圆静置(典型地在室温下，或低于200℃的温度)足够的时间以利固态的形成。此静置时间可介于数分钟至数天，视温度以及形成条件而定。
导电上电极54、56接触到可编程电阻元件50、52，并与之形成电连接。上电极54、56的示例材料可为单层或多层结构。单层上电极54、56具有低导热性，并且可为如氮化钛、氮化钽、镍酸镧(LaNiO3)等。多层上电极54、56为如氮化钛/铝铜、氮化钽/铜等。
最后，可编程元件50、52与导电上电极54、56所形成的堆栈被蚀刻。可编程电阻元件50、52与导电上电极54、56所形成的堆栈可由非侵入性掩模所定义，因为堆栈特征尺寸大于接触点部分42、44的关键尺寸。此步骤可使用湿蚀刻、干蚀刻、或湿蚀刻与干蚀刻的组合。举例而言，可使用如Cl2、BCl3等化合物的干蚀刻。蚀刻选择性的差异足够高，以使得氧化物层32不会被大幅蚀刻。
图8为剖面图，其示出位线以及额外介质层66的形成。内介质层58先沉积，其材料可为二氧化硅、高密度等离子体氧化物、等离子体增强氧化物等。通孔60、62先形成，以接触至上电极54、56并与之电连接。通孔60、62被填充，且金属位线64沿着各列而访问可编程电阻RAM单元。通孔60、62的材料可为钨，而金属位线64的材料可为铜铝。另一可实施的方法为全铜工艺。
图9为一集成电路的方块图，其包括有非易失性可编程电阻存储单元阵列以及其他电路。
集成电路950包括了存储阵列900，存储阵列900利用在半导体衬底上使用具有电阻元件的存储单元而实施。此存储阵列900具有如上所述的窄截面接触点。位址经由总线905而传送到列解码器903以及行解码器901。在方块906中的感测放大器以及数据输入结构，经由数据总线907而连接到列解码器903。数据经由数据输入线911而从集成电路950中的输入/输出端口、或从集成电路950的其他内部或外部来源，传送到方块906中的数据输入结构。数据经由数据输出线915而从方块906传送到集成电路950的输入/输出端口、或传送到其他位于集成电路950内部或外部的目的地。集成电路950也可包括非易失性储存(具有电阻元件)以外的功能电路(图中未示出)。
虽然本发明已参照较佳实施例加以描述，应该所了解的是，本发明并不受限于其详细描述的内容。替换方式及修改方式已在先前描述中建议，并且其他替换方式及修改方式将为本领域的技术人员可想到的。特别是，根据本发明的结构与方法，所有具有实质上相同于本发明的构件结合而实现与本发明实质上相同结果的，皆不脱离本发明的精神范畴。因此，所有这些替换方式及修改方式意欲落在本发明所附的权利要求书及其等价物所界定的范畴中。

Claims (21)

1.一种形成具有非易失性存储单元的集成电路的方法，包括：
形成多个导电行，以沿着各行访问这些非易失性存储单元；
形成介质层于这些导电行之上；
形成层间接触点，其穿越该介质层而电连接这些导电行；
在自对准工艺中，减少该层间接触点的截面部分；
形成非易失性存储单元的可编程电阻元件，以与这些层间接触点形成电连接；以及
形成导电列，以沿着各列访问这些非易失性存储单元，而与该可编程电阻元件电连接。
2.如权利要求1所述的方法，其中形成该介质层的步骤包括：
形成第一介质层于这些导电行之上；以及
形成第二介质层，其至少一部分位于该第一介质层上，其中该第一与第二介质层具有蚀刻选择性的差异。
3.如权利要求1所述的方法，其中该减少截面部分的步骤包括：
控制该层间接触点的关键尺寸，使该关键尺寸少于或等于60纳米。
4.如权利要求1所述的方法，其中该减少截面部分的步骤包括：
形成介质结构，其至少一部分覆盖该层间接触点；以及
通过移除该层间接触点中未被该介质结构所覆盖的部分，而减少该层间接触点的截面部分。
5.如权利要求1所述的方法，其中该减少截面部分的步骤包括：
至少通过移除层间接触点之外的第二介质层而完成，以至少通过这些层间接触点而外露该介质层的第一介质层；
形成第三介质层，其至少部分覆盖这些层间接触点；
仅移除该第三介质层中覆盖该层间接触点的部分，以留下至少部分覆盖这些层间接触点的介质结构；以及
通过移除这些层间接触点中、未被该介质结构覆盖的部分材料，以减少该层间接触点的截面部分。
6.如权利要求5所述的方法，其中仅该移除该第三介质层的部分的步骤包括：
针对该第三介质层的该部分进行湿蚀刻。
7.如权利要求5所述的方法，其中仅该移除该第三介质层的部分的步骤包括：
针对该第三介质层的该部分进行湿蚀刻一段时间，其中该段时间控制了这些层间接触点的该部分的尺寸，其通过该减少截面部分而实现。
8.如权利要求5所述的方法，其中该形成该第三介质层的步骤包括：
形成该介质结构以覆盖这些层间接触点，该介质结构具有实质上三角形的截面。
9.如权利要求5所述的方法，其中该减少截面部分的步骤包括：
针对这些层间接触点未被该介质结构所覆盖的部分，进行干蚀刻。
10.如权利要求1所述的方法，还包括：
以介质结构环绕这些层间接触点，以填满在这些层间接触点与这些介质层间的空隙，这些空隙从该减少截面部分步骤所形成，其中该介质结构具有导热性，其幅度够低以减少重置电流。
11.如权利要求1所述的方法，其中该形成可编程电阻元件的步骤包括：
形成可编程电阻元件，其包括下列组中的至少一种：、硫属化物、PrxCayMnO3、PrSrMnO3、ZrOx、双元素存储化合物、TCNQ、以及PCBM。
12.一种用以形成具有非易失性存储单元的集成电路的方法，包括：
形成多个导电行，以沿着各行访问这些非易失性存储单元；
形成多个介质层于这些导电行之上，包括：
形成第一介质层于这些导电行之上；以及
形成第二介质层，其至少部分位于该第一介质层上，其中该第一与第二介质层具有蚀刻选择性的差异；
形成层间接触点，其穿过这些介质层而电连接这些导电行；
在自对准工艺中减少该层间接触点的截面部分，包括：
至少通过移除层间接触点之外的第二介质层而完成，以至少通过这些层间接触点而外露该介质层的第一介质层；
形成第三介质层，其至少部分覆盖这些层间接触点；
仅移除该第三介质层中覆盖该层间接触点的部分，以留下介质结构，其至少部分覆盖这些层间接触点；以及
通过移除这些层间接触点中、未被该介质结构覆盖的部分材料，以减少该层间接触点的截面部分；
形成非易失性存储单元的可编程电阻元件，以与这些层间接触点形成电连接；以及
形成导电列，以沿着各列存取这些非易失性存储单元，而与该可编程电阻元件电连接。
13.如权利要求12所述的方法，其中该减少截面部分的步骤包括：
控制这些层间接触点的关键尺寸，使该关键尺寸少于或等于60纳米。
14.如权利要求12所述的方法，其中该仅移除该第三介质层的部分的步骤包括：
针对该第三介质层的该部分进行湿蚀刻。
15.如权利要求12所述的方法，其中该仅移除第三介质层的部分的步骤包括：
针对该第三介质层的该部分进行湿蚀刻一段时间，其中该段时间控制了这些层间接触点的该部分的尺寸，其通过该减少截面部分而达成。
16.如权利要求12所述的方法，其中该形成该第三介质层的步骤包括：
形成介质结构以覆盖这些层间接触点，该介质结构具有实质上三角形的截面。
17.如权利要求12所述的方法，其中该减少截面部分的步骤包括：
针对这些层间接触点未被该介质结构所覆盖的部分，进行干蚀刻。
18.如权利要求12所述的方法，其中该形成可编程电阻元件的步骤包括：
形成可编程电阻元件，其包括下列组中的至少一种：硫属化物、PrxCayMnO3、PrSrMnO3、ZrOx、双元素存储化合物、TCNQ、以及PCBM。
19.一种集成电路，其具有非易失性存储单元，包括：
多个导电行，其沿着各行而存取该非易失性存储单元；
多个介质层，其位于这些导电行之上；
这些非易失性存储单元的可编程电阻元件，其位于这些介质层之上；
多个层间接触点，其穿过这些介质层而电连接至这些导电行，每一该层间接触点包括：
第一部份，其邻近于并接触至这些可编程电阻元件的至少一个，该第一部份具有第一截面；以及
第二部分，其邻近于并接触至该第一部份，该第二部份电连接至这些导电行，该第二部分具有第二截面，其大于该第一截面，该第二截面在该第一部分与这些导电行之间实质上为均一的；以及
多个导电列，其沿着各列而访问该非易失性存储单元，以与这些可编程电阻元件电连接。
20.如权利要求19所述的集成电路，其中每一该层间接触点的该第一部份的该第一截面，其具有少于或等于约60纳米的关键尺寸。
21.如权利要求19所述的集成电路，其中该可编程电阻元件包括下列组中的至少一种：硫属化物、PrxCayMnO3、PrSrMnO3、ZrOx、双元素存储化合物、TCNQ、以及PCBM。
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