CN101000944B - Phase storage element and manufacturing method thereof - Google Patents
Phase storage element and manufacturing method thereof Download PDFInfo
- Publication number
- CN101000944B CN101000944B CN2006100002727A CN200610000272A CN101000944B CN 101000944 B CN101000944 B CN 101000944B CN 2006100002727 A CN2006100002727 A CN 2006100002727A CN 200610000272 A CN200610000272 A CN 200610000272A CN 101000944 B CN101000944 B CN 101000944B
- Authority
- CN
- China
- Prior art keywords
- phase change
- electrode
- layer
- pyramidal structure
- dielectric layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Abstract
The invention discloses a phase-changing storage component and it manufacturing method. In which, it etches a phase-changing layer into a cone-shaped structure and flats the dielectric layer of the phase-changing layer till the top of the cone-shaped structure to be exposed. It makes the top of the cone-shaped structure contact with the electrode of heating. In this way, it can change the contact area of the phase-changing layer and the heating electrode smaller through controlling the exposed top layer of the phase-changing layer in a very small size in order to reduce its operating current.
Description
Technical field
The present invention relates to a kind of non-volatile storage components, particularly relate to a kind of novel phase change memory and manufacture method thereof.
Background technology
Ovonics unified memory (phase change memory; PCM) be a kind of non-volatile storage component, its crystalline phase of utilizing thermal effect to change phase-transition material realizes the conversion of the resistance value of assembly.That is to say, its can be considered one higher or than low resistance state between the programmable resistance of reversible variation.
The formation of the memory cell that is used in Ovonics unified memory (cell) that at present, the phase-transition material of chalcogenide compound is general.This chalcogenide compound is for having the material of multiple solid-state phase (solid-state phase), and it can cause the transition phenomenon of thermoinduction along with temperature change: wherein, when it is in heterogeneous body state (having the atomic structure of disorderly arranging), to present high resistance, and when being in crystalline state (atomic structure), then present low-resistance value with proper alignment.At this, changing its temperature can reach by electric current or optical pulse modes such as (optical pulses) is provided.
Structurally, be that current path is become aperture with the Interface design that couples of phase-transition material, to concentrate electric current, make near the phase-transition material of aperture have high current density, and then change the phase state of chalcogenide compound.Because resistance value is the function that couples the area of interface to the current flow heats effect of phase-transition material, therefore the area that couples interface should be more little good more, and when resistance value is high more, the heating of the unitary current amount of phase-transition material will be efficient more, can reduce operating current.
In general, in Ovonics unified memory, utilize transistor (transistor), come the electric current of control flows, and put on the voltage of chalcogenide compound through novel phase change memory as choosing assembly.Therefore, for size of dwindling Ovonics unified memory and the power that reduction consumed, must reduce the required operating current of novel phase change memory.Because resistance value is the function of the contact area of interface area in the current flow heats effect of interface area, therefore in known technology, utilize the area of the interface area of dwindling current path and phase-transition material to reach the purpose that reduces operating current.
In the tradition, novel phase change memory is T type (T-shape) structure, forms the current path by phase change layer 130 between upper and lower electrode 110,120, as shown in Figure 1; At this, utilize photoetching treatment on dielectric layer 140, to form small hole, fill with metal material again, make bottom electrode 120, so the contact area between bottom electrode 120 and the phase change layer 130 can be dwindled.At this, phase-transition material (being phase change layer) and the contact area of the bottom electrode that is used for heating are subject to the ability of photoetching treatment, and fill small hole with metal material, are easy to generate the problem of step coverage rate deficiency.In addition, actually, the ability of renewal photoetching treatment also is not easy, and must carry out renewal of the equipment and staff training etc., all will expend sizable cost and manpower.
Therefore, proposed conical design, it is to use the top of the bottom electrode of taper to contact with phase change layer, dwindles contact area between the two.
With reference to figure 2, its utilization waits tropism's etching principle, multilayer conductive base material (conductivesubstrate) 121a, 121b, 121c, 121d and heating electrode 122 are etched into pyramidal structure synchronously, contact with phase change layer 130 with the heating electrode 122 that forms the awl point again, dwindle contact area whereby, shown in United States Patent (USP) 6800563B2 number.Yet, when actual fabrication, carry out etching according to the method and must take into account the different material of multilayer simultaneously, so the not good and undesirable problem of figure of the uniformity will appear in the pattern of gained after the etching.
Have again, please refer to Fig. 3, it utilizes hocketing of etching and the side direction downsizing of light group, dielectric layer 142 is etched into pyramidal structure, and then deposition heating electrode 122, can utilize the heating electrode 122 of cone tip part to contact, reach the purpose of dwindling contact area whereby, shown in United States Patent (USP) 6746892B2 number with phase change layer 130.
In addition, also develop and EDGE CONTACT formula (edge contact) novel phase change memory, as shown in Figure 4; It is that heating electrode 122 is arranged in the interlayer of trench sidewall, utilizes the thickness of heating electrode 122 to control size with the contact area of phase change layer 130.Yet this mode will cause phase-transition material in the difficulty of filling out on the hole, and then cause the loose contact of side direction contact interface, thereby form the problem of assembly uniformity and reliability aspect.In addition, this mode contacts with phase-transition material by the horizontal expansion of heating electrode, cause the current path of heating electrode long, and it has higher resistivity, therefore will cause extra power consumption.
Have again, another kind of novel phase change memory is side direction type (lateral), shown in No. the 6867425th, United States Patent (USP), with reference to figure 5, be that electrode 112,124 is arranged in the interlayer of trench sidewall equally, utilize the thickness of electrode 112,124 to control size with the contact area of phase change layer 130.Reduce operating current though can contact, and can shorten the flow through path of phase-transition material of electric current by control two interelectrode distances by side direction type, and then the power loss when reducing assembly operation.But the material of general heating electrode has higher resistivity usually, therefore is will cause the increase of dead resistance by lead as if it is served as simultaneously, and then causes extra power consumption.Have again, when two interelectrode distances are too small,, can cause the difficulty of phase-transition material on filling out the hole and sidewall contacts, produce uniformity and reliability problems though can reduce the loss of operand power.
Hence one can see that, in order to dwindle the contact area of current path and phase-transition material, the correlative study personnel in this field have worked out multiple mode, but when applying in the actual fabrication, be subject to making apparatus and/or technical capability easily and produce many problems, therefore provide multiple method of dwindling the contact area of current path and phase-transition material, make its can arrange in pairs or groups the flexibly equipment and technology of leading portion and/or subsequent treatment, and then quicken the development of this art.So, a kind of simple, manufacture method that practical feasibility is high is provided, the contact area of dwindling current path and phase-transition material is one of this field related personnel project of endeavouring to study.
Summary of the invention
The object of the present invention is to provide a kind of novel phase change memory and manufacture method thereof, solve the problem of the contact area of how to dwindle phase change layer and heating electrode in the known technology.
To achieve these goals, the invention provides a kind of manufacture method of novel phase change memory, include the following step: at first, provide first dielectric layer, and in first dielectric layer, have first electrode; On first dielectric layer and first electrode, deposit a phase change layer again; And phase change layer is etched into a pyramidal structure, and wherein the top of this pyramidal structure is at the position away from first electrode, and its bottom is at the position near first electrode, and the area of bottom is greater than the area on top; Then, deposit second dielectric layer on phase change layer; Then, planarization second dielectric layer is until the top of exposing pyramidal structure; And on the top of the pyramidal structure of exposing, forming heating electrode, the material of this heating electrode is the high value electric conducting material, forms second electrode on this heating electrode.Thus, the area that the top of phase change layer is exposed is controlled in the minimum size, can reach the purpose of the contact area of dwindling phase change layer and heating electrode, and then reduces its operating current.
At this, the top of the pyramidal structure that second dielectric layer exposes can be a plane or a pyramid.
Wherein, can utilize chemical mechanical milling method (Chemical Mechanical Polishing/Planarization; CMP) and/or return the planarization that lithographic technique (Etch back technique) is carried out second dielectric layer.
In addition, when utilizing chemical mechanical milling method to carry out the planarization of second dielectric layer, can be before deposition second dielectric layer, earlier deposition stops layer on phase change layer, control carry out chemical mechanical milling method stop opportunity.
In addition, before the sediment phase change layer, can deposit diffused barrier layer earlier, prevent that the metal material of the phase change layer and first electrode from spreading alternately.
To achieve these goals, the present invention also provides a kind of novel phase change memory, includes: first dielectric layer, first electrode, phase change layer, second dielectric layer and heating electrode.At this, first electrode is positioned at first dielectric layer; Phase change layer is positioned on first electrode, and has pyramidal structure, and wherein the top of this pyramidal structure is at the position away from first electrode, and its bottom is at the position near first electrode, and the area of bottom is greater than the area on top; Second dielectric layer is positioned on the phase change layer, and exposes the top of pyramidal structure; And heating electrode, the material of this heating electrode is the high value electric conducting material, is positioned on second dielectric layer, and contacts with the top of the pyramidal structure of exposing, and comes phase change layer is carried out the joule heating, second electrode is positioned on this heating electrode.Thus, as long as the area that the top of phase change layer is exposed is controlled in the minimum size, can reaches the purpose of the contact area of dwindling phase change layer and heating electrode, and then reduce its operating current.
At this, the top of the pyramidal structure that second dielectric layer exposes can be plane or pyramid.
In addition, on heating electrode, second electrode can be set, transmit operating current.
Have again, between the phase change layer and first electrode, have diffused barrier layer, prevent that the metal material of the phase change layer and first electrode from spreading alternately.
In addition, can have the layer of stopping between phase change layer and heating electrode, be used in manufacture process, when utilizing chemical mechanical milling method to carry out the planarization of second dielectric layer, what chemical mechanical milling method was carried out in control stops opportunity.
Describe the present invention below in conjunction with the drawings and specific embodiments, but not as a limitation of the invention.
Description of drawings
Fig. 1 is the profile of known novel phase change memory;
Fig. 2 is the profile of another known novel phase change memory;
Fig. 3 is the profile of another known novel phase change memory;
Fig. 4 is the profile of another known novel phase change memory;
Fig. 5 is the profile of another known novel phase change memory;
Fig. 6 is the profile of the novel phase change memory of first embodiment of the invention;
Fig. 7 is the profile of the novel phase change memory of second embodiment of the invention;
Fig. 8 is the profile of the novel phase change memory of third embodiment of the invention;
Fig. 9 is the profile of the novel phase change memory of fourth embodiment of the invention;
Figure 10 is the profile of the novel phase change memory of fifth embodiment of the invention;
Figure 11 is the profile of the novel phase change memory of sixth embodiment of the invention;
Figure 12 A is in the manufacture method of the present invention, the profile of an embodiment of first dielectric layer that provides;
Figure 12 B is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 12 A;
Figure 12 C is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 12 B;
Figure 12 D is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 12 C;
Figure 12 E is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 12 D;
Figure 12 F is a manufacture method of the present invention, the profile of another embodiment of the structural fabrication schedule that continues shown in Figure 12 D;
Figure 13 A, 13B are the thin portion flow chart of an embodiment of the structure shown in formation Figure 12 C;
Figure 14 A, 14B, 14C are the thin portion flow chart that forms an embodiment of structure shown in Figure 6;
Figure 15 A, 15B, 15C are the thin portion flow chart that forms an embodiment of structure shown in Figure 7;
Figure 16 A, 16B, 16C are the thin portion flow chart that forms an embodiment of structure shown in Figure 8;
Figure 17 A, 17B, 17C are the thin portion flow chart that forms an embodiment of structure shown in Figure 9;
Figure 18 A is a manufacture method of the present invention, the profile of another embodiment of the structural fabrication schedule that continues shown in Figure 12 A;
Figure 18 B is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 18 A;
Figure 18 C is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 18 B;
Figure 18 D is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 18 C;
Figure 18 E is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 18 D;
Figure 18 F is a manufacture method of the present invention, the profile of another embodiment of the structural fabrication schedule that continues shown in Figure 18 D;
Figure 19 is the profile of the novel phase change memory of the seventh embodiment of the present invention;
Figure 20 is the profile of the novel phase change memory of the eighth embodiment of the present invention;
Figure 21 A is a manufacture method of the present invention, the profile of another embodiment of the structural fabrication schedule that continues shown in Figure 12 C;
Figure 21 B is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 21 A;
Figure 21 C is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 21 B;
Figure 21 D is the profile of the novel phase change memory of the ninth embodiment of the present invention;
Figure 21 E is the profile of the novel phase change memory of the tenth embodiment of the present invention;
Figure 22 A is a manufacture method of the present invention, the profile of another embodiment of the structural fabrication schedule that continues shown in Figure 18 C;
Figure 22 B is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 22 A;
Figure 22 C is a manufacture method of the present invention, the profile of an embodiment of the structural fabrication schedule that continues shown in Figure 22 B;
Figure 22 D is the profile of the novel phase change memory of the 11st embodiment of the present invention; And
Figure 22 E is the profile of the novel phase change memory of the 12nd embodiment of the present invention.
Wherein, Reference numeral:
110 top electrodes
112 electrodes
120 bottom electrodes
The 121a conductive base
The 121b conductive base
The 121c conductive base
The 121d conductive base
122 heating electrodes
124 electrodes
130 phase change layers
140 dielectric layers
142 dielectric layers
210 first electrodes
220 second electrodes
222 heating electrodes
230 phase change layers
232 diffused barrier layers
240 first dielectric layers
242 second dielectric layers
250 photoresist patterns
260 stop layer
Embodiment
Please refer to Fig. 6 and Fig. 7, be the novel phase change memory of the present invention first and second embodiment; This novel phase change memory has first electrode 210, phase change layer 230, heating electrode 222, first dielectric layer 240 and second dielectric layer 242.
Wherein, the material of first electrode can be conduction favorable conductive materials such as aluminium (Al), tungsten (W), molybdenum (Mo), titanium (Ti), copper (Cu).And the material of first and second dielectric layers can be silicon dioxide (SiO
2), silicon nitride (Si
3N
4) wait dielectric material.The phase change layer material can be chalcogenide compound (chalcogenide), for example: germanium antimony tellurium alloy (GeSbTe alloy), germanium antimony tin tellurium alloy (GeSbSnTe alloy), iridium germanium antimony tellurium alloy phase-transition materials such as (IrGeSbTe alloys).The material of heating electrode can be the electric conducting material of titanium (Ti), tantalum (Ta), titanium nitride (TiN), tantalum nitride (TaN), nitrogen titanium aluminide (TiAlNx), titanium carbonitride (TiCNx), tungsten tantalum (TaW), tungsten titanium (TiW), tantalum oxide (TaO), polysilicon (poly-Si), tantalum silicon oxide (TaSiO), carbon (C), carbon silicide (SiC), germanium nitride high value such as (GeN).
In addition, second electrode 220 can be set on heating electrode 222, transmit operating current, as Fig. 8, shown in Figure 9.At this, the material of second electrode can be conduction favorable conductive materials such as aluminium, tungsten, molybdenum, titanium, copper.
Have again, between the phase change layer 230 and first electrode 210, have diffused barrier layer 232, spread alternately with the metal material that prevents the phase change layer 230 and first electrode 210, as Figure 10, shown in Figure 11.At this, the material of diffused barrier layer can be the material of good thermal stabilities such as titanium nitride, tantalum nitride, titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tungsten titanium.
At this, can utilize following manufacture method to form novel phase change memory of the present invention.
At first, provide first dielectric layer 240, wherein have first electrode 210, shown in Figure 12 A.
Then, sediment phase change layer 230 on first dielectric layer 240 and first electrode 210 is shown in Figure 12 B.
Then, phase change layer 230 is etched into taper (tapered) structure, shown in Figure 12 C.At this, photoresist pattern 250 can be formed, as shown in FIG. 13A earlier on formed phase change layer 230; Then, shield as etching with photoresist pattern 250, do not cover the zone of the phase change layer 230 of photoresist pattern 250 Deng tropism's etching, so that phase change layer 230 formation bottom (being the position of nearly first electrode 210) areas are big, the upper end position of first electrode 210 (promptly away from) pyramidal structure that area is little is shown in Figure 13 B; Again photoresist pattern 250 is removed at last, can obtain the structure shown in Figure 12 C.At this, can select specific etching shielding and etching parameters, make vertical and horizontal etch rate phase change layer can be cut down tapered structure.
Deposit second dielectric layer 242 more in the above, shown in Figure 12 D.
Then, planarization second dielectric layer 242, until the top of exposing pyramidal structure (being phase change layer 230), shown in Figure 12 E, Figure 12 F, this exposed portions serve is and heating electrode 222 contacted positions.Wherein, the part that this phase change layer 230 exposes can be plane (shown in Figure 12 E), also can be pyramid (shown in Figure 12 F); Thus, as long as plane sizes or pyramid size that the top of phase change layer 230 is exposed are controlled in the minimum size, can reach the purpose of the contact area of dwindling phase change layer 230 and heating electrode 222, and then reduce its operating current.At this, can utilize chemical mechanical milling method and/or time lithographic technique to carry out the planarization of second dielectric layer.
At last, on phase change layer 230, form heating electrode 222, come whereby phase change layer is carried out the joule heating, can obtain novel phase change memory as shown in Figure 6 and Figure 7.At this, heating electrode 222 can be formed, earlier shown in Figure 14 A and Figure 15 A on phase change layer 230; Then, on heating electrode 222, form photoresist pattern 250, shown in Figure 14 B and Figure 15 B; Then, as the etching shielding, etching does not cover the heating electrode 222 in the zone of photoresist pattern 250, until manifesting second dielectric layer 242, shown in Figure 14 C and Figure 15 C with photoresist pattern 250; Again photoresist pattern 250 is removed at last, can obtain structure as shown in Figure 6 and Figure 7 respectively.
At this, the manufacture method of this novel phase change memory can progressively be carried out on base material, or makes the formed CMOS (Complementary Metal Oxide Semiconductor) of flow process (Complementary Metal-OxideSemiconductor at leading portion; CMOS) progressively carry out on.
In addition, on phase change layer 230, also can be formed with the heating electrode 222 and second electrode 220 in regular turn, to obtain as Fig. 8 and novel phase change memory shown in Figure 9.At this, can on phase change layer 230, form the heating electrode 222 and second electrode 220 earlier in regular turn, shown in Figure 16 A and Figure 17 A; Then, on second electrode 220, form photoresist pattern 250, shown in Figure 16 B and Figure 17 B; Then, as the etching shielding, etching does not cover the heating electrode 222 in the zone of photoresist pattern 250, until manifesting second dielectric layer 242, shown in Figure 16 C and Figure 17 C with photoresist pattern 250; Again photoresist pattern 250 is removed at last,, can obtain respectively as Fig. 8 and structure shown in Figure 9.
In addition, before the sediment phase change layer, can deposit diffused barrier layer earlier, spread alternately with the metal material that prevents the phase change layer and first electrode.At this, also be that first dielectric layer 240 is provided earlier, wherein have first electrode 210, shown in Figure 12 A; Then on first dielectric layer 240 and first electrode 210, deposit diffused barrier layer 232, shown in Figure 18 A; And then sediment phase change layer 230 is on diffused barrier layer 232, shown in Figure 18 B; Then etching phase change layer 230 and diffused barrier layer 232 until manifesting first dielectric layer 240, and are etched into pyramidal structure with phase change layer 230, shown in Figure 18 C; Deposit second dielectric layer 242 more thereon, shown in Figure 18 D; Then, planarization second dielectric layer 242 is until the top of exposing pyramidal structure (being phase change layer 230), shown in Figure 18 E, Figure 18 F; At last, on phase change layer 230, form heating electrode 222, come phase change layer is carried out the joule heating, can obtain novel phase change memory as shown in Figure 10 and Figure 11.Wherein, the part that this phase change layer 230 exposes can be plane (shown in Figure 18 E), also can be pyramid (shown in Figure 18 F); Thus, as long as plane sizes or pyramid size that the top of phase change layer 230 is exposed are controlled in the minimum size, can dwindle the contact area of phase change layer 230 and heating electrode 222, and then reduce its operating current.At this, can utilize chemical mechanical milling method and/or time lithographic technique to carry out the planarization of second dielectric layer.
In addition, on phase change layer 230, also can be formed with the heating electrode 222 and second electrode 220 in regular turn, as Figure 19 and shown in Figure 20.
In addition, when utilizing chemical mechanical milling method to carry out the planarization of second dielectric layer 242, can be before deposition second dielectric layer 242, deposition stops layer 260 on phase change layer 230 earlier, stop opportunity with what chemical mechanical milling method was carried out in control, shown in Figure 21 A and Figure 22 A.Then, stopping deposition second dielectric layer 242 on the layer 260, shown in Figure 21 B and Figure 22 B; Then, with chemical mechanical milling method planarization second dielectric layer 242, until the top of exposing pyramidal structure (being phase change layer 230), shown in Figure 21 C and Figure 22 C; At last, on phase change layer 230, form heating electrode 222, come phase change layer is carried out the joule heating, shown in Figure 21 D and Figure 22 D.At this, the part that this phase change layer 230 exposes can be plane (shown in Figure 21 C and Figure 22 C); Thus, as long as the plane sizes that the top of phase change layer 230 is exposed is controlled in the minimum size, can dwindles the contact area of phase change layer 230 and heating electrode 222, and then reduce its operating current.
In addition, on phase change layer 230, also can be formed with the heating electrode 222 and second electrode 220 in regular turn, shown in Figure 21 E and Figure 22 E.At this, the material that stops layer can be silicon nitride (Si
3N
4) wait dielectric material.
Certainly; the present invention also can have other various embodiments; under the situation that does not deviate from spirit of the present invention and essence thereof; those of ordinary skill in the art can make various corresponding changes and distortion according to the present invention, but these corresponding changes and distortion all should belong to the protection range of the appended claim of the present invention.
Claims (10)
1. the manufacture method of a novel phase change memory is characterized in that, includes the following step:
First dielectric layer is provided, and in this first dielectric layer, has first electrode;
Sediment phase change layer on this first dielectric layer and this first electrode;
This phase change layer is etched into pyramidal structure, and wherein the top of this pyramidal structure is away from the position of this first electrode, and the bottom of this pyramidal structure is near the position of this first electrode, and the area of the bottom of this pyramidal structure is greater than the area on the top of this pyramidal structure;
Deposition stops layer on this phase change layer;
Depositing second dielectric layer stops on the layer in this;
This second dielectric layer of planarization is until the top of exposing this pyramidal structure; And
Form heating electrode on this top of this pyramidal structure of exposing, and form second electrode on this heating electrode, wherein the material of this heating electrode is the high value electric conducting material;
Described high value electric conducting material comprises: titanium, tantalum, titanium nitride, tantalum nitride, nitrogen titanium aluminide, titanium carbonitride, tungsten tantalum, tungsten titanium, tantalum oxide, polysilicon, tantalum silicon oxide, carbon, carbon silicide, germanium nitride.
2. the manufacture method of novel phase change memory according to claim 1 is characterized in that, this is etched into the step of a pyramidal structure with this phase change layer, also includes the following step:
On this phase change layer, form the photoresist pattern;
Shield as etching with this photoresist pattern, wait tropism's etching not cover the zone of this phase change layer of this photoresist pattern, make this phase change layer form this pyramidal structure; And
Remove this photoresist pattern.
3. the manufacture method of novel phase change memory according to claim 1 is characterized in that, this second dielectric layer of this planarization utilizes chemical mechanical milling method or returns lithographic technique until the step on the top of exposing this pyramidal structure.
4. the manufacture method of novel phase change memory according to claim 1 is characterized in that, this top that this pyramidal structure is exposed to this second dielectric layer is plane or pyramid.
5. the manufacture method of novel phase change memory according to claim 1 is characterized in that, should form a heating electrode on this top of this pyramidal structure of exposing, and forms the step of one second electrode on this heating electrode, also includes the following step:
This heating electrode of deposition on this pyramidal structure;
This second electrode of deposition on this heating electrode;
On this second electrode, form the photoresist pattern;
Shield as etching with this photoresist pattern, etching does not cover the zone of this heating electrode He this second electrode of this photoresist pattern, until manifesting this second dielectric layer; And
Remove this photoresist pattern.
6. the manufacture method of a novel phase change memory is characterized in that, includes the following step:
First dielectric layer is provided, and in this first dielectric layer, has first electrode;
On this first dielectric layer and this first electrode, deposit diffused barrier layer;
Sediment phase change layer on this diffused barrier layer;
This phase change layer of etching and this diffused barrier layer, until manifesting this first dielectric layer, and this phase change layer is etched into pyramidal structure, wherein the top of this pyramidal structure is away from the position of this first electrode, the bottom of this pyramidal structure is near the position of this first electrode, and the area of this bottom is greater than the area on this top;
Deposition stops layer on this phase change layer;
Depositing second dielectric layer stops on the layer in this;
This second dielectric layer of planarization is until the top of exposing this pyramidal structure; And
Form heating electrode on this top of this pyramidal structure of exposing, and form second electrode on this heating electrode, wherein the material of this heating electrode is the high value electric conducting material;
Described high value electric conducting material comprises: titanium, tantalum, titanium nitride, tantalum nitride, nitrogen titanium aluminide, titanium carbonitride, tungsten tantalum, tungsten titanium, tantalum oxide, polysilicon, tantalum silicon oxide, carbon, carbon silicide, germanium nitride.
7. the manufacture method of novel phase change memory according to claim 6, it is characterized in that this phase change layer of this etching and this diffused barrier layer are until manifesting this first dielectric layer, and this phase change layer is etched into the step of pyramidal structure, includes the following step:
On this phase change layer, form the photoresist pattern;
Shield as etching with this photoresist pattern, wait tropism's etching not cover the zone of this phase change layer He this diffused barrier layer of this photoresist pattern, make this phase change layer form this pyramidal structure; And
Remove this photoresist pattern.
8. the manufacture method of novel phase change memory according to claim 6 is characterized in that, this second dielectric layer of this planarization utilizes chemical mechanical milling method or returns lithographic technique until the step on the top of exposing this pyramidal structure.
9. the manufacture method of novel phase change memory according to claim 6 is characterized in that, this top that this pyramidal structure is exposed to this second dielectric layer is plane or pyramid.
10. the manufacture method of novel phase change memory according to claim 6 is characterized in that, should form heating electrode on this top of this pyramidal structure of exposing, and forms the step of second electrode on this heating electrode, also includes the following step:
This heating electrode of deposition on this pyramidal structure;
This second electrode of deposition on this heating electrode;
On this second electrode, form the photoresist pattern;
Shield as etching with this photoresist pattern, etching does not cover the zone of this heating electrode He this second electrode of this photoresist pattern, until manifesting this second dielectric layer; And
Remove this photoresist pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006100002727A CN101000944B (en) | 2006-01-10 | 2006-01-10 | Phase storage element and manufacturing method thereof |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN2006100002727A CN101000944B (en) | 2006-01-10 | 2006-01-10 | Phase storage element and manufacturing method thereof |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| CN101000944A CN101000944A (en) | 2007-07-18 |
| CN101000944B true CN101000944B (en) | 2010-07-14 |
Family
ID=38692819
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN2006100002727A Expired - Fee Related CN101000944B (en) | 2006-01-10 | 2006-01-10 | Phase storage element and manufacturing method thereof |
Country Status (1)
| Country | Link |
|---|---|
| CN (1) | CN101000944B (en) |
Families Citing this family (11)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN101958337B (en) * | 2009-07-16 | 2012-06-20 | 中芯国际集成电路制造(上海)有限公司 | Phase change random access memory and manufacturing method thereof |
| CN101789491B (en) * | 2010-02-08 | 2012-05-09 | 中国科学院上海微系统与信息技术研究所 | Phase-change memory cell structure, preparation method thereof and preparation method of phase-change memory arrays |
| CN102664235B (en) * | 2012-04-12 | 2013-12-04 | 北京大学 | Small-electrode-structure resistance random access memory and preparation method of small-electrode-structure resistance random access memory |
| CN102832342A (en) * | 2012-09-14 | 2012-12-19 | 中国科学院上海微系统与信息技术研究所 | Phase change storage unit containing titanium silicon nitrogen (TiSiN) material layers and preparation method of phase change storage unit |
| CN103066207A (en) * | 2012-12-26 | 2013-04-24 | 北京大学 | Resistive random access memory and preparation method thereof |
| CN104900806B (en) * | 2015-06-04 | 2018-06-05 | 江苏时代全芯存储科技有限公司 | The manufacturing method of phase-change memory cell |
| CN104993049B (en) * | 2015-07-08 | 2017-08-08 | 江苏时代全芯存储科技有限公司 | Phase-change memory and its manufacture method |
| CN105489757B (en) * | 2015-12-04 | 2018-07-03 | 江苏时代全芯存储科技有限公司 | Phase-change memory structure and its manufacturing method |
| CN106997924B (en) * | 2016-01-22 | 2019-11-26 | 中芯国际集成电路制造(上海)有限公司 | Phase transition storage and its manufacturing method and electronic equipment |
| CN112635666B (en) * | 2020-12-22 | 2023-05-12 | 华中科技大学 | Phase change memory cell |
| CN113795937A (en) * | 2021-07-28 | 2021-12-14 | 长江先进存储产业创新中心有限责任公司 | Phase change memory device and forming method thereof |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114713A (en) * | 1997-01-28 | 2000-09-05 | Zahorik; Russell C. | Integrated circuit memory cell having a small active area and method of forming same |
| US20050139816A1 (en) * | 2003-12-30 | 2005-06-30 | Won-Cheol Jeong | Memory devices having sharp-tipped phase change layer patterns and methods of forming the same |
-
2006
- 2006-01-10 CN CN2006100002727A patent/CN101000944B/en not_active Expired - Fee Related
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6114713A (en) * | 1997-01-28 | 2000-09-05 | Zahorik; Russell C. | Integrated circuit memory cell having a small active area and method of forming same |
| US20050139816A1 (en) * | 2003-12-30 | 2005-06-30 | Won-Cheol Jeong | Memory devices having sharp-tipped phase change layer patterns and methods of forming the same |
Also Published As
| Publication number | Publication date |
|---|---|
| CN101000944A (en) | 2007-07-18 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| CN101000944B (en) | Phase storage element and manufacturing method thereof | |
| CN101459219B (en) | Current constricting phase change memory element structure | |
| US7835177B2 (en) | Phase change memory cell and method of fabricating | |
| CN102097587B (en) | Memory device having wide area phase change element and small electrode contact area | |
| CN101958398B (en) | Thermal protect pcram structure and methods for making | |
| TWI384664B (en) | Memory array with diode driver and method for fabricating the same | |
| KR100668846B1 (en) | Method of manufacturing phase change RAM device | |
| TWI313058B (en) | Vacuum cell thermal isolation for a phase change memory device | |
| TWI469268B (en) | Method of forming memory cell using gas cluster ion beams | |
| TWI497706B (en) | Mushroom type memory cell having self-aligned bottom electrode and diode access device | |
| CN101165936A (en) | Memory unit and its forming method | |
| CN100530739C (en) | Phase change memory unit with loop phase change material and its making method | |
| CN103069603A (en) | Phase change memory cell in semiconductor chip and method for fabricating the phase change memory cell | |
| US7858961B2 (en) | Phase change memory devices and methods for fabricating the same | |
| US7811933B2 (en) | CMOS-process-compatible programmable via device | |
| CN100524876C (en) | Phase storage element and manuafcturing method thereof | |
| CN102832342A (en) | Phase change storage unit containing titanium silicon nitrogen (TiSiN) material layers and preparation method of phase change storage unit | |
| US20120267601A1 (en) | Phase change memory cells with surfactant layers | |
| US20140367630A1 (en) | Semiconductor device and method for manufacturing same | |
| CN103137863A (en) | Phase-change random access memory device and method of manufacturing the same | |
| CN102686770A (en) | Phase change memory device suitable for high temperature operation | |
| CN103427022B (en) | The preparation method comprising the phase change storage structure of sandwich type electrode | |
| CN101916823B (en) | Phase change storage device based on antimony telluride composite phase change material and preparation method thereof | |
| CN1988200A (en) | Gas wall electrode side connection phase shift storage and its producing method | |
| CN103441215B (en) | Phase change storage structure of sandwich type blade-like electrode and preparation method thereof |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| C06 | Publication | ||
| PB01 | Publication | ||
| C10 | Entry into substantive examination | ||
| SE01 | Entry into force of request for substantive examination | ||
| C14 | Grant of patent or utility model | ||
| GR01 | Patent grant | ||
| CF01 | Termination of patent right due to non-payment of annual fee | ||
| CF01 | Termination of patent right due to non-payment of annual fee |
Granted publication date: 20100714 Termination date: 20170110 |