CN101027761B - 使半导体结构平坦化以形成替代金属栅 - Google Patents

使半导体结构平坦化以形成替代金属栅 Download PDF

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CN101027761B
CN101027761B CN200580025244.4A CN200580025244A CN101027761B CN 101027761 B CN101027761 B CN 101027761B CN 200580025244 A CN200580025244 A CN 200580025244A CN 101027761 B CN101027761 B CN 101027761B
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layer
metal
sacrificial
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electrode
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CN101027761A (zh
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J·卡瓦利厄斯
J·布拉斯克
M·多齐
U·沙阿
C·巴恩斯
M·梅茨
S·达塔
R·乔
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Intel Corp
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Abstract

可用金属栅电极代替包括氮化物和填充层的牺牲栅结构。可再次用由填充层覆盖的氮化物层覆盖金属栅电极。氮化物和填充层的替代可再引入应变并提供蚀刻停止。

Description

使半导体结构平坦化以形成替代金属栅
背景
本发明涉及制造半导体器件的方法，尤其涉及制造具有金属栅电极的半导体器件的方法。
具有由二氧化硅形成的极薄栅电介质的MOS场效应晶体管会经历不可接受的栅漏电流。用某些高介电常数(高K值)的介电材料代替二氧化硅形成栅电介质可减小栅漏电。如这里所使用的，“高k值电介质”意思是具有高于10的介电常数。然而，在高k值介电膜最初形成时，它可能具有轻微缺陷的分子结构。为了修补这种膜，有必要将其在比较高的温度下进行退火处理。
因为这种高k值介电层可能与多晶硅不兼容，所以可能期望在包括高k值栅电介质的器件中使用金属栅电极。当制造包括金属栅电极的CMOS器件时，或许有必要用不同的材料制造NMOS栅电极和PMOS栅电极。一种替代栅工艺可以用来由不同的材料形成栅电极。在该工艺中，选择性地去除由一对隔片夹在中间的第一多晶硅层直到第二多晶硅层以便在隔片间形成沟槽。用第一金属填充该沟槽。然后去除第二多晶硅层，并用不同于第一金属的第二金属代替第二多晶硅层。
因此，需要用于形成替代金属栅电极的另一种方式。
附图简述
图1A-1R表示当执行本发明的实施方式时可形成的结构的横截面。
在这些附图中所示的特征不是按比例绘制的。
详细描述
图1A-1R示出当执行本发明的方法的实施方式时可形成的结构。最初，高k值栅介电层170和金属牺牲层169形成于衬底100上，生成图1A的结构。或者，虽然未示出，但在该部分流程中可携带一假栅电介质(例如，20-30埃的SiO2层)，并在替代栅工艺中由高k值电介质代替。衬底100可包括体硅子结构或硅-绝缘体子结构。或者，衬底100可包括其它材料，与硅结合或不与硅结合皆可，诸如锗、锑化铟、碲化铅、砷化铟、磷化铟、砷化镓或锑化镓等。虽然这里描述了可形成衬底100的材料的几个例子，但是，可用作在其上构造半导体器件的基础的任何材料都落入本发明的精神和范围内。
可用于形成高k值栅介电层170的一些材料包括：氧化铪、氧化硅铪、氧化镧、氧化铝镧、氧化锆、氧化硅锆、氧化钽、氧化钛、氧化钛锶钡、氧化钛钡、氧化钛锶、氧化钇、氧化铝、氧化钽钪铅以及铌酸铅锌。特别优选的是氧化铪、氧化锆、氧化钛和氧化铝。虽然这里描述了可用于形成高k值栅介电层170的材料的几个例子，但该层可由能够减小栅漏电的其它材料形成。层170具有高于10的介电常数，在本发明的一个实施例中是在15至25之间。
可利用常规的沉积方法，例如，常规的化学气相沉积(“CVD”)、低压CVD或物理气相沉积(“PVD”)工艺，在衬底100上形成高k值栅介电层170。较佳地是，采用常规的原子层CVD工艺。在这种工艺中，可将金属氧化物前体(例如，金属氯化物)和蒸气以选定的流速供给CVD反应器，然后在选定的温度和压力下工作以生成衬底100和高k值栅介电层170之间的原子级光滑界面。CVD反应器应工作足够长的时间以形成具有期望厚度的层。在大部分应用中，例如，高k值栅介电层170厚度小于约60埃，在一个实施例中，厚度介于约5埃至40埃之间。
金属牺牲层169可形成于介电层170上。金属牺牲层169可以是能够承受高温(高于450℃)而不与上覆的材料反应的任何金属。作为一个例子，金属牺牲层169可由氮化钛形成。在一个实施例中，层169可通过溅射来形成。在另一个实施例中，层169通过原子层沉积来形成。
在高k值栅介电层170和金属牺牲层169形成于衬底100上之后，如图1B所示，牺牲层171形成于高k值栅介电层170上。在该实施例中，硬掩模层172随后形成于牺牲层171上，生成图1B结构。牺牲层171可包括多晶硅、氮化硅、硅锗或锗，且可利用常规的沉积工艺沉积在金属牺牲层169上。牺牲层171的厚度可例如介于约100埃至约2000埃，并且在一个实施例中，介于约500埃至1600埃。在另一个实施例中，牺牲层171可形成于稍后在栅替代时被代替的假栅电介质上。
硬掩模层172例如可包括厚度在约100埃至约1000埃之间的氮化硅，在一个实施例中是在约200埃至350埃之间。硬掩模层172可形成于牺牲层171上。
然后使牺牲层171和硬掩模层172图案化以形成图案化硬掩模层130、131以及图案化牺牲层104、106和169-如图1C所示。常规的湿法或干法蚀刻工艺可用于去除硬掩模层172、金属牺牲层169和牺牲层171的未保护部分。在该实施例中，在这些层蚀刻之后，去除了高k值栅介电层170的暴露部分174。
虽然高k值栅介电层170的暴露部分174可利用干法或湿法技术来去除，但难以在不对邻近结构产生有害影响的情况下利用这种技术来蚀刻该层。难以利用干法蚀刻工艺来选择性地蚀刻高k值栅介电层170一直到下面的衬底为止，而湿法蚀刻技术可各向同性地蚀刻高k值栅介电层170-以不期望的方式底切上面的牺牲层104、106。
为了减小高k值栅介电层170的横向去除，在该层的暴露部分174被蚀刻时，可对高k值栅介电层170的暴露部分174进行改性处理，以促进它相对于该层的覆盖部分175的选择性去除。暴露部分174可通过在蚀刻牺牲层171之后向高k值栅介电层170的该部分添加杂质的方式来进行改性处理。等离子体增强化学气相沉积(“PECVD”)工艺可用于向高k值栅介电层170的暴露部分174添加杂质。在这种PECVD工艺中，在引燃等离子体之前将卤素气体或卤化物气体(或这些气体的组合)送入反应器。反应器应在适当的条件下(例如温度、压力、射频和功率)工作足够的时间以使暴露部分174改性来确保它相对于其它材料的选择性去除。在一个实施例中，采用了低功率PECVD工艺，例如，低于约200瓦。
在一个实施例中，将溴化氢(“HBr”)和氯(“Cl2”)气体以适当的流速送入反应器以确保由这些气体生成的等离子体以期望的方式对暴露部分174改性处理。可施加介于约50瓦至100瓦之间的晶片偏压(例如，约100瓦)足够长的时间以完成暴露部分174的期望的转变。延续时间短于约一分钟等离子体接触，或许短短的5秒钟，即足以导致该转换。
当对暴露部分174改性之后，可将其去除。所加杂质的存在使得暴露部分相对于覆盖部分175能够选择性地蚀刻生成图1D的结构。在一个实施方式中，暴露部分174是通过将其暴露于较强的酸——例如基于卤化物的酸(诸如氢溴酸或盐酸之类的)或磷酸——中来去除。当采用基于卤化物的酸时，该酸较佳地包含约0.5％至约10％体积的HBr或HCl-约5％体积更佳。采用这种酸的蚀刻工艺可在室温或接近室温下发生，并持续约5至约30分钟-尽管如果需要的话可采用更长的暴露。当采用磷酸时，该酸可包含约75％至约95％体积的H3PO4。采用这种酸的蚀刻工艺例如可在约140℃至约180℃之间发生，并且在一个实施例中在约160℃发生。当采用这种酸时，暴露步骤可持续约30秒至约5分钟-对于20埃厚的膜约1分钟。
图1D表示在制造互补金属氧化物半导体(“CMOS”)时形成的中间结构。该结构包括图1E所示衬底100的第一部分101和第二部分102。隔离区103将第一部分101与第二部分102分开。隔离区103可包括二氧化硅或可分离晶体管的有源区域的其它材料。第一牺牲层104形成于第一高k值栅介电层105上，而第二牺牲层106形成于第二高k值栅介电层107上。硬掩模130、131形成于牺牲层104、106上。
在形成图1D的结构后，隔片可形成于牺牲层104、106的相对的侧上。当这些隔片包括氮化硅时，它们可以下面的方式形成。首先，将基本均匀厚度(例如，小于约1000埃厚)的氮化硅层沉积在整个结构上，产生图1E所示的结构。常规的沉积工艺可用于形成该结构。
在一个实施例中，氮化硅层134在没有首先在衬底100和层104、106上形成缓冲氧化物的情况下直接沉积在衬底100和牺牲层104、106的相对的侧上。然而，在另一个实施例中，这种缓冲氧化物层可在形成层134前形成。类似地，虽然在图1E中未示出，但在对层134进行蚀刻前，第二氧化物可形成于层134上。如果使用了的话，这种氧化物可使后面的氮化硅蚀刻步骤能够生成L形隔片。
氮化硅层134可利用常规的工艺来蚀刻以各向异性蚀刻氮化硅，形成图1F的结构。作为该蚀刻步骤的结果，牺牲层104由一对侧壁隔片108、109夹在中间，而牺牲层106由一对侧壁隔片110、111夹在中间。
然后用氮化物蚀刻停止层180覆盖图1F的结构以形成图1G的结构。层180可以与层134相同的方式来形成。
正如一般所做的，期望在牺牲层104、106上形成隔片108、109、110、111之前进行多次的掩模和离子注入步骤(图1H)，以在层104、106附近形成轻注入区135a-138a(最后将作为器件的源区和漏区的尖端区)。同样如一般所做的，在形成隔片108、109、110、111之后，可通过将离子注入到衬底100的部分101和102中然后应用适当的退火步骤来形成源区和漏区135-138。
用于在衬底100的部分101中形成n-型源区和漏区的离子注入和退火工序可同时将牺牲层104掺杂为n-型。类似地，用于在衬底100的部分102中形成p-型源区和漏区的离子注入和退火工序可同时将牺牲层106掺杂为p-型。当用硼掺杂牺牲层106时，该层应包括足够浓度的该元素以确保后面用于去除n-型牺牲层104的湿法蚀刻工艺不去除大量的p-型牺牲层106。
退火将激活先前引入到源区和漏区以及尖端区以及引入牺牲层104、106的掺杂物。在较佳的实施例中，应用的是在超过1000℃的温度下发生的快速热退火，在1080℃下发生的最优。除激活掺杂剂外，这种退火可改变高k值栅介电层105、107的分子结构以形成性能改善的栅介电层。
由于牺牲金属层169的安置，更好性能的介电层170可从这些高温步骤中得到，而在高介电常数的介电层170和牺牲层171之间没有显著的反应。
在形成隔片108、109、110、111和层180之后，可将介电层112沉积在器件上，生成图1H的结构。介电层112可包括二氧化硅或低k值材料。介电层112可用磷、硼或其它元素来掺杂，并且可利用高密度等离子体沉积工艺来形成。至该工艺阶段，就已形成了由牺牲区139、140、141、142覆盖的源区和漏区135、136、137、138。这些源区和漏区可通过向衬底注入离子、然后将它们激活来形成。或者，如对于本领域的技术人员显而易见的，可采用外延生长工艺来形成源区和漏区。
将介电层112从硬掩模130、131上去除，硬掩模130、131进而从图案化的牺牲层104、106上去除，形成图1I的结构。可将常规的化学机械抛光(“CMP”)应用于去除该部分介电层112和硬掩模130、131。可将硬掩模130、131去除以暴露图案化的牺牲层104、106。当抛光介电层112时，可从层104、106的表面上抛光除去硬掩模130、131-因为到了工艺的这个阶段，它们已解决了它们的问题。
在形成图1I结构后，去除牺牲层104以生成位于侧壁隔片108、109之间的沟槽113-产生图1J所示的结构。
在一个实施例中，应用的是相对于牺牲层106对层104有选择性的湿法蚀刻工艺，以去除层104和169而不去除大量的层106。
当牺牲层104掺杂为n-型，而牺牲层106掺杂为p-型(例如，用硼)时，这种湿法蚀刻工艺可包括将牺牲层104在足够的温度下暴露在包括氢氧化物源的水溶液中足够长时间以充分地去除所有的层104。该氢氧化物源可包括以去离子水为溶剂的约2％至约30％体积浓度的氢氧化铵或氢氧化四烃基铵，例如，氢氧化四甲基铵(“TMAH”)。
任何剩余的牺牲层104可通过将其暴露在一种维持在约15℃至约90℃之间的温度下(例如约40℃以下)包括以去离子水为溶剂的约2％至约30％体积浓度的氢氧化铵的溶液中来选择性地去除。在较佳地持续至少一分钟的该暴露步骤期间，可能必须施加约10kHz至约2000kHz之间的频率的声能，消耗约在1至约10瓦/平方厘米之间。
在一个实施例中，具有约1350埃厚度的牺牲层104可通过将其在约25℃下暴露在包括以去离子水为溶剂的15％体积浓度的氢氧化铵的溶液中30分钟、同时施加约1000kHz的声能(消耗约5瓦/平方厘米)来选择性地去除。这种蚀刻工艺可在不去除有意义的量的p-型牺牲层106的情况下充分地去除所有的n-型牺牲层104。
作为一个选择，可将牺牲层104通过将其暴露在一种维持在约60℃至约90℃之间的温度下、包括以去离子水为溶剂的约20％至约30％体积浓度的TMAH的溶液中至少一分钟来选择性地去除。通过将具有约1350埃厚度的牺牲层104在约80℃下暴露在包括以去离子水为溶剂的25％体积浓度的TMAH的溶液中约2分钟、同时施加约1000kHz的声能(耗能约5瓦/平方厘米)来选择性地去除牺牲层104，可充分地去除所有的层104而不去除大量的层106。第一高k值栅介电层105应足够厚，以防止用于去除牺牲层104的蚀刻剂到达位于第一高k值栅介电层105之下的沟道区。
金属牺牲层169也可通过选择性地蚀刻来去除。在一些实施例中，可不去除层169。在一些实施例中，可在形成替代金属栅之前去除介电层105。在这种情况下，可在形成替代栅之前形成金属氧化物栅电介质。
在所示实施例中，n-型金属层115直接形成于层105上以填充沟槽113并生成图1K的结构。n-型金属层115可包括任何一种可用其获得金属NMOS栅电极的n-导电材料。n-型金属层115较佳地具有使其适合用于制造半导体器件金属NMOS栅电极的热稳定性。
可用于形成n-型金属层115的材料包括：铪、锆、钛、钽、铝及其合金，例如包括这些元素的金属碳化物，即，碳化铪、碳化锆、碳化钛、碳化钽、碳化铝。n-型金属层115可利用已熟知的PVD或CVD工艺(例如，常规的溅射或原子层CVD工艺)形成于第一高k值栅介电层105上。如图1L所示，除填充在沟槽113中的n-型金属层115外，将n-型金属层115去除。可经由湿法或干法蚀刻工艺或适当的CMP操作将层115从器件的其它部分去除。当从其表面去除层115时，电介质112可用作蚀刻或抛光停止。
n-型金属层115可用作具有介于约3.9eV至约4.2eV之间的功函、介于约100埃至约2000埃厚(在一个实施例中，介于约500埃至1600埃)的金属NMOS栅电极。虽然图1J和1K表示n-型金属层115可填充所有的沟槽113的结构，但在另一个实施例中，n-型金属层115可仅填充部分沟槽113，同时其余的沟槽用例如钨、铝、钛或氮化钛等易于抛光的材料填充。利用较高导电率的填充金属代替功函金属可提高栅叠层的总的导电率。在这一实施例中，用作功函金属的n-型金属层115约50埃至1000埃厚，例如至少100埃厚。
在其中沟槽113包括功函金属和沟槽填充金属两者的实施例中，可认为所得的金属NMOS栅电极包括功函金属和沟槽填充金属两者的组合。如果将沟槽填充金属沉积在功函金属上，则沉积时沟槽填充金属可覆盖整个器件，形成如同图1K结构的结构。该沟槽填充金属随后必须被向后抛光使得它仅填充沟槽，形成如同图1L结构的结构。
在所示实施例中，在沟槽113中形成n-型金属层115之后，将牺牲层106去除以生成位于侧壁隔片110、111之间的沟槽150-产生图1M所示的结构。在较佳的实施例中，层106在足够的温度下(例如，在约60℃至约90℃之间)暴露于在以去离子水为溶剂的包括约20％至30％体积的TMAH的溶液中足够长的时间，同时施加声能，以去除所有的层106而不去除大量的n-型金属层115。
或者，可应用干法蚀刻工艺以选择性地去除层106。当牺牲层106是掺杂的p-型(例如，用硼)时，这种干法蚀刻工艺可包括将牺牲层106暴露于由六氟化硫(“SF6”)、溴化氢(“HBr”)、碘化氢(“HI”)、氯气、氩气和/或氦气得到的等离子体。这种选择性干法蚀刻工艺可在平行板反应器或电子回旋共振蚀刻器中进行。
在去除牺牲层106之后，或许期望清洁第二高k值栅介电层107，例如通过将该层暴露于上述的基于过氧化氢的溶液中。可任选地，如上所述，在用p-型金属填充沟槽150之前，可在第二高k值栅介电层107上形成一覆盖层(它在沉积后可被氧化)。然而，在该实施例中，p-型金属层116直接形成于层107上以填充沟槽150并生成图1N结构。p-型金属层116可包括任何一种可用其获得金属PMOS栅电极的p-型导电材料。p-型金属层116较佳地具有使其适合用于形成半导体器件金属PMOS栅电极的热稳定特性。
可用于形成p-型金属层116的材料包括：钌、钯、铂、钴、镍、和导电金属氧化物，例如氧化钌。p-型金属层116可利用例如常规的溅射或原子层CVD工艺等已熟知的PVD或CVD工艺形成于第二高k值栅介电层107上。如图1O所示，除填充沟槽150的之外，p-型金属层116被去除。层116可经由湿法或干法蚀刻工艺或适当的CMP操作来从器件的其它部分去除，同时电介质112用作蚀刻或抛光停止。
p-型金属层116可用作具有介于约4.9eV至约5.2eV之间的功函、介于约100埃至约2000埃厚(介于500埃至1600埃之间更佳)的金属PMOS栅电极。虽然图1N和10表示其中p-型金属层116填充所有的沟槽150的结构，但在其它实施例中，p-型金属层116仅填充部分沟槽150。对于金属NMOS栅电极，可用易于抛光的材料(例如，钨、铝、钛或氮化钛)填充其余的沟槽。在这一实施例中，用作功函金属的p-型金属层116可介于约50埃至1000埃厚。如同金属NMOS栅电极，在其中沟槽150包括功函金属和沟槽填充金属两者的实施例中，可认为所得的金属PMOS栅电极包括功函金属和沟槽填充金属两者的组合。
接下来，可去除介电层112以形成图1P所示的结构。然后沉积一种新的氮化物蚀刻停止层181，如图1Q所示。在一个实施例中，层181可以是与层180同样的。然后，可沉积介电层214，如图1R所示，以形成层间电介质。层214可由与层112相同的材料以相同的方式来形成。
因为氮化物蚀刻停止层180的一部分在去除层104和106期间被去除，这一层在减小应变方面所产生的益处被消除了。因此，通过重新增加层181和层214，可以再现应变减小层和蚀刻停止层的益处。在一些实施例中，可利用任何电介质214。例如电介质214可以是诸如多孔或非多孔碳掺杂氧化物之类的具有小于5的介电常数(例如，约3.2)的低k值介电层。
尽管已参考有限数量的实施例对本发明进行了描述，但本领域的技术人员可以由这些实施例明了众多的修改和变体。所附权利要求书旨在涵盖落入本发明的真正精神和范围内的所有修改和变体。

Claims (12)

1.一种方法，包括：
形成高K值栅介电层；
在所述高K值栅介电层上形成金属牺牲层，所述金属牺牲层是能够承受高于450℃的温度而不与上覆的材料反应的金属；
在所述金属牺牲层上形成牺牲栅结构；
使用所述栅结构作为掩模形成源极和漏极，并且对所述源极、漏极和高K值栅介电层进行退火；
去除所述金属牺牲层和牺牲栅结构；
用金属栅电极代替所述金属牺牲层和牺牲栅结构；
用氮化物层覆盖所述金属栅电极；以及
用层间电介质覆盖所述氮化物层，
其中，所述层间电介质填充所述金属栅电极之间的区域。
2.如权利要求1所述的方法，其特征在于，所述方法包括用介电常数小于5的层间电介质覆盖所述氮化物层。
3.如权利要求1所述的方法，其特征在于，所述方法包括形成一对牺牲栅结构，以及用适于形成NMOS和POMS晶体管的金属栅电极代替所述牺牲栅结构。
4.如权利要求1所述的方法，其特征在于，形成牺牲栅结构的步骤包括形成具有侧壁隔片的多晶硅栅结构。
5.一种方法，包括
形成高K值栅介电层；
在所述高K值栅介电层上形成金属牺牲层，所述金属牺牲层是能够承受高于450℃的温度而不与上覆的材料反应的金属；
在所述金属牺牲层上形成一对牺牲栅结构；
使用所述栅结构作为掩模形成源极和漏极，并且对所述源极、漏极和高K值栅介电层进行退火；
去除所述金属牺牲层和牺牲栅结构；
用金属栅电极代替所述金属牺牲层和牺牲栅结构；
用氮化物层覆盖所述金属栅电极；以及
用层间电介质覆盖所述氮化物层，
其中，所述层间电介质填充所述金属栅电极之间的区域。
6.如权利要求5所述的方法，其特征在于，所述方法包括形成一对牺牲栅结构，以及用适于形成NMOS和POMS晶体管的金属栅电极代替所述牺牲栅结构。
7.如权利要求5所述的方法，其特征在于，形成牺牲栅结构的步骤包括形成具有侧壁隔片的多晶硅栅结构。
8.一种半导体结构，包括：
衬底；
形成于所述衬底上的高K值栅介电层；
形成于所述高K值栅介电层上的金属栅电极，其中所述金属栅电极是通过代替形成于所述高K值栅介电层上的金属牺牲层和牺牲栅结构形成的，所述金属牺牲层是能够承受高于450℃的温度而不与上覆的材料反应的金属；
使用所述牺牲栅结构作为掩模形成的源极和漏极；
所述金属栅电极上的氮化物层；以及
所述氮化物层上的层间介电层，
其中，所述层间电介质填充所述金属栅电极之间的区域，其中，在形成所述金属栅电极之前对所述源极、漏极和高K值栅介电层进行了退火。
9.如权利要求8所述的结构，其特征在于，所述层间电介质具有小于5的介电常数。
10.如权利要求8所述的结构，其特征在于，所述结构包括一对金属栅电极，一个用于NMOS晶体管，一个用于PMOS晶体管。
11.如权利要求8所述的结构，其特征在于，所述氮化物层与所述栅电极直接接触。
12.如权利要求8所述的结构，其特征在于，所述层间电介质是碳掺杂氧化物。
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