CN101064286B - 高性能应力增强mosfet及制造方法 - Google Patents

高性能应力增强mosfet及制造方法 Download PDF

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CN101064286B
CN101064286B CN200710091566XA CN200710091566A CN101064286B CN 101064286 B CN101064286 B CN 101064286B CN 200710091566X A CN200710091566X A CN 200710091566XA CN 200710091566 A CN200710091566 A CN 200710091566A CN 101064286 B CN101064286 B CN 101064286B
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field effect
effect transistor
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D·奇丹巴尔拉奥
R·A·多纳通
W·K·汉森
K·里姆
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Core Usa Second LLC
GlobalFoundries Inc
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Abstract

本发明涉及半导体结构和制造方法，更具体地说，涉及CMOS器件，该器件具有嵌入两个栅极并且还嵌入PFET源极和漏极区域中的应力引起材料，以及不同厚度的PFET和NFET沟道。在一个实施中，该结构通过改变NFET或PFET的顶硅层的厚度，增强了器件性能。

Description

高性能应力增强MOSFET及制造方法
技术领域
本发明一般涉及半导体器件及制造方法，更具体地说，涉及在制造期间，在器件中施加拉伸和压缩应力的半导体器件及制造方法。
背景技术
半导体器件衬底中的机械应力可以调节器件性能。即，已公知半导体器件中的应力能提高半导体器件性能。因此，为了提高半导体器件性能，在n型器件(例如NFET)和/或p型器件(例如PFET)的沟道中产生拉伸应力和/或压缩应力。然而，同样的应力成分，拉伸应力或压缩应力，对n型器件和p型器件的性能有不同的影响。
例如，已公知，当在硅层(或覆层)上形成器件时，在硅衬底顶上弛豫的SiGe层上外延生长该硅层，器件表现出更好的性能。在此系统中，硅覆层经受双轴拉伸应变。当在硅上外延生长时，未弛豫SiGe层具有与硅衬底匹配的晶格常数。通过弛豫(例如通过高温处理)，SiGe的晶格常数接近其本征晶格常数，该晶格常数比硅的晶格常数大。完全弛豫的SiGe层具有接近其本征值的晶格常数。当在其上外延生长硅时，硅层与弛豫SiGe层的更大的晶格常数匹配，这向在其上形成的硅层施加物理双轴应力(例如，膨胀)。向硅层施加的此物理应力对在其上形成的器件有益(例如，CMOS器件)，因为膨胀的硅层提高了n型器件的性能，而SiGe层中更高的Ge含量提高了p型器件的性能。
为了在集成电路(IC)芯片中最优化NFET和PFET的性能，对NFET和PFET应该分别设计和应用应力成分。即，因为对NFET的性能有益的应力类型通常对PFET的性能不利。更具体地说，当器件处于拉伸状态(例如：在平面器件的电流流动方向上)，NFET的操作性能增强，而PFET的操作性能降低。为了有选择地在NFET中产生拉伸应力并且在PFET中产生压缩应力，使用了有差别的工艺和不同的材料组合。
例如，建议用沟槽隔离结构分别在NFET和PFET中形成合适的应力。当使用该方法时，用于NFET器件的隔离区域包括第一隔离材料，该材料在NFET器件的纵向(例如，平行于电流流向)和横向(例如，垂直于电流流向)产生第一类型的机械应力。另外，为PFET提供第一隔离区域和第二隔离区域，并且这些隔离区域的每一个在PFET器件的横向和纵向中提供唯一的机械应力。
可选地，栅极侧壁上的衬里旨在有选择地引起适当的应力，在FET器件的沟道中引起合适的应力(例如，参见Ootsuka等人的IEDM2000，P.575)。通过提供衬里，以比作为沟槽隔离填充技术的结果提供的应力更近的方式向器件提供合适的应力。
虽然这些方法提供的结构具有向NFET器件施加的拉伸应力和沿PFET器件的纵向施加的压缩应力，但是他们要求附加材料和/或更复杂的工艺，因此导致了更高的成本。另外，在此情况下施加的应力水平典型地为中等水平(即，在100s MPa的量级)。因此，希望提供更成本有效的和更简单的方法用于在NFET和PFET沟道中分别产生大的拉伸和压缩应力。
发明内容
本发明的第一方面，一种制造半导体结构的方法包括：在P型场效应晶体管(PFET)沟道区域和N型场效应晶体管(NFET)沟道区域中，同时形成具有下应力引起材料的分层结构。该方法还包括在PFET沟道区域的下应力引起材料上形成层时，保护NFET沟道区域，以减小在PFET沟道区域中的应力效应。在NFET沟道区域和PFET沟道区域中蚀刻岛，在NFET沟道区域中形成较高的所得应力成分。在PFET沟道区域的蚀刻部分中形成应力引起材料，在PFET沟道区域中形成与NFET沟道区域相反的应力成分。
本发明的另一方面，提供了一种制造半导体结构的方法。该方法包括在NFET区域和PFET区域中的衬底上形成应力引起层并且在NFET区域和PFET区域中的应力引起层上形成顶层。该顶层在NFET区域和PFET区域中的厚度不同。在PFET区域和NFET区域的侧面中蚀刻沟槽。蚀刻后，应力引起层的弹性边弛豫在沟道区域中产生拉伸应力。薄顶层在NFET区域中导致更高的拉伸应力，并且厚顶层在PFET区域中导致很小的拉伸应力。对NFET区域用第一材料并且对PFET区域用第二材料填充沟槽。第二材料在PFET区域中产生压缩应力。
另外，本发明的另一方面，提供了一种半导体结构，该结构包括在如Si层的衬底上形成的PFET和NFET沟道。PFET和NFET器件在沟道区域中具有相同材料的分层结构，在PFET沟道区域中相同材料的顶层厚于NFET沟道区域的顶层。PFET沟道区域和NFET沟道区域的沟槽不同。
附图说明
图1a到1i表示根据本发明形成器件的制造工艺；
图2a示出了根据本发明的NFET器件中的应力位置；
图2b示出了根据本发明的应力作为到NFET器件的栅极中心的纵向距离的函数的曲线图；
图3示出并且比较了根据本发明的平均沟道应力作为应力引起层，例如，假晶SiGe层上的硅层厚度的函数。
具体实施方式
本发明旨在半导体器件和制造方法，其在CMOS的NFET沟道中提供拉伸应力并且在PFET沟道中提供压缩应力。在本发明的实施例中，可以在相同的衬底上使用类似的工艺步骤获得在NFET和PFET沟道中形成的应力，从而降低了用于生产此类器件的整个材料的成本和时间。在实施例中，在形成NFET和PFET的区域中的硅层中形成沟道。然后分开并且有选择地处理该器件的沟道，这样以便一个器件被覆盖时，可以蚀刻并填充另一器件以便获得期望的性能。通过应用这些技术，分别在NFET和PFET的沟道中的覆盖外延生长层中导致拉伸或压缩应力。在一个实施例中，允许PFET的覆盖硅层比NFET相应的层生长的更厚。本发明的此制造工艺导致器件具有提高的沟道性能。
图1a到1i表示根据本发明形成器件的制造工艺。在图1a中，提供包括如绝缘体上硅(SOI)层10等的衬底。还可以在SOI10上形成可选的掩埋氧化物层(BOX)12，在BOX12上具有硅层14。图1a还示出了在Si层14上外延生长的假晶SiGe层16，随后具有另一外延硅层18。
在实施例中，层的厚度有不同的范围。例如BOX12在到
Figure S07191566X20070405D000042
之间，硅层14在
Figure S07191566X20070405D000043
到之间，优选厚度为
Figure S07191566X20070405D000045
另外，SiGe层16可以在到 到
Figure S07191566X20070405D000049
之间，优选
Figure S07191566X20070405D0000410
然而，应该明白，这些层的厚度可以依赖于器件的不同设计参数改变。
在实施中，以常规方式外延生长假晶SiGe层16。Ge含量与Si含量的比率大于0％，本发明的预期范围在20％-30％之间。可以通过任何选择性外延硅形成技术以常规方式沉积假晶SiGe层16上的硅层18，例如可以使用快速热化学气相沉积(RTCVD)或分子束外延(MBE)以外延生长器件优质硅。
图1b示出了由浅沟槽隔离(STI)20形成的分离沟道(或器件区域)。通过包括光刻和蚀刻步骤的常规构图工艺形成绝缘沟槽20。例如，对掩埋氧化物使用衬垫氧化，衬垫氮化物沉积，基于光刻的构图，叠层的反应离子蚀刻(RIE)的标准技术，来构图叠层14，16，18以形成STI20。然后，可以使用例如衬里沉积、填充沉积和化学机械抛光，来形成STI20。STI形成工艺在技术上已公知。
图1c示出了对PFET叠层的Si层16的修改。在此工艺中，在NFET区域上设置掩模22。在PFET区域的Si层18上有选择地生长外延Si，结果生成无缝新Si层24。新形成的层24与NFET区域中的顶层Si层16相比允许其厚度不同。优选，Si层24比NFET区域的Si层16厚，对于Si层24具有在
Figure S07191566X20070405D000051
到
Figure S07191566X20070405D000052
的厚度范围，在NFET Si层18和PFET Si层24层之间具有至少
Figure S07191566X20070405D000053
的差别。
图1d到1i示出栅极结构的制造工艺，包括分别用于NFET和PFET沟道的源极和漏极(S/D)区域。参考图1d，通过包括光刻和蚀刻步骤的常规构图工艺在NFET和PFET区域两者中构图SiN覆盖的(28)多晶硅栅极26。通过实例，在该结构上形成由SiN28保护层覆盖的多晶硅层。应用光刻工艺，该工艺需要在SiN覆盖的多晶硅层上应用光致抗蚀剂，向辐射图形曝光光致抗蚀剂，并且利用常规的抗蚀剂显影剂显影图形。在光刻步骤之后，可以使用如RIE、等离子体蚀刻、离子束蚀刻或激光烧蚀的常规蚀刻工艺，以将图形转移到NFET区域和PFET区域的有源区域以形成多晶硅栅极26。然后形成用作蚀刻停止材料的侧壁隔离物30。同样以常规形式形成覆层28和多晶硅侧壁隔离物30。在此工艺中，在该结构上沉积牺牲体材料。在一个实施例中，牺牲材料是形成SiN元件28和30的氮化物材料(例如Si3N4)。可以以常规方式形成层28，30，例如通过使用硅烷源的化学气相沉积(CVD)。适合用于形成氮化物层的其它技术包括LPCVD，和常压CVD(APCVD)。分别覆盖NFET和PFET区域中的下层16和24的多晶硅栅极26及其两个侧壁隔离物30的尺寸在
Figure S07191566X20070405D000054
到
Figure S07191566X20070405D000055
的范围内，因为隔离物的优选尺寸为
Figure S07191566X20070405D000056
所以剩下的栅极26的尺寸在
Figure S07191566X20070405D000057
到
Figure S07191566X20070405D000058
的范围内，NFET和PFET区域两者都优选
Figure S07191566X20070405D000059
应该明白，这适用于围绕标称值中心的栅极长度(技术上的最小尺寸)。例如，对于65nm技术，
Figure S07191566X20070405D0000510
是合理的栅极长度。
参考图1e，在NFET沟道中制备S/D沟槽前在PFET区域上设置硬掩模22。向下蚀刻NFET中邻近由层16，18，28，30形成的叠层的区域，希望直到硅层14，即使有些过度蚀刻也是可以接受的。此蚀刻在SiGe层边缘引起弹性驰豫，结果在上硅层上形成拉伸应变。
图1f示出了在由SiGe和Si层形成的栅极岛之间的S/D沟槽中，选择生长外延硅32后的器件。以上述尺度看，最终的栅极岛导致
Figure S07191566X20070405D0000511
到之间的纵向尺寸，优选
Figure S07191566X20070405D0000513
在NFET区域的栅极岛中的假晶SiGe层16向在沟道区域中的外延生长硅18上施加拉伸应力，导致提高的NFET器件性能。
图1g，类似于图1d，示出了PFET区域S/D的制备。在此工艺步骤中，在NFET区域上设置保护硬掩模22，并且向下蚀刻邻近由层16，24，26，28，30形成的叠层的S/D沟槽，希望直到硅层14。由于SiGe层上的上硅层比NFET区域的硅层厚，因此在PFET区域的硅沟道上施加的拉伸应力较小。
图1h示出了PFET器件的已填充S/D沟槽。相对于NFET区域，这些沟槽由外延生长的SiGe34填充，在一个实施例中，与层24基本齐平。这些元件的纵向尺度类似于上述用于NFET区域的尺度。由层16和24形成的PFET栅极岛具有
Figure S07191566X20070405D000061
到
Figure S07191566X20070405D000062
之间的最终尺寸，优选。SiGe材料34在PFET器件的硅沟道上引起压缩应力，结果提高了PFET器件的性能。
图1i示出已制造的CMOS器件。eSiGe材料34相对于沟槽中硅和锗的总量的比率可以在高于0％的任何锗之间变化。
图2a示出了根据本发明的NFET器件中的应力位置。如图2a所示，拉伸应力存在于NFET沟道中，未驰豫SiGe区域处在压缩下。更具体地说，在本发明的结构中，SiGe层16的晶格结构与下硅层14的晶格结构匹配。这导致SiGe层16和周围的区域处在压缩应力下。在蚀刻S/D沟槽(或阱)后，SiGe层的边缘将进行弹性弛豫，导致沟道中硅层18上的拉伸应力。
图2b示出了应力作为到NFET器件栅极中心的纵向距离的函数曲线。对于锗含量为20％，并且Si层18的厚度为
Figure S07191566X20070405D000064
的器件，本发明提供300MPa范围内的拉伸应力。在一个实施例中，在Si层18中纵向应力成分(从源极到漏极的电流流动方向上的应力)的优选范围优选大于100MPa。图2b还显示拉伸应力横向延伸到外延生长的硅元件32中，并且高于100MPa的拉伸应力向上到达元件32中的处，并且在从栅极边缘的处达到弛豫(没有引起应力)。
图3示出了位于上面的硅层18和24的纵向上的应力曲线。如此曲线所示，SiGe层的Ge含量的范围从20％到30％。NFET中的上层硅层的厚度范围从约
Figure S07191566X20070405D000071
到值得注意，在高达
Figure S07191566X20070405D000073
的Si层中获得了高应力(高于200MPa)，其范围依赖于层16中Ge的含量在约275MPa到415MPa之间，然后，当硅层变为
Figure S07191566X20070405D000074
厚时，弛豫为基本无应变区域。因此，对于在PFET中的SiGe层上的硅层优选为或更厚。
因此，在本发明的结构中，在NFET沟道中形成拉伸应力并且在PFET沟道中形成压缩应力。通过引入这样的应力，可以获得器件的高性能。另外，用本发明的工艺，可以减少制造成本从而导致高效益。
虽然以实施例的方式描述了本发明，本领域的技术人员将认识到实践本发明可以在附加权利要求的精神和范围内进行修改。例如，本发明可以容易地应用到体衬底上。

Claims (16)

1.一种制造半导体结构的方法：
在P型场效应晶体管沟道区域和N型场效应晶体管沟道区域中，同时形成包括Si顶层和SiGe底层的分层结构；
在所述P型场效应晶体管沟道区域中在所述分层结构上形成另一Si层时，保护所述N型场效应晶体管沟道区域，从而在所述P型场效应晶体管沟道区域中由所述分层结构的Si顶层和所述另一Si层无缝地形成所述P型场效应晶体管沟道区域的Si顶层；以及
在所述N型场效应晶体管沟道区域和所述P型场效应晶体管沟道区域中蚀刻岛，在所述N型场效应晶体管沟道区域中形成较高的所得应力成分；以及
在所述P型场效应晶体管沟道区域的蚀刻部分中形成SiGe材料，在所述P型场效应晶体管沟道区域中形成与所述N型场效应晶体管沟道区域相反的应力成分。
2.根据权利要求1的方法，其中所述P型场效应晶体管沟道区域厚于所述N型场效应晶体管沟道区域。
3.根据权利要求1的方法，其中所述P型场效应晶体管沟道区域具有厚于所述N型场效应晶体管沟道区域的Si顶层。
4.根据权利要求1的方法，其中所述SiGe的锗含量为从20％到30％。
5.根据权利要求1的方法，其中在所述P型场效应晶体管沟道区域中所述Si顶层的厚度为
Figure FSB00000080241200011
6.根据权利要求1的方法，其中在所述P型场效应晶体管沟道区域的蚀刻部分中形成所述SiGe材料之前，在所述P型场效应晶体管沟道区域中的Si顶层的厚度减小了在所述P型场效应晶体管沟道区域中的拉伸应力。
7.根据权利要求6的方法，其中在所述P型场效应晶体管沟道区域的蚀刻部分中的所述SiGe材料在所述P型场效应晶体管沟道区域中产生压缩应力。
8.根据权利要求1的方法，其中在保护所述N型场效应晶体管沟道区域时提供所述蚀刻所述P型场效应晶体管沟道区域的步骤和所述在所述P型场效应晶体管沟道区域的蚀刻部分中形成SiGe材料的步骤。
9.一种制造半导体结构的方法：
在N型场效应晶体管区域和P型场效应晶体管区域中的衬底上形成SiGe层；
在所述N型场效应晶体管区域和所述P型场效应晶体管区域中的所述SiGe层上形成Si顶层，所述Si顶层在所述P型场效应晶体管区域中比在所述N型场效应晶体管区域中的厚；
在所述P型场效应晶体管区域的源极和漏极区域以及所述N型场效应晶体管区域的源极和漏极区域处蚀刻沟槽，所述沟槽的所述蚀刻在所述N型场效应晶体管区域中产生拉伸应力并且在所述P型场效应晶体管区域中产生减小的拉伸应力；以及
对所述N型场效应晶体管区域用第一材料并且对所述P型场效应晶体管区域用第二材料填充所述沟槽，所述第一材料在所述N型场效应晶体管区域中不影响由所述沟槽的所述蚀刻产生的拉伸应力，所述第二材料在所述P型场效应晶体管区域中形成压缩应力。
10.根据权利要求9的方法，其中通过在所述P型场效应晶体管区域上沉积或生长更多的材料，在所述P型场效应晶体管区域中形成较厚的Si顶层，同时保护所述N型场效应晶体管区域，形成所述P型场效应晶体管区域的所述Si顶层。
11.根据权利要求10的方法，其中在所述P型场效应晶体管区域中所述沟槽的蚀刻后，所述P型场效应晶体管区域中的较厚的Si顶层减少了沟道中由所述SiGe层产生的应力。
12.根据权利要求9的方法，其中所述第二材料是硅锗合成物。
13.根据权利要求12的方法，其中所述第一材料是硅。
14.根据权利要求9的方法，其中所述Si顶层的厚度在50到
Figure FSB00000080241200021
的范围内变化。
15.一种半导体结构，包括P型场效应晶体管器件和N型场效应晶体管器件，所述P型场效应晶体管器件和所述N型场效应晶体管器件在沟道区域中具有包括Si顶层和SiGe底层的分层结构，在所述P型场效应晶体管沟道区域中的Si顶层厚于所述N型场效应晶体管沟道区域的Si顶层，并且所述P型场效应晶体管的在源极和漏极区域处的沟槽填充物为SiGe，所述N型场效应晶体管的在源极和漏极区域处的沟槽填充物为Si。
16.根据权利要求15的结构，其中与所述N型场效应晶体管沟道区域的应力相比，所述P型场效应晶体管沟道区域中的所述Si顶层在沟槽蚀刻后减少了由所述Si顶层下面的所述SiGe底层产生的应力。
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US7608489B2 (en) 2009-10-27
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US20100013024A1 (en) 2010-01-21
US7791144B2 (en) 2010-09-07

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